LMU112

LMU112 LODEV | Alldatasheet

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12 x 12-bit Parallel Multiplier Multipliers 08/16/2000–LDS.112-K1 ❑❑❑❑❑ 25 ns Worst-Case Multiply Time ❑❑❑❑❑ Low Power CMOS Technology ❑❑❑❑❑ Replaces Fairchild MPY112K ❑❑❑❑❑ Two’s Complement or Unsigned Operands ❑❑❑❑❑ Three-State Outputs ❑❑❑❑❑ Package Styles Available:

• 48-pin PDIP
• 52-pin PLCC, J-Lead FEATURES DESCRIPTION LMU112 12 x 12-bit Parallel MultiplierDEVICES INCORPORATED The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B). Two’s complement or unsigned magnitude operands are accommo- dated via the operand control bit (TC) LMU112 B LOCK DIAGRAM A REGISTERCLK A CLK B 12 12 OE B 11-0A 11-0 R 23-8 TC FORMAT ADJUST B REGISTER RESULT REGISTER which is loaded along with the B operands. The operands are specified to be in two’s complement format when TC is asserted and unsigned magnitude when TC is deasserted. Mixed mode operation is not allowed. For two’s complement operands, the 17 most significant bits at the output of the asynchronous multiplier array are shifted one bit position to the left. This is done to discard the redundant copy of the sign-bit, which is in the most significant bit position, and extend the bit precision by one bit. The result is then truncated to the 16 MSB’s and loaded into the output register on the rising edge of CLK B. The contents of the output register are made available via three-state buffers by asserting OE. When OE is de- asserted, the outputs (R 23-8) are in the high impedance state.

12 x 12-bit Parallel Multiplier Multipliers 08/16/2000–LDS.112-K3 Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.5 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 10 20 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) O PERATING CONDITIONS To meet specified electrical and switching characteristics ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V

12 x 12-bit Parallel Multiplier Multipliers 08/16/2000–LDS.112-K4 123456789012 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 1 2345678901 2 123456789012 1234567890123456789012345678901212 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1 23456789012345678901234567890121 2 1234567890123456789012345678901212 LMU112– 60* 50 25 Symbol Parameter Min Max Min Max Min Max tMC Clocked Multiply Time 60 50 25 tPW Clock Pulse Width 15 15 10 tS Input Register Setup Time 15 15 10 tH Input Register Hold Time 3 3 1 tD Output Delay 25 25 20 tENA Three-State Output Enable Delay (Note 11) 25 25 20 tDIS Three-State Output Disable Delay (Note 11) 25 25 20 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS LMU112– 65* 55* 30* Symbol Parameter Min Max Min Max Min Max tMC Clocked Multiply Time 65 55 30 tPW Clock Pulse Width 20 20 12 tS Input Register Setup Time 15 15 12 tH Input Register Hold Time 3 3 3 tD Output Delay 30 30 25 tENA Three-State Output Enable Delay (Note 11) 30 30 25 tDIS Three-State Output Disable Delay (Note 11) 30 30 25 M ILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS HIGH IMPEDANCE INPUT tENAtDIS tD tMC tPW tHtS CLK A CLK B OE R 23-8 tPW 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *DISCONTINUED SPEED GRADE

12 x 12-bit Parallel Multiplier Multipliers 08/16/2000–LDS.112-K5 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. In- put levels below ground or above V CC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing ev- ery cycle and no load, at a 5 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

12 x 12-bit Parallel Multiplier Multipliers 08/16/2000–LDS.112-K6 48-pin

ORDERING INFORMATION

0°C to +70°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING Plastic DIP (P5) LMU112PC50 LMU112PC25 Plastic J-Lead Chip Carrier (J5) LMU112JC50 LMU112JC25 Speed 50 ns 25 ns A10 A11 VCC VCC B10 B11 TC CLK B OE R 23 R 22 R 21 R 20 R 19 CLK A GND GND R R 9 R 10 R 11 R 12 R 13 R 14 R 15 R 16 R 17 R 18 1234567 52 51 50 49 48 47 2827 29 30 31 332221 23 24 25 26 Top View NC CLK A GND GND R R 9 R 10 R 11 R 12 VCC VCC B10 B11 TC CLK B NC OE R 23 R 22 R 21 R 20 R 19 R 18 R 17 R 16 R 15 R 14 R 13 NC NC A11 A10