LF9501

LF9501 LODEV | Alldatasheet

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08/16/2000–LDS.9501-H Video Imaging Products ❑❑❑❑❑ 50 MHz Maximum Operating Frequency ❑❑❑❑❑ Programmable Buffer Length from 2 to 1281 Clock Cycles ❑❑❑❑❑ 10-bit Data Inputs and Outputs ❑❑❑❑❑ Data Delay and Data Recirculation Modes ❑❑❑❑❑ Supports Positive or Negative Edge System Clocks ❑❑❑❑❑ Expandable Data Word Width or Buffer Length ❑❑❑❑❑ Replaces Harris HSP9501 ❑❑❑❑❑ 44-pin PLCC, J-Lead FEATURES DESCRIPTION LF9501 Programmable Line BufferDEVICES INCORPORATED The LF9501 is a high-speed, 10-bit programmable line buffer. Some applications the LF9501 is useful for include sample rate conversion, data time compression/expansion, soft- ware controlled data alignment, and programmable serial data shifting. By using the MODSEL pin, two different modes of operation can be selected: delay mode and data recirculation mode. The delay mode provides a minimum of 2 to a maximum of 1281 clock cycles of delay between the input and output of the device. The data recirculation mode provides a feedback path from the data output to the data input for use as a program- mable circular buffer. By using the length control input (LC 10-0) and the length control enable (LCEN) the length of the delay buffer or amount of recirculation delay can be programmed. Providing a delay value on the LC 10-0 inputs and driving LCEN LOW will load the delay value into the length control register on the next selected clock edge. Two regis- ters, one preceeding the program- mable delay RAM and one following, are included in the delay path. There- fore, the programmed delay value should equal the desired delay minus 2. This consequently means that the value loaded into the length control register must range from 0 to 1279 (to provide an overall range of 2 to 1281). The active edge of the clock input, either positive or negative edge, can be selected with the clock select (CLKSEL) input. All timing is based on the active clock edge selected by CLKSEL. Data can be held tempo- rarily by using the clock enable (CLKEN) input. LF9501 BLOCK DIAGRAM REGISTER MUX PROGRAMMABLE DELAY RAM REGISTER DI9-0 10 10 10 10 MODSEL CLOCK GENERATOR CLKSEL CLKEN CLK OE REGISTER LCO 10-0 LCEN TO ALL REGISTERS REGISTER DO 9-0

2 08/16/2000–LDS.9501-H Video Imaging Products Outputs DO9-0 — Data Output The 10-bit data output appears on DO9-0 on the Nth clock cycle, where N is the overall delay (desired delay). Controls LCEN — Length Control Enable When LCEN is driven LOW, the next active clock edge will cause the loading of the delay value present at the LC 10-0 input. OE — Output Enable The Output Enable controls the state of DO9-0. Driving OE LOW enables the output port. When OE is HIGH, DO 9-0 is placed in a high-impedance state. The internal transfer of data is not affected by this control. MODSEL — Mode Select The Mode Select pin is used to choose the desired mode of operation: data delay mode or data recirculation mode. Driving MODSEL LOW places the device in the delay mode. The device operates as a programmable pipeline register. New data from the DI 9-0 input is loaded on every active edge of CLK. Driving MODSEL HIGH places the device in the data recirculation mode. The device operates as a programmable circular buffer. The output of the device is routed back to the input. MODSEL may be changed during device operation (synchronously), however, the required setup and hold times, with respect to CLK, must be met. SIGNAL DEFINITIONS Power V CC and GND +5 V power supply. All pins must be connected. Clock CLK — Master Clock The active edge of CLK, selected by CLKSEL, strobes all registers. All timing specifications are referenced to the active edge of CLK. Inputs DI 9-0 — Data Input 10-bit data, from the data input, is latched into the device on the active edge of CLK when MODSEL is LOW. LC 10-0 — Length Control Input The 11-bit value is used to specify the length of the delay buffer, between DI 9-0 and DO9-0, or the amount of recirculation delay. An integer value ranging from 0 to 1279 is used to select a delay ranging from 2 to 1281 clock cycles. The value placed on the LC 10-0 inputs is equal to the desired delay minus 2. The data presented on LC 10-0 is loaded into the device on the active edge of CLK, selected by CLKSEL, in conjunction with LCEN being driven LOW. CLKSEL — Clock Select The CLKSEL control allows the selection of the active edge of CLK. A LOW on CLKSEL selects negative- edge triggering of the device. Driving CLKSEL HIGH selects positive-edge triggering. All timing specifications are referrenced to the selected active edge of CLK. CLKEN — Clock Enable The Clock Enable control enables and disables the CLK input. Driving CLKEN LOW enables CLK and causes the device to operate in a normal fashion. When CLKEN is HIGH, CLK is disabled and the device will hold all internal operations and data. CLKEN may be changed during device operation (synchronously), however, the required setup and hold times, with respect to CLK, must be met. The changing of CLKEN takes effect on the active edge of CLK following the edge in which it was latched.

08/16/2000–LDS.9501-H Video Imaging Products M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –4.0 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 4.0 mA 0.4 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 125 mA ICC2 VCC Current, Quiescent (Note 7) 500 µA C IN Input Capacitance TA = 25°C, f = 1 MHz 10 pF C OUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V

4 08/16/2000–LDS.9501-H Video Imaging Products 1234567890 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1234567890 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 LF9501– 40* 31* 25 20 15 * Symbol Parameter Min Max Min Max Min Max Min Max Min Max tCYC Cycle Time 40 31 25 20 15 tPW Clock Pulse Width 15 12 10 8 6 tDS Data Input Setup Time 12 10 8 6 5 tDH Data Input Hold Time 2 2 2 2 0 tES Clock Enable to Clock Setup Time 12 10 8 6 5 tEH Clock Enable to Clock Hold Time 2 2 2 2 0 tLS Length Control Input Setup Time 13 10 8 6 5 tLH Length Control Input Hold Time 2 2 2 2 0 tLES Length Control Enable to Clock Setup Time 13 10 8 6 5 tLEH Length Control Enable to Clock Hold Time 2 2 2 2 0 tMS Mode Select Setup Time 13 10 8 6 5 tMH Mode Select Hold Time 2 2 2 2 0 tOUT Clock to Data Out 22 16 15 14 10 tOH Output Hold Time (Note 8) 44444 tENA Three-State Output Enable Delay (Note 11) 25 20 15 14 12 tDIS Three-State Output Disable Delay (Note 11) 25 24 15 14 12 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS *When CLKSEL is HIGH, assume CLK is inverted. FUNCTIONAL TIMING — CLKSEL LOW CLK* tCYC tPW tPW MODSEL tMH tDS tDH DI9-0 DO 9-0 OE tDIS tENA tOUT tOH tMS HIGH IMPEDANCE 123456789012345678901234 1 2345678901234567890123 4 123456789012345678901234 *DISCONTINUED SPEED GRADE

08/16/2000–LDS.9501-H Video Imaging Products 1234567890 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 SWITCHING CHARACTERISTICS C LOCK ENABLE TIMING — CLKSEL LOW CLK* tPW CLKEN tMHtES tES INTERNAL CLOCK LENGTH CONTROL TIMING — CLKSEL LOW CLK* tLEH LCEN tMHtLES LC 10-0 tLS tLH *When CLKSEL is HIGH, assume CLK is inverted. LF9501– 40* 31* 25 20 15 * Symbol Parameter Min Max Min Max Min Max Min Max Min Max tCYC Cycle Time 40 31 25 20 15 tPW Clock Pulse Width 15 12 10 8 6 tDS Data Input Setup Time 12 10 8 6 5 tDH Data Input Hold Time 2 2 2 2 0 tES Clock Enable to Clock Setup Time 12 10 8 6 5 tEH Clock Enable to Clock Hold Time 2 2 2 2 0 tLS Length Control Input Setup Time 13 10 8 6 5 tLH Length Control Input Hold Time 2 2 2 2 0 tLES Length Control Enable to Clock Setup Time 13 10 8 6 5 tLEH Length Control Enable to Clock Hold Time 2 2 2 2 0 tMS Mode Select Setup Time 13 10 8 6 5 tMH Mode Select Hold Time 2 2 2 2 0 tOUT Clock to Data Out 22 16 15 14 10 tOH Output Hold Time (Note 8) 44444 tENA Three-State Output Enable Delay (Note 11) 25 20 15 14 12 tDIS Three-State Output Disable Delay (Note 11) 25 24 15 14 12 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) 123456789012345678901234 1 2345678901234567890123 4 123456789012345678901234 *DISCONTINUED SPEED GRADE

6 08/16/2000–LDS.9501-H Video Imaging Products 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. In- put levels below ground or above V CC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing ev- ery cycle and no load, at a 25 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

08/16/2000–LDS.9501-H Video Imaging Products 44-pin

ORDERING INFORMATION

0°C to +70°C — COMMERCIAL SCREENING Speed 25 ns 20 ns Plastic J-Lead Chip Carrier (J1) LF9501JC25 LF9501JC20 44123456 43 42 41 40 2524 26 27 281918 20 21 22 23 Top View DO 0 DO 1 DO 2 DO 3 DO 4 VCC GND DO 5 DO 6 DO 7 DO 8 DI0 DI1 DI2 DI3 DI4 VCC GND DI DI6 DI7 DI8 DO 9 OE LC 0 LC 1 LC 10 LC 9 LC 8 LC 7 LC 6 DI9 NC LCEN CLKSEL NC NC CLKEN CLK LC LC 3 LC 4 LC 5 MODSEL –40°C to +85°C — COMMERCIAL SCREENING