LF3304

LF3304 LODEV | Alldatasheet

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08/16/2000–LDS.3304-F LF3304 Dual Line Buffer/FIFODEVICES INCORPORATED ❑❑❑❑❑ 100 MHz Data Rate for Video and other High-Speed Applications ❑❑❑❑❑ One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit ❑❑❑❑❑ Dual Modes: Line Buffer or FIFO ❑❑❑❑❑ User-Programmable FIFO Flags ❑❑❑❑❑ User-Resettable Read and Write Pointers ❑❑❑❑❑ Single 3.3 V Power Supply,

5 V Tolerant I/O

The LF3304 is a dual line buffer/ FIFO, designed to operate at HDTV rates. The LF3304 will operate in two distinct modes: Line Buffer and FIFO. In these modes the two memo- ries can operate independently or with common control. The LF3304 comprises t wo 12-bit 4K memories configurable in a variety of ways including: Two 12-bit 4K deep line buffers (independent lengths), Three 8-bit 4K deep line buffers VARIABLE LENGTH RAM ARRAY B 4K x 12-bit VARIABLE LENGTH RAM ARRAY A 4K x 12-bit AIN11-0 BIN11-0 AOUT 11-0 BOUT 11-0 OEB RAM ARRAY 2 CONTROL LENGTH 11-0 WENB RENB RRB RWB RAM ARRAY 1 CONTROL WENA RENA RRA RWA EFB PAFB FFB PAEB PAEA FFA EFA PAFA ADDRA LDB FLAG GENERATOR FLAG GENERATOR MASTER CONTROL MODE 1-0 WCLKA RCLKA WCLKB RCLKB LDA ADDRB OEA LF3304 BLOCK DIAGRAM (common lengths), One 12-bit 8K deep line buffer, or Two 12-bit 4K FIFOs (independent operation). In FIFO mode, independent Read and Write Resets give the designer control over the internal pointers providing flexibility not commonly found in ordinary FIFOs. The LF3304 operatates at a maximum data rate of 100 MHz and is available in a 100-lead PQFP package.

tied together) being driven LOW. data being input on the next clock cycle. data will appear on the outputs. register on the rising edge of xCLKA. register on the rising edge of xCLKB. TABLE 1. DEVICE CONFIGURATION

controlled by separate external clocks. controlled by separate external clocks. depending on ADDRA (see Table 2). depending on ADDRB (see Table 2). data being input on the next clock cycle. data will appear on the outputs. TABLE 2. LOADING PROGRAMMABLE FLAG REGISTERS

08/16/2000–LDS.3304-F LDB — RAM Array B Load When LDB is LOW, data on BIN11-0 is latched in the LF3304 on the rising edge of WCLKB. WENA — Write Enable A If WENA is LOW, data on AIN 11-0 is written to the device on the rising edge of WCLKA. When RAM Array A is full, WENA is ignored. RENA — Read Enable A If RENA is LOW, data from RAM Array A is read and presented on AOUT 11-0 after tD has elapsed from the rising edge of RCLKA if the output port is enabled. If RENA goes HIGH, the last value loaded in the RAM Array A output register will remain unchanged. When RAM Array A is empty, RENA is ignored. WENB — Write Enable B If WENB is LOW, data on BIN 11-0 is written to the device on the rising edgle of WCLKB. When RAM Array B is full, WENB is ignored. RENB — Read Enable B If RENB is LOW, data from RAM Array B is read and presented on BOUT 11-0 after tD has elapsed from the rising edge of RCLKB if the output port is enabled. If RENB goes HIGH, the last value loaded in the RAM Array B output register will remain unchanged. When RAM Array B is empty, RENB is ignored. RWA — Reset Write A The write address pointer is reset to the first physical location when RWA is set LOW. After power up, the LF3304 requires a Reset Write for initialization because the write address pointer is not defined at that time. RRA — Reset Read A The read address pointer is reset to the first physical location when RRA is set LOW. After power up, the LF3304 requires a Reset Read for initialization because the read address pointer is not defined at that time. RWB — Reset Write B See RWA Description. RRB — Reset Read B See RRA description. OEA — Output Enable A When OEA is LOW, AOUT 11-0 is enabled for output. When OEA is HIGH, AOUT 11-0 is placed in a high- impedence state. The flag outputs are not affected by OEA. OEB — Output Enable B When OEB is LOW, BOUT 11-0 is enabled for output. When OEB is HIGH, BOUT 11-0 is placed in a high- impedence state. The flag outputs are not affected by OEB. Outputs AOUT 11-0 — Data Output A AOUT11-0 is the 12-bit registered data output port. BOUT11-0 — Data Output B BOUT11-0 is the 12-bit registered data output port. FFA — Full Flag A FFA goes LOW when RAM Array A is full of data. When FFA is LOW, RAM Array A can not be written to. The Full Flag is synchronized to the rising edge of WCLKA. EFA — Empty Flag A EFA goes LOW when the read pointer is equal to the write pointer, indicating that RAM Array A is empty. When EFA is LOW, read operations can not be performed. The Empty Flag is synchro- nized to the rising edge of RCLKA. FFB — Full Flag B FFB goes LOW when RAM Array B is full of data. When FFB is LOW, RAM Array B can not be written to. The Full Flag is synchronized to the rising edge of WCLKB. EFB — Empty Flag B EFB goes LOW when the read pointer is equal to the write pointer, indicating that RAM Array B is empty. When EFB is LOW, read operations can not be performed. The Empty Flag is synchro- nized to the rising edge of RCLKB. PAFA — Programmable Almost-Full Flag A PAFA goes LOW when the write pointer is (Full – N) locations ahead of the read pointer. N is the value stored in the PAFA register and has no default value. PAFA is synchronized to the rising edge of WCLKA. PAEA — Programmable Almost-Empty Flag A PAEA goes HIGH when the write pointer is (N + 1) location ahead of the read pointer. N is the value stored in the PAEA register and has no default value. PAEA is synchronized to the rising edge of RCLKA. PAFB — Programmable Almost-Full Flag B PAFB goes LOW when the write pointer is (Full – N) locations ahead of the read pointer. N is the value stored in the PAFB register and has no default value. PAFB is synchronized to the rising edge of WCLKB. PAEB — Programmable Almost-Empty Flag B PAEB goes HIGH when the write pointer is (N + 1) location ahead of the read pointer. N is the value stored in the PAEB register and has no default value. PAEB is synchronized to the rising edge of RCLKB.

08/16/2000–LDS.3304-F FIFO MODE OPERATION Initialization Upon power-up, the LF3304 requires the initialization of the internal read and write address pointers. This initialization sequence can be done by either a Flag Enable Reset or a Flag Disable Reset. A Flag Enable Reset will force the FIFO to operate in a ‘Flag Enabled’ mode. In this mode, writing will be disabled when FFx is LOW and reading is disabled when EFx is LOW. Any ‘write beyond full’ event or ‘read beyond empty’ event will be disabled. Note: in an ‘empty’ state, the last data word read from the FIFO is held on the output bus until the next valid read cycle. A Flag Disable Reset will force the FIFO to operate in a ‘Flag Disabled’ mode. In this mode, the user is allowed to write over previously un- read data and read out previously read data. Consequently, any enabled write or read is valid thus allowing the write and read pointers to ‘wrap-around’. Note: due to the nature of this mode, the flag status should be disregarded. For example, as the 4096th data word is written into the FIFO, assuming that no preceding read cycles have occured, FFx will be driven LOW thus indicat- ing a ‘full’state. While the FIFO is still in this ‘full’ state, the next enabled write will access address 000H, thus writing over data that has not yet been read out. Flag Enable Reset A Flag Enable Reset resets the read and write pointers and enables the flags to control the reading and writing of data according to the Full Flag and Empty Flag conditions. A Flag Enable Reset occurs when the following conditions are met: 1. RWA/RWB must be LOW for at least one WCLKA/WCLKB cycle. 2. RRA/RRB must be LOW for at least one RCLKA/RCLKB cycle. 3. WENx and RENx must be HIGH during the above two conditions plus one addition write or read cycle (which ever is longer). The Flag Enable Reset condition can be disabled if one of the two Flag Disable Reset conditions are applied. Flag Disable Reset A Flag Disable Reset resets the read and write pointers and disables the flags from controlling the reading and writing of data. A Flag Disable Reset occurs when the following conditions are met: 1. RWA/RWB must be LOW for at least one WCLKA/WCLKB cycle while WENx is LOW. 2. RRA/RRB must be LOW for at least one RCLKA/RCLKB cycle while RENx is LOW. Configuration of Programmable Flags In order to load a FIFO A Program- mable Flag Register, a rising edge of WCLKA, while WENA is LOW, latches AIN11-0 into either the PAFA or PAEA Register - depending on the states of ADDRA and LDA (See Table 2). In order to load a FIFO B Program- mable Flag Register, a rising edge of WCLKB, while WENB is LOW, latches BIN11-0 into either the PAFB or PAEB Register - depending on the states of ADDRB and LDB (See Table 2). See the Figure labeled “Program- mable Flag Load Timing.”

08/16/2000–LDS.3304-F M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –4 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input High Voltage 2.0 5.5 V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 50 mA ICC2 VCC Current, Quiescent (Note 7) 2m A C IN Input Capacitance TA = 25°C, f = 1 MHz 10 pF C OUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 3.00 V ≤ VCC ≤ 3.60 V Active Operation, Military –55°C to +125°C 3.00 V ≤ VCC ≤ 3.60 V

08/16/2000–LDS.3304-F LF3304– 15 12 10 Symbol Parameter Min Max Min Max Min Max tCYC Cycle Time 15 12 10 tPWH Clock Pulse Width High 5 4 3 tPWL Clock Pulse Width Low 5 4 3 tDS Data Setup Time 6 5 4 tDH Data Hold Time 0 0 0 tWES Write Enable Setup Time 6 5 4 tWEH Write Enable Hold Time 0 0 0 tRES Read Enable Setup Time 6 5 4 tREH Read Enable Hold Time 0 0 0 tLDS Load Setup Time 6 5 4 tLDH Load Hold Time 0 0 0 tRS Read/Write Reset Setup Time 6 5 4 tRH Read/Write Reset Hold Time 0 0 0 tAC Access Time 8 7 6 tWFF Write Clock to Full Flag 8 7 6 tREF Read Clock to Empty Flag 8 7 6 tPAF Write Clock to Programmable Almost-Full Flag 8 7 6 tPAE Read Clock to Programmable Almost-Empty Flag 8 7 6 tOHZ Output Enable to Output in Low Impedance 8 7 6 tOLZ Output Enable to Output in High Impedance 8 7 6 tSKEW1 Skew Time Between Read and Write Clocks for EF and FF 6 5 4 tSKEW2 Skew Time Between Read and Write Clocks for PAEx and PAFx 6 5 4 SWITCHING CHARACTERISTICS C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

08/16/2000–LDS.3304-F tPWH tPWL tCYC tRES tREH RCLKA RENA RENB RCLKB tAC RRA = RRB = HIGH AOUT 11–0 BOUT 11–0 EF tREF tREF OEA = OEB = LOW WCLKA WCLKB tSKEW1 tPWH tPWL tCYC (n) (n+1) tDS tDH tWES tWEH WCLKA WENA WENB AIN11–0 BIN11–0 WCLKB RWA = RWB = HIGH FF (n+3) tWFF tWFF (n+2) RCLKA RCLKB tSKEW1 W RITE CYCLE TIMING R EAD CYCLE TIMING

08/16/2000–LDS.3304-F W RITE RESET TIMING (n–2) (n–1) (n) tRS tRH RCLKA RRA RRB AOUT 11–0 BOUT 11–0 RCLKB (n+1) RENA = RENB = LOW OEA = OEB = LOW tAC (n+2) (0) (0) (1) (n-1) (n) (n+1) tRS tRH WCLKA RWA RWB AIN11–0 BIN11–0 WCLKB WENA = WENB = LOW tDS tDH (0)(n+2) (1) R EAD RESET TIMING PROGRAMMABLE FLAG LOAD TIMING PAEx PAFxAIN11–0 BIN11–0 WCLKA WCLKB ADDRA ADDRB LDA LDB tDS tDH tLDS tLDH WENA WENB

08/16/2000–LDS.3304-F PROGRAMMABLE ALMOST FULL FLAG PROGRAMMABLE ALMOST EMPTY FLAG tPAE WCLKA PAEA PAEB WCLKB RCLKA RCLKB tSKEW2 tPAE tPAF WCLKA PAFA PAFB WCLKB RCLKA RCLKB tPAF tSKEW2 O UTPUT ENABLE AND DISABLE OEA OEB AOUT 11–0 BOUT 11–0 tOHZ tOLZ HIGH IMPEDANCE

08/16/2000–LDS.3304-F 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damaging substrate injection currents and accu- mulations of static charge. Neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot. Input levels below ground will be clamped begin- ning at –0.6 V. The device can withstand indefinite operation with inputs or out- puts in the range of –0.5 V to +5.5 V. Device operation will not be adversely affected, however, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with outputs changing every cycle and no load, at a 40 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. 9. AC specifications are tested with NCV F NOTES input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC noise to maintain re- quired DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a mini- mum or maximum value. Input require- ments are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst- case operation of any device always pro- vides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH, is set at

3.0 V for Z-to-0 and 0-to-Z tests, and

set at 0 V for Z-to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.0V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

08/16/2000–LDS.3304-F GND VCC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 GND VCC BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 GND VCC WENA RWA WCLKA RCLKA RRA RENA VCC GND MODE LDA ADDRA OEA VCC GND LENGTH LENGTH 4 FFA/LENGTH 3 EFA/LENGTH 2 PAFA/LENGTH 1 PAEA/LENGTH 0 VCC GND AOUT AOUT 1 AOUT 2 AOUT 3 AOUT 4 AOUT 5 AOUT 6 AOUT 7 AOUT 8 AOUT 9 AOUT 10 AOUT 11 VCC GND BOUT BOUT 1 BOUT 2 BOUT 3 BOUT 4 BOUT 5 BOUT 6 BOUT 7 BOUT 8 BOUT 9 BOUT 10 BOUT 11 VCC GND WENB RWB WCLKB RCLKB RRB RENB GND VCC MODE 1 LDB ADDRB OEB GND VCC LENGTH 11 LENGTH 10 LENGTH 9/FFB LENGTH 8/EFB LENGTH 7/PAFB LENGTH 6/PAEB Top View 100 Plastic Quad Flatpack (Q2) LF3304QC15 LF3304QC12 LF3304QC10

ORDERING INFORMATION

0°C to +70°C — COMMERCIAL SCREENING Speed 15 ns 12 ns 10 ns 100-pin