L9D340G64BG2

L9D340G64BG2 LODEV | Alldatasheet

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integrated module products LOGIC Devices Incorporated www.logicdevices.com 1 May 19, 2009 LDS-L9D340G6BG2-A

4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)

PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product DDR3 Integrated Module [iMOD]:

• Vcc=VccQ=1.5V ± 0.075V
• 1.5V center-terminated, push/pull I/O
• Package: 16mm x 22mm, 13 x 21 matrix w/ 271balls
• Matrix ball pitch: 1.00mm Space saving footprint Thermally enhanced, Impedance matched, integrated packaging Differential, bidirectional data strobe 8n-bit prefetch architecture 8 internal banks (per word, 4 words integrated in package) Nominal and dynamic on-die termina- tion (ODT) for data, strobe, and mask signals. CAS (READ) latency (CL): 6, 8, and CAS (WRITE) latency (CWL): 6, 7 and 8 Fixed burst length (BL) of 8 and burst chop (BC) of 4 Selectable BC4 or BL8 on-the- fly (OTF)

FEATURES

Operating Temperature Range (Case Temp=Tc)

• Industrial: -40 ˚C to 85˚C supporting SELF & AUTO REFRESH
• Extended: -40 ˚C to 105˚C; manual REFRESH only
• Mil-Temp: -55 ˚C to 125˚C; manual REFRESH only CORE clocking frequencies:
• Industrial: 667MHz, 533MHz and 400MHz
• Extended: 533MHz and 400MHz
• Mil-Temp: 400MHz Data Transfer Rates:
• Industrial: 1333, 1066 and 800 Mbps
• Extended: 1066 and 800 Mbps
• Mil-Temp: 800 Mbps Write leveling Multipurpose register Output Driver Calibration 40% space savings while provid- ing a surface mount friendly pitch (1.00mm) Reduced I/O routing (34%) 30% improvement in routings for your memory array Reduced trace lengths due to the highly integrated, impedance matched packaging Thermally enhanced packaging technology allow silicon integration without performance degradation due to power dissipation (heat) High TCE organic laminate inter- poser for improved glass stability over a wide operating temperature Suitability of use in High Reliability applications requiring Mil-temp, non- hermetic device operation Benefits *Note: This integrated product and/or its specifications are subject to change without notice. Latest document should be retrieved from LDI prior to your design consideration. ORDER NUMBER SPEED GRADE DEVICE GRADE PKG FOOTPRINT I/O PITCH PKG NO. 16mm x 22mm 271 DDR3-1333 DDR3-1066 DDR3-800 Industrial Extended Mil-Temp L9D340G64BG2I15 L9D340G64BG2E19 L9D340G64BG2M25 iMOD Part Information BG21.00mm

Area 352mm2 ~40% I/O 271 Balls/Loca/g415ons 30% Monolithic Solu/g415on IMOD Solu/g415on 4 x 139.5mm2 = 558mm2 PLUS 4 x 96 pins = 384 pins total S A V I N G S O P T I O N S 22.0 16.0 L9D34G64BG2M3 LOT CODE DATE CODE ASSM CODE 22.0 16.0 DDR3 9.0mm x 15.5mm 96 ball FBGA DDR3 9.0mm x 15.5mm 96 ball FBGA DDR3 9.0mm x 15.5mm 96 ball FBGA DDR3 9.0mm x 15.5mm 96 ball FBGA INDUSTRIAL EXTENDED MIL-TEMP DDR3-1333 DDR3-1066 DDR3-800 L9D340G64BG2I15 L9D340G64BG2E19 L9D340G64BG2M25 667/533/400 400 1333/1066/800 800 8-8-8/6-6-6 6-6-6 Device Grade CORE Freq. [MHz] Support Data Rate [Mbps] Support Target tRCD-tRP-CL Speed Grade Speed Mark Part Ordering Information tRCD [ns] tRP [ns] CL [ns] LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product INTEGRATED VS. MONOLITHIC SOLUTIONS - HIGHLIGHTS TABLE 1: KEY TIMING PARAMETERS

Sample Part Number: L9D340G64BG2M15 Total Density= 4.0Gb Speed Grade tCK = 2.50ns tCK = 1.875ns tCK = 1.5ns 40G L9D3 Temperature Industrial Temperature Extended Temperature Military Temperature I E M Note: Not all options can be combined. Please see our Part Catalog for available offerings.

64 BG2

Organization= 64M x 64 16 x 22mm PBGA Code Code LOGIC Devices Incorporated www.logicdevices.com 3 May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 1 - 1Gb DDR3 PART NUMBERS Configuration Refresh Count ROW Addressing Back Addressing Column Addressing [8 Meg x 8 banks x 16] x 4 8K (A[12:0]) 8 (BA[2:0]) 1K (A[9:0]) Parameter 64 Meg x 64 TABLE 2: ADDRESSING

MRS , MPR, write leveling Preharge Power- Down Writing Automatic Sequence Command Sequence Preharging READ READ READ READ AP READ AP READ AP PRE, PREA PRE, PREA PRE, PREA WRITE WRITE CKE L CKE L CKE L WRITE WRITE AP WRITE AP WRITE AP PDE PDE PDX PDX SRX SRE REF MRS AC T RESET ZQCL ZQCL/ZQCS Reading ACT = ACTIVATE PREA=PRECHARGE ALL SRX = Self refresh exit MPR = Multipurpose register READ = RD, RDS4, RDS8 WRITE = WR, WRS4, WRS8 MRS = Mode register set READ AP = RDAP, RDAPS4, RDAPS8 WRITE AP = WRAP, WRAPS4, WRAPS8 PDE = Power-down entry REF = REFRESH ZQCL = ZQ LONG CALIBRATION PDX = Power-down exit RESET = START RESET PROCEDURE ZQCS = ZQ SHORT CALIBRATION PRE = PRECHARGE SRE = Self refresh entry LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product STATE DIAGRAM FIGURE 2 - SIMPLIFIED STATE DIAGRAM

LOGIC Devices Incorporated www.logicdevices.com 5 May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product The DDR3 SDRAM uses double data rate architecture to achieve high speed operation. The double data rate (DDR) architecture is an 8n prefetch with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal memory core and eight corresponding n-bit-wide, one-half-clock-cycle data transfer at the I/O pin. The differential strobes (LDQSx, LDQSx\\, UDQSx, UDQSx\\) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The READ data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CKx, CKx\\). The crossing of CK going HIGH and CK\\ going LOW is referred to as the posi- tive edge of Clock (CK). Control, Command, and Address signals are reg- istered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is refer- enced on the first rising edge of DQS after the READ preamble. READ and WRITE accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTI- VATE command are used to select the bank and the starting column loca- tion for the burst access. DDR3 SDRAM devices use READ and WRITE BL8 and BC4. An AUTO PRECHARGE function may be enabled to provide a self-timed ROW PRE- CHARGE that is initiated at the end of the burst access. As with standard DDR SDRAM devices, the pipelined, multi-bank architec- ture of the DDR3 SDRAM allows for concurrent operation, thereby provid- ing high bandwidth by hiding ROW PRECHARGE and ACTIVATION time. A SELF REFRESH mode is provided for all temperature grade offerings along with AUTO SELF REFRESH for Industrial product, as well as, power- saving, POWER-DOWN mode. FUNCTIONAL DESCRIPTION INDUSTRIAL TEMPERATURE The industrial temperature (I) device requires the case temperature not exceed -40˚C or +85˚C. JEDEC specifications require the REFRESH rate to double when Tc exceeds +85 ˚C; this also requires use of the high- temperature SELF REFRESH option. Additionally, ODT resistance and the INPUT/OUTPUT impedance must be derated when the Tc is <0˚C or >+85˚C. EXTENDED TEMPERATURE The Extended temperature (E) device requires the case temperature not exceed -40˚C or +105˚C. JEDEC speci fications require the refresh rate to double when Tc exceeds +85 ˚C; this also requires use of the high- temperature SELF REFRESH option. Additionally, ODT resistance and the INPUT/OUTPUT impedance must be derated when the Tc is <0˚C or >85˚C. MILITARY, EXTREME OPERATING TEMPERATURE The Mil-Temp (M) device requires the case temperature not exceed -55˚C or +125˚C. JEDEC requires the REFRESH rate double when Tc exceeds +85˚C and LDI recommends an additional derating as speci fied in this document as to properly maintain the DRAM core cell charge at tempera- tures above Tc>105˚C.

RST\\ VSS VSSQ VCC VCCQ WE\\ CKE CAS\\ RAS\\ CS\\ A0-A12, BA0-1 A, BA CK0 CK0\\ LDQS0 LDQS0\\ UDQS0 UDQS0\\ LDM0 UDM0 DQ 0 DQ DQ 8 DQ 15 DQ 0 DQ DQ 8 DQ A, BA DQ 0 DQ 7 DQ 8 DQ DQ 16 DQ DQ 24 DQ A, BA DQ 0 DQ DQ 8 DQ DQ 32 DQ DQ 40 DQ A, BA DQ 0 DQ DQ 8 DQ DQ 48 DQ DQ 56 DQ CK1 CK1\\ LDQS1 LDQS1\\ UDQS1 UDQS1\\ LDM1 UDM1 CK2 CK2\\ LDQS2 LDQS2\\ UDQS2 UDQS2\\ LDM2 UDM2 CK3 CK3\\ LDQS3 LDQS3\\ UDQS3 UDQS3\\ LDM3 UDM3 CS\\ RAS\\ CAS\\ CKE WE\\ VCCQ VCC VSSQ VSS RESET\\ RST\\ VSS VSSQ VCC VCCQ WE\\ CKE CAS\\ RAS\\ CS\\ RST\\ VSS VSSQ VCC VCCQ WE\\ CKE CAS\\ RAS\\ CS\\ RST\\ VSS VSSQ VCC VCCQ WE\\ CKE CAS\\ RAS\\ CS\\ LOGIC Devices Incorporated www.logicdevices.com 6 May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 3 - FUNCTIONAL BLOCK DIAGRAM

VrefCARESET\\ RFU BA2 RFU LDM1 CK2 VssQ VssQ VssQ DQ2 DQ1 DQ4 DQ20 DQ30 DQ14 DQ9 DQ12 DQ62 DQ59 BA1 A3 A12 RFU BA0 A5 VssQ VssQ VssQ VssQ VccQ VccQ VccQ VccQ Vcc Vcc Vcc Vcc VccVcc Vcc Vcc Vcc Vcc Vcc VccVcc Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC VccQ VccQNC NC NC NC NC NC NC NC VssQ NC NC 123456789 1 0 1 1 1 2 1 3 A VssQ VccQ VccQ NC NC VssQ NC NC VccQ A B VssQ Vcc Vss B C VccQ NC NC NC NC C D D E DQ35 DQ51 E F DQ36 F G LDM3 LDM2 G H DQ38 DQ54 H J UDM3 DQ44 J K K L L M M N ZQ3 ZQ2 N P DQ13 DQ29 DQ8 P R LDQS0\\D Q 10 DQ26 DQ23 R T DQ0 DQ16 T 123456789 1 0 1 1 1 2 1 3 AddressUNPOPULATED Level REF NCV + (I/O Power) CNTRL GND (Core) Data IO VccQ Vcc VccQ NC NC NC VssQ NC VccQ VccQ VssQ VssQ VssQ Vss Vcc Vss U V W Y AA U V W Y AA VssQ Vss DQ52 Vcc Vss Vcc UDQS1\\ LDQS1\\ CK0 Vss NC A6 A10 A9 A0 A11 A2 A4 Vcc UDQS1 UDQS0 CK0\\ CK1\\ Vss Vcc VccQ Vcc LDQS1 DQ5 CK1 NC Vss VccQ Vcc DQ33 DQ49 DQ60 DQ41 NC NC DQ43 DQ57 DQ46 ZQ0 ZQ1 DQ15 DQ24 DQ31 UDQS0\\ NC NC NC NC NC NC NC NC NC NC NC NC NCNC NC NC NC NC NC NC NC NC NC NC NC NC Vss Vss Vss VssVss Vss Vss Vss Vcc Vcc Vcc Vcc Vcc Vcc VssQ VssQ DQ63 DQ55 DQ39 DQ50 DQ34 DQ53 DQ58 DQ56 DQ47 DQ42 DQ40 DQ61 DQ45 DQ48 DQ32 DQ25 DQ28 DQ22 DQ6 DQ27 DQ11 DQ17 DQ19 DQ3 DQ7 DQ21 DQ18 DQ37 VssQ CK3 CK3\\ CK2\\ LDQS2 LDQS3 LDQS2\\ UDQS2\\ UDQS 2 UDQS3 UDM0 ODT LDQS0 RAS\\ CAS\\ CS\\ CKE WE\\ UDM2 LDQS3\\ UDQS3\\ UDM1 LDM0 GND (I/O) V + (Core Power) Rev.A, 9/08, 271BGA-1.00MM PITCH - X64, SCB LOGIC Devices Incorporated www.logicdevices.com 7 May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 4 - SDRAM - DDR3 PINOUT TOP VIEW BALL /SIGNAL LOCATION (PBGA)

LOGIC Devices Incorporated www.logicdevices.com 8 May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION Ball Assignments Symbol Type Description L3, L10, M3, K9, M4, M10, K3, M11, M5, K5, K4, L4, K10 M9, L11, F6 K11, G7, F7 U2, U3, V4, V3, E12, E11, D10, D11 R11, P8, R12, N12, G3, H6, G2, U10 A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 /AP, A11, A12 /BC BA0, BA1, BA2 RFU CKX, CKX\\ CKE CS\\ LDMx, UDMx RAS\\ CAS\\ WE\\ Input Input Input Input Input Input Input Input Input Input Address Inputs: Provide the ROW address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READY/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW), bank selected by BA[2:0] or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VrefCA. A12/BC#: when enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop, LOW = BC4 burst chop). Bank Address Inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRE- CHARGE command is being applied. BA[2:0] define which mode register (MR 0, MR1, MRE, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VrefCA. Future Address: A13, A14, A15 Clock: CKx and CKx\\ are differential clock inputs, one differential pair per WORD, four WORDs contained in the L9D3xxG64 product. All control and address input signals are sampled on the crossing of the positive edge of CKx and the negative edge of CKx\\. Output data strobes (UDQSx/ UDQSx\\ and LDQSx/LDQSx\\) is referenced to the crossing of CKx and CKx\\. Clock Enable: CKE enables and disables internal circuitry and clocks on the SDRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CKx, CKx\\, CKE, RESET#, and ODT) are disabled during SELF REFRESH. CKE is referenced to VrefCA. Chip Select: CS\\ enables (registered LOW) and disables the command decoder. All commands are masked when CS\\ is registered HIGH. CS\\ provides for external rank selection on systems with multiple ranks. CS\\ is considered part of the command code. CS\\ is referenced to VrefCA. Input Data Mask: LDMx is the Lower-byte of a WORD, UDMx is the Upperbyte of a WORD, the L9D3xxG64 contains four WORDS. The data mask input, masks WRITE data. Lower byte data masked when LDMx is sampled HIGH, upper byte data masked when UDMx is sampled HIGH. The UDMx and LDMx pins are structured as inputs only, the pins electrical loading is designed to match that of the DQ and LDQSx\\, UDQSx and UDQSx\\ pins. ROW Address Strobe/Select: Defines the command being entered along CAS\\, WE\\, and CS\\. This input pin is referenced to VrefCA. COLUMN Address Strobe/Select: Defines the command being entered along with RAS\\, WE\\, and CS\\. This input pin is referenced to VrefCA. WRITE Enable Input: Defines the command being entered along with CAS\\, RAS\\,, and CS\\. This input pin is referenced to VrefCA.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol Type Description T5, R3, T4, R2, F9, G11, F10, G12 N4, N6, N3, N2, J10, J8, J11, J12 T2, T10, V5, U12, T11, U4, P12, T6 P4, N10, R4, R9, N11, P2, N9, N5 T3, R10, U6, U11, T12, U5, P11, R6 P5, P9, R5, R8, P10, P3, N8, P6 F12, F4, D9, E2, F3, E10, H2, F8 H10, J4, G10, G5, J3, H12, J5, J9 ODT RESET\\ LDQSx, LDQSx\\ UDQSx, UDQSx\\ DQ 0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 DQ16, DQ17, DQ18, DQ19, DQ20, DQ21, DQ22, DQ23 DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30, DQ31 DQ32, DQ33, DQ34, DQ35, DQ36, DQ37, DQ38, DQ39 DQ40, DQ41, DQ42, DQ43, DQ44, DQ45, DQ46, DQ47 Input Input Input Input I/O I/O I/O I/O I/O I/O On-Die Termination: ODT enables (when registered HIGH) and disables termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following signals: DQ[63:0], LDQXx\\, UDQSx\\, UDMx, and LDMx. The ODT input is ignored if disabled via the LOAD MODE register command. ODT is referenced to VrefCA. RESET: An input control pin, active LOW referenced to Vss. The RESET\\ input receiver is a CMOS input defined as a rail to rail signal with DC HIGH ≥ 0.8 x Vcc and DC LOW ≤ 0.2 x VccQ. RESET\\ assertion and de-assertion are asynchronous. Data Strobe, LOW Byte (per WORD): Output, edge-aligned with READ data. Input, center- aligned with WRITE data. Data Strobe, HIGH Byte (per WORD): Output, edge-aligned with READ data. Input, center- aligned with WRITE data. Data Input/Output: LOW Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ. Data Input/Output: HIGH Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ. Data Input/Output: LOW Byte, WORD 2. Pin referenced to VrefDQ. Data Input/Output: HIGH Byte, WORD 2. Pin referenced to VrefDQ. Data Input/Output: LOW Byte, WORD 3. Pin referenced to VrefDQ. Data Input/Output: HIGH Byte, WORD 3. Pin referenced to VrefDQ.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol Type Description F11, G4, E8, E3, F2, E9, H3, G8 H9, H5, G9, G6, H4, H11, J6, H8 B3, B5, B6, B8, B9, B11, C2, C12, J7, K2, K6, K8, K12, L5, L9, M2, M6, M8, M12, N7, W2, W12, Y3, Y5, Y6, Y8, Y9, Y11 A3, A4, A10, A11, C1, C13, D1, D13, K1, K13, M1, M13, V13, W1, W13, AA3, AA4, AA10, AA11 B4, B7, B10, C3, C11, D2, D12, H7, K7, L2, L6, L8, L12, M7, P7, V2, V12, W3, W11, Y2, Y4, Y7, Y10, Y12 A2, A7, A12, A13, B1, B13, L1, L13, Y1, Y13, AA1, AA2, AA7, AA12, AA13 C5, C6, D5, D6 A5, A6, A8, A9, C4, C7, C8, C9, C10, D3, D4, D7, D8, E1, E4, E5, E13, F1, F5, F13, G1, G13, H1, H13, J1, J13, N1, N13, P1, P13, R1, R13, T1, T7, T8, T9, T13, U1, U7, U8, U13, V8, V9, V10, V11, W4, W5, W7, W8, W9, W10, AA5, AA6, AA8, AA9 DQ48, DQ49, DQ50, DQ51, DQ52, DQ53, DQ54, DQ55 DQ56, DQ57, DQ58, DQ59, DQ60, DQ61, DQ62, DQ63 Vcc VccQ Vss VssQ VrefCA VrefDQ ZQx UNPOPULATED NC Supply Supply Supply Supply Supply Supply Supply Supply Ref. Data Input/Output: LOW Byte, HIGH WORD (WORD 4). Pin referenced to VrefDQ. Data Input/Output: HIGH Byte, HIGH WORD (WORD 4). Pin referenced to VrefDQ. Power Supply: 1.5V ± 0.075V Data I/O Supply: 1.5V ± 0.075V Ground Data I/O Ground: Isolated from Core for improved noise immunity Voltage Reference CORE: VrefCA must be maintained at all times Voltage Reference I/O: VrefDQ must be maintained at all times. External Reference for output drive calibration Unpopulated, un-plated matrix location(s) No Connect: These ball locations have no electrical connection internally. Locations other than those indicating an upgrade or alternative function should be left isolated (non-connected)

1.00 NOM

12.00 NOM

0.50 NOM

0.05 MAX

Note: All dimensions in mm 271 x Ø 0.60 NOM LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 5 - MECHANICAL DRAWING 15.95 16.15 21.95 22.15

1.75 MAX

20.00 NOM

PACKAGE OUTLINE DIMENSIONS LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product NOTES: 1. Vcc and VccQ must be within 300mV of each other at all times and VREF must not be greater than 0.6 x VccQ. When Vcc and VccQ are less than 500MV, VREF may be ≤300mV. 2. Max operating case temperature. Tc is measured in the center of the package. 3. Device Functionality is not guaranteed if the DRAM device exceeds the Maximum Tc during operation. NOTES: 2. DM input is grouped with I/O pins, reflecting the signal is grouped with DQ and therefore matched in loading. 3. CCCQS is for DQS vs. DQS\\ 4. CDIO = CIO (DQ) - 0.5 x (CIO [DQS] + CIO [DQS\\]) 5. Excludes CK, CK\\ 6. C DI_CNTL = CI(CNTL) - 0.5 x (CCK[CK] + CCK [CK\\]); CNTL = ODT, CS\\ and CKE 7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 x (CCK [CK] + CCK [CK\\]); CMD = RAS\\, CAS\\, and WE\\ ADDR = [n:0] Capacitance Parameter Symbol MIN MAX MIN MAX MIN MAX UNITS NOTES CK and CK\\ ∆C: CK to CK\\ Single-end I/O: DQ, DM Differential I/O: DQS, DQS\\ ∆C: DQS to DQS\\ ∆C: DQ to DQS ∆C: CNTL to CK ∆C: cmd_ADDR to CK Inputs (RAS\\, CAS\\, WE\\, CS\\, CKE, ADDR) TABLE 6: INPUT/OUTPUT CAPACITANCE CCK CDCK C10 C10 CCCQS CDI0 CDI_CNTL CDI_CMD_ADDR CI_Shared 3.1 1.5 1.5 -0.5 -0.5 -0.5 2.9 6.2 0.2 3.0 3.0 0.2 0.3 0.3 0.3 5.5 6.2 0.2 3.0 3.0 0.2 0.3 0.3 0.3 5.3 3.0 1.5 1.5 -0.5 -0.5 -0.5 2.9 6.1 0.2 2.5 2.5 0.2 0.3 0.3 0.3 5.1 pF pF pF pF pF pF pF pF pF DDR3-800 DDR3-1066 DDR3-1333 3.1 1.5 1.5 -0.5 -0.5 -0.5 2.9 Symbol Parameter MIN MAX UNITS NOTES Vcc VccQ VIN, VOUT TcIndustrial TcExtended TcMiltemp TSTG V V V 2,3 2,3 2,3 2,3 TABLE 5: ABSOLUTE MAXIMUM RATINGS 1.975 1.975 1.975 105 125 120 -0.4 -0.4 -0.4 -40 -55 -55 V cc Supply Voltage relative to Vss Vcc Supply Voltage relative to VssQ Voltage on any pin relative to Vss Operating Case Temperature Operating Case Temperature Operating Case Temperature Storage Temperature

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ICC Parameter 6-6-6 8-8-8 10-10-10 UNITS tCK (MIN) ICC CL ICC tRCD (MIN) ICC tRC (MIN) ICC tRAS (MIN) ICC tRP (MIN) ICC tFAW tRRD ICC tRFC TABLE 8: TIMING PARAMETERS FOR ICC MEASUREMENTS - CLOCK UNITS ns CK CK CK CK CK CK CK CK 1.5 1.875 DDR3-800 -25 DDR3-1066 -19 DDR3-1333 -15 x64 x64 64M x 16 (4X) 2.5

CK, CK\\ CKE Sub-Loop CS\\ RAS\\ CAS\\ WE\\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] 00110000000 10000000000 10000000000 11110000000 11110000000 00100000000 001100000F0 100000000F0 100000000F0 111100000F0 111100000F0 001000000F0 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 Repeat cycles nRC +1 through nRC +4 until 2 x RC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 PRE Repeat cycles 1 through 4 until nRAS - 1, truncate if needed Repeat cycles 1 through 4 until nRC - 1, truncate if needed Repeat cycles nRC +1 through nRC +4 until nRC - 1 + nRAS - 1, truncate if needed PRE ACT D D 4 x nRC 6 x nRC 8 x nRC 10 x nRC 12 x nRC 14 x nRC nRC + 3 nRC + 4 nRC + nRAS 2 x nRC nRAS nRC nRC + 1 nRC + 2 Cycle Number Command Data ACT D D Static HIGH Toggling LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 9: ICC0 MEASUREMENT LOOP

CK, CK\\ CKE Sub-Loop CS\\ RAS\\ CAS\\ WE\\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] 00110000000 10000000000 10000000000 11110000000 11110000000 01010000000 00100000000 001100000F0 100000000F0 100000000F0 111100000F0 111100000F0 010100000F0 001000000F0 Cycle Number Command Data ACT D D nR C D nR A S nR C n RC +1 nRC +2 n RC +3 n RC +4 n RC + nRCD n RC + nRAS 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC RD PRE ACT D D RD PRE Repeat sub-loop 0, use BA [2:0] = 1 00110011 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 Repeat cycles 1 through 4 until nRCD - 1, truncate if needed Repeat cycles 1 through 4 until nRAS - 1, truncate if needed Repeat cycles 1 through 4 until nRC - 1, truncate if needed Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed 00000000 Toggling Static HIGH Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 10: ICC1 MEASUREMENT LOOP

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 11: ICC MEASUREMENT CONDITIONS FOR POWER-DOWN CURRENTS Name Timing Pattern CKE External Clock tCK tRC tRAS tRCD tRRD tRC CL AL CS\\ Command Inputs ROW/COLUMN Addr Bank Address DM Data I/O Output Buffer DQ, DQS ODT Burst Length ACTIVE Bank(s) IDLE Bank(s) Special Notes n/a LOW Toggling tCK (MIN) I CC n\\a n\\a n\\a n\\a n\\a n\\a n\\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF None All n\\a n/a LOW Toggling tCK (MIN) I CC n\\a n\\a n\\a n\\a n\\a n\\a n\\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF None All n\\a n/a HIGH Toggling tCK (MIN) I CC n\\a n\\a n\\a n\\a n\\a n\\a n\\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF None All n\\a n/a LOW Toggling tCK (MIN) I CC n\\a n\\a n\\a n\\a n\\a n\\a n\\a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, OFF None All n\\a Icc2P0 Precharge Power- Down Current (Slow Exit) Icc2P1 Precharge Power- Down Current (Fast Exit) Icc2Q Precharge Quiet Standby Current Icc3P Active Power- Down Current

CK, CK\\ CKE Sub-Loop CS\\ RAS\\ CAS\\ WE\\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] 10000000000 10000000000 111100000F0 111100000F0 Cycle Number Command Data D 2D \\ 3D \\ Repeat sub-loop 0, use BA [2:0] = 7 4-7 8-11 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Static HIGH Toggling12-15 16-19 20-23 24-27 28-31 LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 12: ICC2N / ICC3N MEASUREMENT LOOP

CK, CK\\ CKE Sub-Loop CS\\ RAS\\ CAS\\ WE\\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] 10000000000 10000000000 111100000F0 111100000F0 Cycle Number Command Data Toggling Static HIGH 12-15 28-31 1D- 2D \\- D\\- 4-7 Repeat sub-loop 0, use BA [2:0] = 1; ODT = 0 8-11 Repeat sub-loop 0, use BA [2:0] = 2; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 3; ODT = 1 16-19 Repeat sub-loop 0, use BA [2:0] = 4; ODT = 0 20-23 Repeat sub-loop 0, use BA [2:0] = 5; ODT = 0 24-27 Repeat sub-loop 0, use BA [2:0] = 6; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 7; ODT = 1 LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 13: ICC2NT MEASUREMENT LOOP

CK, CK\\ CKE Sub-Loop CS\\ RAS\\ CAS\\ WE\\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] 01010000000 10000000000 11110000000 11110000000 010100000F0 100000000F0 111100000F0 111100000F0 Data Static HIGH Toggling 56-63 8-15 Cycle Number Command RD D RD - D 32-39 16-23 24-31 40-47 48-55 00000000 00110011 Repeat sub-loop 0, use BA [2:0] = 7 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 14: ICC4R MEASUREMENT LOOP

CK, CK\\ CKE Sub-Loop CS\\ RAS\\ CAS\\ WE\\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] 01001000000 10001000000 11111000000 11111000000 010010000F0 100010000F0 111110000F0 111110000F0 Data 1D- WR Toggling Sta/g415c HIGH 2D \\- 00000000 Cycle Number Command D\\- 4W R00110011 5D- D\\- 7D \\- 8-15 Repeat sub-loop 0, use BA [2:0] = 1 16-23 Repeat sub-loop 0, use BA [2:0] = 2 24-31 Repeat sub-loop 0, use BA [2:0] = 3 32-39 Repeat sub-loop 0, use BA [2:0] = 4 40-47 Repeat sub-loop 0, use BA [2:0] = 5 48-55 Repeat sub-loop 0, use BA [2:0] = 6 56-63 Repeat sub-loop 0, use BA [2:0] = 7 LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 15: ICC4W MEASUREMENT LOOP

CK, CK\\ CKE Sub-Loop CS\\ RAS\\ CAS\\ WE\\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] 9-12 13-16 Cycle Number Command Data 17-20 21-24 25-28 29-32 33-n RFC-1 Repeat sub-loop 1a, use BA [2:0] = 1 Repeat sub-loop 1a, use BA [2:0] = 2 1a2 5-8 Static HIGH Toggling REF D D Repeat sub-loop 1a, use BA [2:0] = 4 Repeat sub-loop 1a, use BA [2:0] = 5 Repeat sub-loop 1a, use BA [2:0] = 6 Repeat sub-loop 1a, use BA [2:0] = 3 Repeat sub-loop 1a, use BA [2:0] = 7 Repeat sub-loop 1a through 1h until n RFC - 1, truncate if needed LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 16: ICC5B MEASUREMENT LOOP

PACKAGE OUTLINE DIMENSIONS LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 17: ICC MEASUREMENT LOOP ICC Test Icc8: Reset Icc6E/M: Self Refresh Current Icc6: Self Refresh Current Extended or Mil Temperature Range, Tc = -40°C to 85°C or -55°C to 125°C Industrial Range Tc =-40°C to 85°C CKE External Clock tCK tRC tRAS tRCD tRRD tRC CL AL CS\\ Command Inputs ROW/COLMUN addresses BANK addresses Data I/O Output buffer DQ, DQS ODT Burst Length Active BANKS IDLE BANKS SRT ASR LOW Off, CK and CK\\ = LOW n\\a n\\a n\\a n\\a n\\a n\\a n\\a n\\a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, Mid-level n\\a n\\a n\\a Disabled (normal) Disabled LOW Off, CK and CK\\ = LOW n\\a n\\a n\\a n\\a n\\a n\\a n\\a n\\a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, Mid-level n\\a n\\a n\\a Enabled (extended) Disabled Mid-level Mid-level n\\a n\\a n\\a n\\a n\\a n\\a n\\a n\\a Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level n\\a None All n\\a n\\a

CK, CK\\ CKE Sub-Loop CS\\ RAS\\ CAS\\ WE\\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] A [2:0] 00110000000 01010001000 10000000000 001101000F0 010101010F0 100001000F0 100003000F0 100007000F0 001100000F0 010100010F0 100000000F0 00110100000 01010101000 10000100000 10000300000 10000700000 Cycle Number Command Data 00000000 nRRD nRRD + 1 nRRD + 2 nRRD + 3 2 x nRRD 3x nRRD 4 x nRRD 4 x nRRD + 1 nFAW nFAW + nRRD nFAW + 2xnRRD nFAW + 3xnRRD nFAW + 4xnRRD nFAW + 4xnRRD+1 2 x nFAW 2 x nFAW + 1 2 x nFAW + 2 3 x nFAW + nRRD 3 x nFAW + 2x nRRD 2 x nFAW + 3 2 x nFAW + nRRD 2 x nFAW + nRRD+1 2 x nFAW + nRRD+2 2 x nFAW + nRRD+3 2 x nFAW + 2x nRRD Static HIGH Toggling ACT RDA D ACT 3 x nFAW + 3x nRRD 3 x nFAW + 4x nRRD 3 x nFAW + 4x nRRD +1 D ACT RDA Repeat cycle 2 x nFAW + 2 until 2 x nFAW + nRRD - 1 2 x nFAW + 3x nRRD 2 x nFAW + 4x nRRD 2 x nFAW+4x nRRD+1 3 x nFAW Repeat sub-loop 11, use BA[2:0] = 3 Repeat sub-loop 1, use BA[2:0] = 5 Repeat sub-loop 0, use BA[2:0] = 6 Repeat sub-loop 1, use BA[2:0] = 7 Repeat cycle nFAW + 4 x nRRD until 2 x nFAW - 1, if needed RDA D Repeat cycle 2 until nRRD - 1 Repeat cycle nRRD + 2 until 2 x nRRD - 1 Repeat sub-loop 0, use BA[2:0] = 2 Repeat sub-loop 0, use BA[2:0] = 3 Repeat cycle 4 x nRRD until nFAW - 1, if needed 00110011 Repeat sub-loop 10, use BA[2:0] = 2 RDA D 00110011 Repeat sub-loop 0, use BA[2:0] = 4 D ACT D Repeat cycle 2 x nFAW + nRRD + 2 until 2 x nFAW + 2 x nRRD - 1 00000000 Repeat cycle 3 x nFAW + 4 x nRRD until 4 x nFAW - 1, if needed Repeat cycle 2 x nFAW + 4 x nRRD until 3 x nFAW - 1, if needed Repeat sub-loop 10, use BA[2:0] = 4 Repeat sub-loop 11, use BA[2:0] = 5 Repeat sub-loop 10, use BA[2:0] = 6 Repeat sub-loop 11, use BA[2:0] = 7 D LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 18: ICC7 MEASUREMENT LOOP

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product NOTES: Tc = 01. °C to ≤ 85 °C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. Tc = -402. °C to ≤ 105°C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. Tc = -553. °C to ≤ 125°C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. ICC DDR3-800 DDR3-1066 DDR3-1333 UNITS Notes Icc0 Icc1 Icc2P0 Icc2P1 Icc2Q Icc2N Icc2NT Icc3P Icc3N Icc4R Icc4W Icc5B Icc6 Icc7 Icc8 Speed Bin 350 365 380 435 463 482 176 118 153 176 184 239 275 195 253 290 314 405 465 118 123 130 196 200 215 902 920 940 941 960 980 784 800 816 1372 1475 1590 I CC2P + 2mA ICC2P + 2.1mA ICC2P + 2.4mA 390 406 510 530 137 178 212 275 215 279 372 484 138 145 215 219 1020 1041 1137 1160 862 880 1489 1600 ICC2P + 2mA ICC2P + 2.1mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP TABLE 19: ICC MAXIMUM LIMITS 435 585 157 240 255 412 157 235 1137 1392 941 1646 I CC2P + 2mA

PACKAGE OUTLINE DIMENSIONS PACKAGE OUTLINE DIMENSIONS LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product NOTES: Vcc and VccQ must track one another, VccQ must be less than or equal 1. to Vcc, Vss = VssQ. Vcc and VccQ may include AC noise of ± 50mV (250 kHz to 20MHz) in 2. addition to the DC (0Hz to 250kHz) speci fications, Vcc and VccQ must be at the same level for valid AC timing parameters. V3. REF (see Table 22). The minimum limit requirement is for testing purposes. The leakage 4. current on the VREF pin should be minimal. NOTES: V1. REFCA(DC) is expected to be approximately 0.5 x Vcc and to track vari- ations in the DC level. Externally generated peak noise (noncommon mode) on V REFCA may not exceed ± 1% x Vcc around the VREFCA(DC) value. Peak-to-peak AC noise on V REFCA should not exceed ± 2% of VREFCA(DC). DC values are determined to be less than 20MHz in frequency. DRAM 2. must meet speci fications if the DRAM induces additional AC noise greater than 20MHz in frequency. V3. REFDQ(DC) is expected to be approximately 0.5 x Vcc and to track variations in the DC level. Externally generated peak noise (noncom- mon mode) on VREFDQ may not exceed ± 1% x Vcc around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ± 2% of VREFDQ(DC). V4. REFDQ(DC) may transition to V REFDQ(SR) and back to V REFDQ(DC) when in SELF zREFRESH, within restrictions outlined in the SELF REFRESH section. V5. TT is not applied directly to the device. V TT is a system supply for signal termination resistors. MIN and MAX values are system-depen- dent. Parameter/Condition Symbol MIN TYP MAX UNITS NOTES Supply Voltage I/O Supply Voltage Input Leakage Current: Any input 0V≤V IN≤Vcc, VREF pin 0V≤VIN≤1.1V All other pins not under test = 0V VREF Supply Leakage Current: V REFDQ = Vcc/2 or VREFCA = Vcc/2 All other pins not under test = 0V V V μA μA 1,2 1,2 3,4 TABLE 20: DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS 1.575 1.575 1.5 1.5 1.425 1.425 All Voltages are referenced to Vss Vcc VccQ II IVREF Parameter/Condition Symbol MIN TYP MAX UNITS NOTES VIN low; DC/commands/address busses VIN high; DC/commands/address busses Input reference voltage command/address bus I/O reference voltage DQ bus I/O reference voltage DQ bus in SELF REFRESH Command/address termination voltage (system level, not direct DRAM input) V V V V V V 1,2 2,3 TABLE 21: DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS See Table 20 Vcc 0.51 x Vcc 0.51 x Vcc Vcc n/a n/a 0.5 x Vcc 0.5 x Vcc 0.5 x Vcc 0.5 x VccQ Vss See Table 20 0.49 x Vcc 0.49 x Vcc Vss All Voltages are referenced to Vss VIL VIH VREFCA(DC) VREFDQ(DC) VREFDQ(SR) VTT

PACKAGE OUTLINE DIMENSIONS LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input high DC voltage: Logic 0 Input high AC voltage: Logic 0 Input high AC voltage: Logic 0 Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input high DC voltage: Logic 0 Input high AC voltage: Logic 0 Input high AC voltage: Logic 0 +175 +150 +100 -100 -150 -175 +150 +100 -100 -150 +175 +150 +100 -100 -150 -175 +175 +150 +100 -100 -150 -175 V IH (AC175) MIN VIH (AC150) MIN VIH (DC100) MIN VIL (DC100) MAX VIL (AC150) MAX VIL (AC175) MAX VIH (AC175) MIN VIH (AC150) MIN VIH (DC100) MIN VIL (DC100) MAX VIL (AC150) MAX VIL (AC175) MAX NOTES: All voltages are referenced to V1. REF, VREF is V REFCA for control, com- mand, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. Input setup timing parameters (2. tIS and tDS) are referenced at VIL(AC)/ VIH(AC), not VREF(DC). Input hold timing parameters (3. tIH and tDH) are referenced at V IL(DC)/ VIH(DC), not VREF(AC). Single-ended input slew rate = 1V/ns; maximum input voltage swing 4. under test is 900mV (peak-to-peak). Parameter/Condition Symbol DDR3-900 DDR1333 UNITS Command and Address TABLE 22: INPUT SWITCHING CONDITIONS DQ and DM DDR3-1066 mV mV mV mV mV mV mV mV mV mV mV mV

Notes: 1. Numbers in diagrams reflect nominal values. Minimum VIL and VIH levels 0.925V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V V IH (AC) VIH (DC) VIL (DC) VIL (AC) VIL and VIH levels with ringback 1.90V 1.50V 0.925V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V 0.0V -0.40V V DDQ + 0.4V narrow pulse width VDDQ VIH (AC) VIH (DC) VREF + AC noise VREF + DC error VREF + DC error VREF + AC noise VIL (DQ) VIL (AC) VSS VSS 0.4V narrow pulse width LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product OPERATING CONDITIONS FIGURE 6 - INPUT SIGNAL

FIGURE 7 & 8: OVERSHOOT/UNDERSHOOT SPECIFICATIONS Maximum amplitude Overshoot area VCC/VCCQ Time (ns) Volts (V) Maximum amplitude Undershoot area Time (ns) VSS/VSSQ Volts (V) Figure 7: Overshoot Figure 8: Undershoot AC OVERSHOOT/UNDERSHOOT SPECIFICATION LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product PACKAGE OUTLINE DIMENSIONS PACKAGE OUTLINE DIMENSIONS Parameter DDR3-800 DDR3-1066 DD R3-1333 Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 38) Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 39) Maximum overshoot area above V cc (see Figure 16 on page 38) Maximum undershoot area below Vss (see Figure 17 on page 39) TABLE 23: CONTROL AND ADDRESS PINS 0.4V 0.4V 0.4Vns 0.4Vns 0.4V 0.4V 0.67Vns 0.67Vns 0.4V 0.4V 0.5Vns 0.5Vns Parameter DDR3-800 DDR3-1066 DD R3-1333 Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 38) Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 39) Maximum overshoot area above V cc/ VccQ (see Figure 16 on page 38) Maximum undershoot area below V ss/ VssQ (see Figure 17 on page 39) TABLE 24: CLOCK, DATA, STROBE, AND MASK PINS 0.4V 0.4V 0.15Vns 0.15Vns 0.4V 0.4V 0.25Vns 0.25Vns 0.4V 0.4V 0.19Vns 0.19Vns

PACKAGE OUTLINE DIMENSIONS LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Parameter/Condition Symbol MIN MAX UNITS NOTES Differential input voltage, logic high - slew Differential input voltage, logic low - slew Differential input voltage, logic high Differential input voltage, logic low Differential input crossing voltage relative to Vcc/2 for DQS, DQS\\, CK, CK\\ Differential input crossing voltage relative to Vcc/2 for CK, CK\\ Single-ended high level for strobes Single-ended high level for CK, CK\\ Single-ended low level for strobes Single-ended low level for CK, CK\\ mV mV mV mV mV mV mV mV 7,8 TABLE 25: DIFFERENTIAL INPUT OPERATING CONDITIONS (CKX, CKX\\, DQSX, AND DQSX\\) n/a -200 Vcc/VccQ 2x(VREF-VIL(AC)) VREF(DC) + 150 VREF(DC) + 175 VccQ Vcc VccQ/2-VIL(AC) Vcc/2-VIL(AC) +200 n/a 2x(VIH(AC)-VREF) Vss/VssQ VREF(DC) - 150 VREF(DC) - 175 VccQ/2 + VIH(AC) Vcc/2 + VIH(AC VssQ Vss VIH DIFF(AC)slew VIL DIFF(AC)slew VIH DIFF(AC) VIL DIFF(AC) VIX VIX(175) VSHE VSEL NOTES: Clock is referenced to VccD and Vss. Data strobe is referenced to 1. VccQ and VssQ. Reference is V2. REFCA(DC) for clock and for VREFDQ(DC) for strobe. Differential input slew rate = 2V/ms.3. Defines slew rate reference points relative to input crossing voltages.4. MAX limit is relative to single-ended signals, the overshoot speci fica-5. tions are applicable. MIN limit is relative to single-ended signals, the undershoot speci fica-6. tions are applicable. The typical value of V7. IX(AC) is expected to be about 0.5 x Vcc of the transmitting device and VIX(AC) is expected to track variations in Vcc. VIX(AC) indicates the voltage at which differential input signals must cross. The V8. IX extended range (±175mV) is allowed only for the clock and this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single- ended swing V SEL, VSEH of at least Vcc/2 ±250mV, and the differential slew rate of CK, CK\\ is greater than 3V/ns.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 9 - VIX FOR DIFFERENTIAL SIGNALS VIX X X X X VCC, VCCQ VCC, VCCQ CK#, DQS# CK#, DQS# VIX VIX VIX CK, DQS CK, DQS VSS, VSSQ VSS, VSSQ VCC/2, VCCQ/2 VCC/2, VCCQ/2 FIGURE 10 - SINGLE-ENDED REQUIREMENTS FOR DIFFERENTIAL SIGNALS VSS or VSS Q VCC or VCC Q VSEL (MAX) VSEH (MIN) VSEH VSEL VCC /2 or VCC Q/2 CK or DQS

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 11 - DEFINITION OF DIFFERENTIAL AC-SWING AND tDVAC V IHDIFF (AC ) MIN V IHDIFF (DC) MIN 0.0 V ILDIFF (DC) MAX V ILDIFF (MAX) tDVAC V IHDIFF (MIN) V ILDIFF (AC ) MAX half cycle tDVAC CK - CK# DQ S - DQS # PACKAGE OUTLINE DIMENSIONS Slew Rate (V/ns) 350mV 300mV -4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0 <1.0 TABLE 26: DIFFERENTIAL INPUT OPERATING CONDITIONS (tDVAC) FOR CKX, CKX\\, DQSX, AND DQSX\\ 175 170 167 163 162 161 159 155 150 150 Below VIL (AC) tDVAC (ps) at [VIHDIFF(AC) to VILDiff(AC)]

PACKAGE OUTLINE DIMENSIONS Input Edge From To Calculation Setup Hold TABLE 27: SINGLE-ENDED INPUT SLEW RATE Input Slew Rate (Linear Signals) Rising Falling Rising Falling Measured VREF VREF VIL(DC)Max VIH(DC)MIN VIH(AC)MIN VIL(AC)MAX VREF VREF VIH(AC) MIN - VREF VREF - VIL(AC) MAX ∆TFS VREF - VIL(DC) MAX ∆TFH VIH(DC) MIN - VREF ∆TRSH LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS Setup (tIS and tDS) nominal slew rate for a rising signal is de fined as the slew-rate between the last crossing of V REF and the first crossing V IH(AC) MIN. Setup ( tIS and tDS) nominal slew rate for a falling signal is de fined as the slew rate between the last crossing of V REF an the first crossing of VIL(AC) MAX. Hold ( tIH and tDH) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF. Hold (tIH and tDH) nominal slew rate for a falling signal is de fined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS FIGURE 12 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED INPUT SIGNALS ! " ! "

PACKAGE OUTLINE DIMENSIONS Input Edge From To Calculation CK and DQS Reference TABLE 28: DIFFERENTIAL INPUT SLEW RATE DEFINITION Input Slew Rate (Linear Signals) Rising Falling Measured VREF VREF VIH(AC)MIN VIL(AC)MAX VIH(DIFF) MIN - VIL(DIFF) MAX ∆TR(DIFF) VIH(DIFF) MIN - VIL(DIFF) MAX ∆TF(DIFF) LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product SLEW RATE DEFINITIONS FOR DIFFERENTIAL INPUT SIGNALS Input slew rate for differential signals (CKx, CKx\\, UDQSx , UDQSx\\, LDQSx and LDQSx\\) are defined and measured as shown in Table 28. The nominal slew rate for a rising signal is defined as the slew rate between VIL(DIFF) MAX and VIH(DIFF) MIN. The nominal slew rate for a falling signal is defined as the slew rate between VIH(DIFF) MIN and VIL(DIFF) MAX. FIGURE 13 - NOMINAL DIFFERENTIAL INPUT SLEW RATE DEFINITION FOR DQS, DQS# AND CK, CK# #"$

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ODT CHARACTERISTICS RTTPU RTTPD ODT Chip in termination mode VCCQ DQ VSSQ IOUT = IPD - IPU IPU IPD IOUT VOUT To other circuitry such as RCV, . . . ODT’s effective resistance R TT is de fined by MR1[9,6 and 2]. ODT is applied to the DQx, UDMx, LDMx, UDQSx, UDQSx\\, LDQSx and LDQSx\\ balls. The ODT target values are listed in Table 29. Parameter/Condition Symbol MIN TYP MAX UNITS N O T E S RTT effective impedance Deviation of VM with respect to VccQ/2 % 1, 2, 4 1, 2, 3, 4 TABLE 29: ON-DIE TERMINATION DC ELECTRICAL CHARACTERISTICS RTT_EFF ∆VM -5 See Table 30 NOTES: Tolerance limits are applicable after a proper ZQ calibration has been 1. performed at a stable temperature and voltage (VccQ=Vcc, VssQ-Vss). Refer to “ODT Sensitivity” on page 37 if either the temperature or voltage changes after calibration. Measurement definition for R2. TT: Apply V IH(AC) to a pin under test and measure the current I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]: VIL(AC) - VIL(AC) I[VIH(AC))-I(VIL(AC))] Measure voltage (VM) at the tested pin with no load:3. For extended MIL-temp devices, the minimum values are derated by 4. 6% when the device is between -40°C and 0°C (Tc). RTT = 2 x VM VccQ ∆VM = -1 x 100 FIGURE 14 - ODT LEVELS AND I-V CHARACTERISTICS

PACKAGE OUTLINE DIMENSIONS LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product MR1 [ 9 , 6 , 2 ] 0, 1, 0 0, 0, 1 0, 1, 1 1, 0, 1 1, 0, 0 TABLE 30: RTT EFFECTIVE IMPEDANCES 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ V IL(AC) to VIH(AC) 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ V IL(AC) to VIH(AC) 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ V IL(AC) to VIH(AC) 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ V IL(AC) to VIH(AC) 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ 0.2 x VccQ 0.5 x VccQ 0.8 x VccQ V IL(AC) to VIH(AC) RTT Resistor VOUT MIN TYP MAX UNITS 120Ω 60Ω 40Ω 30Ω 20Ω 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12 RTT120PD240 RTT120PU240 RTT60PD120 RTT60PU240 RTT40PD80 RTT40PU80 RTT30PD60 RTT30PU60 RTT20PD40 RTT20PU40 120Ω 60Ω 40Ω 30Ω 20Ω

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ODT SENSITIVITY If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 29 can be expected to widen according to Tables 31 and 32. Symbol MIN MAX UNITS RTT RZQ/(2, 4, 6, 8, 12) TABLE 31: ODT SENSITIVITY DEFINITION 1.6 + dRTTdT x [DT] + dRTTdV x [DV]0.9 - dRTTdT x dRTTdV x [DV] TABLE 32 - ODT TEMPERATURE & VOLTAGE SENSITIVITY Change MIN MAX UNITS dRTTdT dRTTdV 1.5 0.15 ODT loading differs from that used in AC timing measurements. Two param- eters define when ODT turns on or off synchronously, two define when ODT turns on or off Asynchronously and, another de fines when ODT turns on or off dynamically. Table 33 outlines and provides definition and measurement reference settings for each parameter. ODT turn-on time begins when the output leaves HIGH-Z and ODT resis- tance begins to turn on. ODT turn-off time begins when the output leaves LOW-Z and ODT resistance begins to turn-off. ODT TIMING DEFINITIONS Timing reference point DQ, DM DQS , DQS# DUT VREF VTT = VSSQ VCCQ/2 ZQ RZQ = 240Ω VSSQ RTT = 25Ω CK, CK# FIGURE 15 - ODT TIMING REFERENCE LOAD

CK# tAON VSSQ DQ, DM DQS , DQS# Begin point: Rising edge of CK - CK# defined by the end point of ODTL on VSW1 End point: Extrapolated point at VSSQ TSW1 TSW2 CK CK# VCCQ/2 tAOF End point: Extrapolated point at VRTT_NOM VRTT_NOM VSSQ tAON tAOF VSW2 VSW2 VSW1 TSW1 TSW1 Begin point: Rising edge of CK - CK# defined by the end point of ODTL off LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product PACKAGE OUTLINE DIMENSIONS Symbol Begin Point Definition End Point Definition Figure tAON tAOF tAONPD tAOFPD tADC TABLE 33: ODT TIMING DEFINITIONS Figure 25 on page 60 Figure 25 on page 60 Figure 26 on page 61 Figure 26 on page 61 Figure 27 on page 62 Extrapolated point at VssQ Extrapolated point at VR TT_NORM Extrapolated point at VssQ Extrapolated point at VRTT_NOM Extrapolated points at VRTT_WR and VRTT_NOM Rising edge of CK-CK\\ defined by the end point of ODTL on Rising edge of CK-CK\\ defined by the end point of ODTL off Rising edge of CK-CK\\ with ODT first being registered HIGH Rising edge of CK-CK\\ with ODT first being registered LOW Rising edge of CK-CK\\ defined by the end point of ODTLCNW, ODTLCWN4, or ODTLCWN8 PACKAGE OUTLINE DIMENSIONS Parameter RTT_NORM Setting RTT_WR_Setting VSW1 VSW2 tAON tAOF tAONPD tAOFPD tADC TABLE 34: REFERENCE SETTINGS FOR ODT TIMING MEASUREMENTS 100mV 200mV 100mV 200mV 100mV 200mV 100mV 200mV 300mV 50mV 100mV 50mV 100mV 50mV 100mV 50mV 100mV 200mV n/a n/a n/a n/a n/a n/a n/a n/a RZQ/2 (120Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/12 (20Ω) Measured FIGURE 16 - tAON AND tAOF DEFINITIONS ODT TIMING DEFINITIONS

CK# tAONPD VSSQ DQ, DM DQS , DQS# Begin point: Rising edge of CK - CK# with ODT first registered HIGH VSW1 End point: Extrapolated point at VSSQ TSW2 CK CK# VCCQ/2 tAOFPD End point: Extrapolated point at VRTT_NOM VRTT_NOM VSSQ tAONPD tAOFPD TSW1 TSW2 TSW1 VSW2 VSW2 VSW1 Begin point: Rising edge of CK - CK# with ODT first registered LOW LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ODT CHARACTERISTICS FIGURE 17 - tAONPD AND tAOFPD DEFINITION FIGURE 18 - tADC DEFINITION CK CK# tADC DQ, DM DQS , DQS# End point: Extrapolated point at V RTT_NOM TSW21 tADC End point: Extrapolated point at VRTT_WR VCCQ/2 VSSQ VRTT_NOM VRTT_WR VRTT_NOM TSW11 VSW1 VSW2 TSW12 TSW22 Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW Begin point: Rising edge of CK - CK# defined by the end point of ODTL CNW4 or ODTLCNW8

RCV, . . . Chip in drive mode V CCQ VSSQ IPU IPD IOUT VOUT DQ LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product OUTPUT DRIVER IMPEDANCE FIGURE 19 - OUTPUT DRIVER 34 OHM OUTPUT DRIVER IMPEDANCE The 34Ω driver (MR1[5,1]=01) is the default driver. Unless otherwise stated, all timings and speci fications listed herein apply to the 34 Ω driver only. Its impedance RON is de fined by the value of the external reference resistor RZQ as follows: RON34=RZQ/7 (with nominal RZQ=240Ω±1%) and is actu- ally 34.3Ω±1%. The 34 Ω output driver impedance characteristics are listed in Table 35. PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR VOUT MIN TYP MAX UNITS NOTES 0, 1 TABLE 35: 34Ω DRIVER IMPEDANCE CHARACTERISTICS RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 1, 2 0.2/VccQ 0.5/VccQ 0.8/VccQ 0.2/VccQ 0.5/VccQ 0.8/VccQ 0.5/VccQ 34.3Ω R ON34PD RON34PU 0.6 0.9 0.9 0.9 0.9 0.6 -10 1.0 1.0 1.0 1.0 1.0 1.0 n/a 1.1 1.1 1.4 1.4 1.1 1.1 Pull-Up/Pull-Down mismatch (MMPUPD) NOTES: Tolerance limits assume RZQ of 240 Ω (±1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage 1. (VccQ = Vcc, VssQ = Vss). Refer to “34 Ohm drive sensitivity” if either the temperature or the voltage changes after calibration Measurement definition for mismatch between pull-up and pull-down (MM2. PUPD). Mearure both RONPU and RONPD at 0.5 x VccQ: MMPUD = RONNOM RONPU - RONPD

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product

34 OHM OUTPUT DRIVER IMPEDANCE

34 OHM DRIVER

The 34Ω driver’s current range has been calculated and summarized in Table 37 for Vcc=1.5V, Table 38 for Vcc=1.575V and Table 39 for Vcc=1.425V. The individual pull-up and pull-down resistors (RON34PD and RON34PU) are defined as follows with the Impedance Calculations listed in Table 36.

• RON34PD=(VOUT)/[IOUT]: RON34PU is turned off
• RON34PU=(VccQ-VOUT)/[IOUT]: RON34PD is turned off PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR VOUT MIN TYP MAX UNITS 0, 1 TABLE 36: 34Ω DRIVER PULL-UP AND PULL-DOWN IMPEDANCE CALCULATIONS Ω Ω Ω Ω Ω Ω 0.2/VccQ 0.5/VccQ 0.8/VccQ 0.2/VccQ 0.5/VccQ 0.8/VccQ 34.3Ω R ON34PD RON34PU 2.04 30.5 30.5 30.5 30.5 20.4 34.3 34.3 34.3 34.3 34.3 34.3 38.1 38.1 48.5 48.5 38.1 38.1 242.4 34.6 240 34.3 237.6 33.9 Ω Ω RON MIN TYP MAX UNITS RZQ = 240Ω±1% RZQ = (240Ω±1%)/7 PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR VOUT MIN TYP MAX UNITS 0, 1 mA mA mA mA mA mA I OL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ 34.3Ω RON34PD RON34PU 15.5 25.8 41.2 41.2 25.8 15.5 9.2 36.8 36.8 9.2 8.3 20.7 20.7 8.3 TABLE 38: 34Ω DRIVER IOH/IOL CHARACTERISTICS: VCC=VCCQ=1.575V PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR VOUT MIN TYP MAX UNITS 0, 1 mA mA mA mA mA mA I OL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ 34.3Ω RON34PD RON34PU 14.7 24.6 39.3 39.3 24.6 14.7 8.8 21.9 21.9 8.8 7.9 19.7 24.8 24.8 19.7 7.9 TABLE 37: 34Ω DRIVER IOH/IOL CHARACTERISTICS: VCC = VCCQ = 1.5V

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR VOUT MIN TYP MAX UNITS 0, 1 mA mA mA mA mA mA I OL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ IOL @ 0.2 x VccQ IOL @ 0.5 x VccQ IOL @ 0.8 x VccQ 34.3Ω RON34PD RON34PU 23.3 37.3 37.3 23.3 8.3 20.8 33.3 33.3 20.8 8.3 7.5 18.7 23.5 23.5 18.7 7.5 TABLE 39: 34Ω DRIVER IOH/IOL CHARACTERISTICS: VCC=VCCQ=1.425V 34Ω OUTPUT DRIVER SENSITIVITY If either the temperature or voltage changes after ZQ calibration, the tolerance limits listed in Table 35 can be expected to w iden according to Table 40 and 41. Symbol MIN MAX UNITS RON @ 0.8 x VccQ RON @ 0.5 x VccQ RON @ 0.2 x VccQ RZQ/7 RZQ/7 RZQ/7 TABLE 40: 34Ω OUTPUT DRIVER SENSITIVITY DEFINITION 1.1 - dRONdTH x [∆T] + dRONdVH x [∆V] 1.1 - dRONdTM x [∆T] + dRONdVM x [∆V] 1.1 - dRONdTL x [∆T] + dRONdVL x [∆V] 0.9 - dRONdTH x [∆T] + dRONdVH x [∆V] 0.9 - dRONdTM x [∆T] + dRONdVM x [∆V] 0.9 - dRONdTL x [∆T] + dRONdVL x [∆V] Change MIN MAX UNITS dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH %/°C %/mV %/°C %/mV %/°C %/mV TABLE 41: 34Ω OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY 1.5 0.13 1.5 0.13 1.5 0.13

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ALTERNATIVE 40 OHM DRIVER PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR VOUT MIN TYP MAX UNITS NOTES 0, 1 TABLE 42 - 40Ω DRIVER IMPEDANCE CHARACTERISTICS RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 1, 2 0.2/VccQ 0.5/VccQ 0.8/VccQ 0.2/VccQ 0.5/VccQ 0.8/VccQ 0.5/VccQ 40.0Ω R ON40PD RON40PU 0.6 0.9 0.9 0.9 0.9 0.6 -10 1.0 1.0 1.0 1.0 1.0 1.0 n/a 1.1 1.1 1.4 1.4 1.1 1.1 Pull-Up/Pull-Down mismatch (MMPUPD) NOTES: Tolerance limits assume RZQ of 240 Ω (±1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage 1. (VccQ = Vcc, VssQ = Vss). Refer to “40 Ohm drive sensitivity” if either the temperature or the voltage changes after calibration Measurement definition for mismatch between pull-up and pull-down (MM2. PUPD). Mearure both RONPU and RONPD at 0.5 x VccQ: MMPUPD = RONNOM RONPU - RONPD x 100 40Ω OUTPUT DRIVER SENSITIVITY If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 42 can be expected to widen according to Table 43 and 44. Symbol MIN MAX UNITS RON @ 0.8 x VccQ RON @ 0.5 x VccQ RON @ 0.2 x VccQ RZQ/6 RZQ/6 RZQ/6 TABLE 43: 40Ω OUTPUT DRIVER SENSITIVITY DEFINITION 1.1 - dRONdTH x [∆T] + dRONdVH x [∆V] 1.1 - dRONdTM x [∆T] + dRONdVM x [∆V] 1.1 - dRONdTL x [∆T] + dRONdVL x [∆V] 0.9 - dRONdTH x [∆T] + dRONdVH x [∆V] 0.9 - dRONdTM x [∆T] + dRONdVM x [∆V] 0.9 - dRONdTL x [∆T] + dRONdVL x [∆V]

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ALTERNATIVE 40 OHM DRIVER Change MIN MAX UNITS dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH %/°C %/mV %/°C %/mV %/°C %/mV TABLE 44: 40Ω OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY 1.5 0.15 1.5 0.15 1.5 0.15 OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS The SDRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 45 whi le the differential output driver is summarized in Table 46. PACKAGE OUTLINE DIMENSIONS Parameter/Condition Symbol MIN MAX UNITS NOTES Output leakage current: DQ are disabled; 0V ≤ VOUT≤ VccQ; ODT is disabled; ODT is HIGH Output slew rate: Single-ended; for rising and falling edges, measure between VOL(AC) = VREF - 0.1 x VccQ and VOH (AC) = VREF + 0.1 x VccQ Single-ended DC high-level output voltage Single-ended DC mid-point level output voltage Single-ended DC low-point level output voltage Single-ended DC high-point level output voltage Single-ended DC low-point level output voltage Delta R ON between pull-up and pull-down for DQ/DQS Test load for AC timing and output slew rates uA V/ns V V V V V 1, 2, 3, 4 1, 2, 5 1, 2, 5 1, 2, 5 1, 2, 3, 6 1, 2, 3, 6 1, 7 TABLE 45: SINGLE-ENDED OUTPUT DRIVER CHARACTERISTICS 2.5 -10 IOZ SRQSE VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) MMPUPD 0.8 x VccQ 0.5 x VccQ 0.2 x VccQ VTT + 0.1 x VccQ VTT - 0.1 x VccQ Output to VTT (VccQ/2) via 25Ω resistor See Table 35 on page 40 IV curve linearity. Do not use AC Test load.5. See Table 47 on page 47 for output slew rate.6. See Table 35 on page 40 for additional information.7. See Figure 29 on page 66 for an example of a single-ended output 8. signal. NOTES: RZQ of 240Ω (±1%) with RZQ/7 enabled (default 34Ω driver) and is appli-1. cable after proper ZQ calibration has been performed at a stable tem- perature and voltage (VccQ = Vcc, VssQ = Vss). V2. TT = VccQ/2 See Figure 31 on page 68 for the test load configuration.3. The 6V/ns maximum is applicable for a single DQ signal when it is switch-4. ing from either HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are combinations, the maximum limit of 6V/ ns maximum is reduced to 5V/ns.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product PACKAGE OUTLINE DIMENSIONS Parameter/Condition Symbol MIN MAX UNITS NOTES Output leakage current: DQ are disabled; 0V ≤ VOUT≤ VccQ; ODT is HIGH Output slew rate: Differential; for rising and falling edges, measure between VOLDIFF(AC) = - 0.2 x VccQ and VOH (AC) = + 0.2 x VccQ Output differential cross-point voltage Differential high-level output voltage Differential low-level output voltage Delta R ON between pull-up and pull-down for DQ/DQS Test load for AC timing and output slew rates uA V/ns mV V V 1, 2, 3 1, 4 1, 4 1, 5 TABLE 46: DIFFERENTIAL OUTPUT DRIVER CHARACTERISTICS VREF+150 VREF-150 -10 IOZ SRQDIFF VOX(AC) VOHDIFF(AC) VOLDIFF(AC) MMPUPD + 0.2 x VccQ - 0.2 x VccQ Output to VTT (VccQ/2) via 25Ω resistor See Table 48 on page 65 for the output slew rate.4. See Table 35 on page 58 for additional information.5. See Figure 30 on page 67 for an example of a differential output 6. signal. NOTES: RZQ of 240Ω (±1%) with RZQ/7 enabled (default 34Ω driver) and is appli-1. cable after proper ZQ calibration has been performed at a stable tem- perature and voltage (VccQ = Vcc, VssQ = Vss). V2. REF = VccQ/2 See Figure 31 on page 68 for the test load configuration.3. FIGURE 20 - DQ OUTPUT SIGNAL VOH(AC) MIN output MAX output VOL(AC)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 21 - DIFFERENTIAL OUTPUT SIGNAL VOH(DIFF) MIN output MAX output VOL(DIFF) VOX(AC) MAX VOX(AC) MINX X X X OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS REFERENCE OUTPUT LOAD Figure 22 represents the effective reference load of 25Ω used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate measurements. It is not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by any specific Industry test system/apparatus. System designers should use IBIS or other simulation tools to correlate the timing reference load presented or exhibited on the system or system environment. FIGURE 22 - REFERENCE OUTPUT LOAD FOR AC TIMING AND OUTPUT SLEW RATE Timing Reference Point DQ DQS DQS# DUT VREF VTT = VCCQ/2 VCCQ/2 ZQ RZQ = 240Ω VSS RTT = 25Ω

PACKAGE OUTLINE DIMENSIONS Output Edge From To Calculation DQ TABLE 47: SINGLE-ENDED OUTPUT SLEW RATE Output Slew Rate (Linear Signals) Rising Falling Measured VOL(AC) VOH(AC) VOH(AC) VOL(AC) VOH(AC) - VOL (AC) ∆TRSE VOH(AC) - VOL(AC) ∆TFSE LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product SLEW RATE DEFINITIONS FOR SINGLE-ENDED OUTPUT SIGNALS The single-ended output driver is summarized in Table 45. With the reference load for timing measurements, the output slew-rat e for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended signals as indicated in Table 47 and Figure 23. FIGURE 23 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED OUTPUT SIGNALS

PACKAGE OUTLINE DIMENSIONS Output Edge From To Calculation DQS, DQS\\ TABLE 48: DIFFERENTIAL OUTPUT SLEW RATE DEFINITION Output Slew Rate (Linear Signals) Rising Falling Measured VOLDIFF(AC) VOHDIFF(AC) VOHDIFF(AC) VOLDIFF(AC) VOHDIFF(AC) - VOL DIFF(AC) ∆TRDIFF VOHDIFF(AC) - VOLDIFF(AC) ∆TFDIFF LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product SLEW RATE DEFINITIONS FOR DIFFERENTIAL OUTPUT SIGNALS The differential output driver is summarized in Table 46. With the reference load for timing measurements, the output slew rat e for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for differential signals, as shown in Table 48 and Figure 33. FIGURE 24 - NOMINAL DIFFERENTIAL OUTPUT SLEW RATE DEFINITION FOR DQS, DQS#

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product PACKAGE OUTLINE DIMENSIONS Parameter Symbol MIN MAX MIN MAX MIN MAX UNITS NOTES ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CL=5 CL=6 CL=8 CL=10 Supported CL Settings Supported CWL Settings 2,3 2,3 TABLE 49: SPEED BINS tRCD tRP tRC tRAS tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) tCK (AVG) 52.5 37.5 2.5 60ms 3.3 3.3 52.5 37.5 2.5 1.875 60ms 3.3 3.3 <2.5 2.5 1.875 1.5 60ms 3.3 3.3 <1.875 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CK CK CWL=5 CWL=6 CWL=7 CWL=5 CWL=6 CWL=7 CWL=5 CWL=6 CWL=7 CWL=5 CWL=6 CWL=7 5 5, 6 5, 6, 7 Reserved (filled blocks) settings are not allowed.3. NOTES: t1. REFI depends on tOPER The CL and CWL setting result in 2. tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be ful- filled.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 50 (SHEET 1 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS MIN MAX MIN MAX MIN MAX 8 7800 8 7800 8 7800 9,42 8 3900 8 3900 8 3900 9,42 8 2900 8 2900 8 29009,42 ns 10,11 -100 100 -90 90 -80 80 ps 13 -90 90 -80 80 -70 70 ps 13 ps ps 16 ps 16 -147 147 -132 132 -118 118 ps 17 -175 175 -157 157 -140 140 ps 17 -194 194 -175 175 -155 155 ps 17 -209 209 -188 188 -168 168 ps 17 -222 222 -200 200 -177 177 ps 17 -232 232 -209 209 -186 186 ps 17 -241 241 -217 217 -193 193 ps 17 -249 249 -224 224 -200 200 ps 17 -257 257 -231 231 -205 205 ps 17 -263 263 -237 237 -210 210 ps 17 -269 269 -242 242 -215 215 ps 17 Units Notes Symbol Parameter -15 (DDR3-1333)

11 Cycles

12 Cycles

0.43 - 0.43 - tERRnPER MIN = (1+0.68ln[n]) x tJITPER MIN tERRnPER MAX = (1+0.68ln[n]) x tJITPER MAX 0.43 - 0.43 - tCK (AVG)15 ps 17 180 160 140 180 160 tERRnPER tJITCC tJITCC, LCK tERR6PERR tERR7PERR tERR8PERR n = 13, 14 … 49, 50 Cycles tERR2PERR tERR3PERR tERR4PERR tERR5PERR 200 tERR9PERR tERR10PERR tERR11PERR tERR12PERR Cumula/g415ve error across

2 Cycles

3 Cycles

4 Cycles

5 Cycles

6 Cycles

7 Cycles

8 Cycles

9 Cycles

10 Cycles

Clock absolute HIGH pusle width Clock absolute LOW pulse width tCLK (ABS) tCKDLL_DIS tCL (AVG) tCH (ABS) tCL (ABS) Clock period average: DLL enable mode HIGH pulse width average LOW pulse width average Clock period average: DLL disable modeTC = 85˚C to 105˚C 0.43 - tJITPER tJITPER, LCK tCK (AVG) ns - 0.43tCK (AVG) MIN=tCK (AVG) MIN+tJITPER MIN; MAX=tCK (AVG)MAX+tJITPER MAX TC = 0˚C to <85˚C TC = >105˚C to ≤125˚C tCH (AVG) See SPEED BIN TABLE (#49) for tCK range allowed

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 50 (SHEET 2 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS MIN MAX MIN MAX MIN MAX 75 - 25 - - - ps 18,19 250 - 200 - - - ps 19,20 125 - 75 - 30 - ps 18,19 275 - 250 - 180 - ps 19,20 150 - 100 - 65 - ps 18,19 250 - 200 - 165 - ps 19,20 600 - 490 - 400 - ps 41 - 200 - 150 - 125 ps -800 400 -600 300 -500 250 ps 22,23 - 400 - 300 - 250 ps 22,23 0 . 2-0 . 2-0 . 2- C K 2 5 -400 400 -300 300 -255 255 ps 23 0.38 - 0.38 - 0.4 - CK 21 0.38 - 0.38 - 0.4 - CK 21 -800 400 -600 300 -500 250 ps 22,23 - 400 - 300 - 250 ps 22,23 0.9 Note 24 0.9 Note 24 0.9 Note 24 CK 23,24 0.3 Note 27 0.3 Note 27 0.3 Note 27 CK 23,27 Data SETUP /g415me to DQS, DQS\\tDS AC150 DQ Input Timing Data HOLD /g415me from DQS, DQS\\VREF @ 1V/ns Data SETUP /g415me to DQS, DQS\\tDS AC175 Base (specifica/g415on) [CWL=1.875; 8-8-8] VREF @ 1V/ns Base (specifica/g415on) VREF @ 1V/ns Base (specifica/g415on) DQ HIGH-A /g415me from CK, CK\\ DQS, DQS\\ DIFFERENTIAL READ postambletRPST DQS, DQS\\ DIFFERENTIAL Output HIGH /g415me Units Notes DQ LOW-Z /g415me from CK, CK\\ DQ Strobe Input Timing DQS, DQS\\ DIFFERENTIAL WRITE postamble Parameter Symbol DQS, DQS\\ FALLING Setup to CK, CK\\ RISINGtDSS DQ Ouput Timing DQS, DQS\\ to DQ SKEW, per access DQ Output HOLD /g415me from DQS, DQS\\ tDQSS DQS, DQS\\ DIFFERENTIAL Input Low pulse width tWPST DQS,DQS\\ RISING to CK, CK\\ RISING tDQSL DQS, DQS\\ DIFFERENTIAL Input HIGH pulse widthtDQSH DQS, DQS\\ DIFFERENTIAL READ preambletRPRE DQS, DQS\\ FALLING Hold from CK, CK\\ RISINGtDSH DQS, DQS\\ DIFFERENTIAL WRITE preambletWPRE DQ Strobe Output Timing tQSH DQS, DQS\\ DIFFERENTIAL Output LOW /g415metQSL DQS, DQS\\ RISING to/from RISING CK, CK\\tDQSCK DQS, DQS\\ HIGH-Z /g415me (RL+BL/2)tHZ (DQS) DQS, DQS\\ LOW-Z /g415me (RL-1)tLZ (DQS) 10 1 10 ns DQS, DQS\\ RISING to/from RISING CK, CK\\ when DLL is disabled tDQSK DLL_DIS10 1 tDH AC100 Minimum Data Pulse WidthtDIPW tQH0.38 - tDQSQ - 0.38 - tCK (AVG) 21 tHZ (DQ) tLZ (DQ) 0.38

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 50 (SHEET 3 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS MIN MAX MIN MAX MIN MAX 512 - 512 - 512 - CK 28 200 - 125 - 65 - ps 29,30 375 - 300 - 240 - ps 20,30 350 - 275 - 190 - ps 29,30 500 - 425 - 340 - ps 20,30 275 - 200 - 140 - ps 29,30 375 - 300 - 240 - ps 20,30 900 - 780 - 620 - ps 41 ns 31 ns 31 ns 31,32 ns 31 40 - 37.5 - 30 - ns 31 50 - 50 - 45 - ns 31 CK CK CK CK MULTIPURPOSE REGISTER READ burst end to mode register set for mul/g415purpose register exit tMPRRMIN = 1CK; MAX = n/a CK MIN = 4CK; MAX = n/a MIN = greater of 12CK or 15ns; MAX = n/a MODE REGISTER SET command cycle /g415metMRD MIN = greater of 4CK or 7.5ns; MAX = n/a MIN = 4CK; MAX = n/a Auto precharge WRITE recovery + PRECHARGE /g415metDAL MIN = WR + tRP/tCK (AVG); MAX = n/aCK CAS\\-to-CAS\\ command delaytCCD MIN = 15ns; MAX = n/a Delay from start of internal WRITE transac/g415on to internal READ command tWTRMIN = greater of 4CK or 7.5ns; MAX = n/a CK 31,32,33 CK 31,34 WRITE recovery /g415metWR MODE REGISTER SET command update delaytMOD Four ACTIVATE windows for 2KB page size Four ACTIVATE windows for 1KB page sizetFAW READ-to-PRECHARE /g415metRTP Notes Symbol Parameter Units Command and Address Timing CTRL, CMD, ADDR setup to CK, CK\\ Base (specifica/g415on) VREF @ 1V/ns tIS AC175 CTRL, CMD, ADDR setup to CK, CK\\ Base (specifica/g415on)tIS AC150 VREF @ 1V/ns CTRL, CMD, ADDR hold to CK, CK\\ Base (specifica/g415on)tIH DC100 VREF @ 1V/ns DLL Locking /g415metDLLK See "Speed Bin Table (#49) for tRCD See "Speed Bin Table (#49) for tRP See "Speed Bin Table (#49) for tRAS Minimum CTRL, CMD, ADDR pulse widthtIPW ACTIVATE to Internal READ or WRITE delaytRCD PRECHARGE command periodtRP 1KB page sizeMIN=greater of 4CK or 10ns MIN=greater of 4CK or 7.5ns ACTIVATE-to-PRECHARGE command periodtRAS ACTIVATE-to-ACTIVATE command periodtRCDSee "Speed Bin Table (#49) for tRC CK 31 MIN=greater of 4CK or 6nsCK 31 ACTIVATE-to-ACTIVATE minimum command period2KB page size tRRD MIN=greater of 4CK or 10nsMIN=greater of 4CK or 6ns

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 50 (SHEET 4 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS MIN MAX MIN MAX MIN MAX 256 - 256 - 256 - CK 64 - 64 - 64 - CK CK ms ns 35 ms 36 ms 36 ms 36 μs 36 μs 36 μs 36 Valid clocks a/g332er SELF REFRESH entry or POWER-DOWN entry tCKSREMIN = greater of 5CK or 10ns; MAX = n/a CK Valid clocks before SELF REFRESH exit, POWER-DOWN exit, or RESET exit tCKSRXMIN = greater of 5CK or 10ns; MAX = n/a CK EXIT SELF REFRESH TO commands requiring a locked DLLtXSDLL MIN = tDLLK (MIN); MAX = n/aCK 28 MINIMUM CKE LOW pulse width for SELF REFRESH entry to SELF REFRESH exit /g415ming tCKESR MIN = tCKE (MIN) + CK; MAX = n/aCK SELF REFRESH Timing Exit SELF REFRESH TO commands not requiring a locked DLLtXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/aCK Maximum REFRESH period/interval TC ≤ 85˚C tREFI 7.8 TC >85˚C ≤ 105˚C 3.9 TC >105˚C ≤ 125˚C 2.9 TC ≤ 85˚C TC >105˚C ≤ 125˚C TC >85˚C ≤ 105˚C Maximum REFRESH period Begin power supply ramp to power supplies stable tVDDPRMIN = n/a; MAX = 200 ms REFRESH-to-ACTIVATE or REFRESH command periodtRFC MIN = 110; MAX = 9 x tREFIns REFRESH Timing RESET\\ LOW to power supplies stabletRPSMIN = 0; MAX = 200 RESET\\ LOW to I/O and RTT HIGH-ZtIOZMIN = n/a; MAX = 200 ZQCS command: Short Calibra/g415on TimetZQCS Exit RESET from CKE HIGH to a valid commandtXPRMIN = greater of 5CK or tRFC + 10ns; MAX = n/a Ini/g415aliza/g415on and RESET Timing - 512 - 512 - CK ZQCL command: Long Calibra/g415on /g415me POWER-UP and RESET opera/g415on Normal opera/g415on tZQINIT tZQOPER 512 Notes Symbol Calibra/g415on Timing Parameter Units

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 50 (SHEET 5 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS MIN MAX MIN MAX MIN MAX CK CK CK CK 37 CK CK CK CK MIN = Greater of 3CK or 7.5ns; MAX = n/aMIN = Greater of 3CK or 6ns; MAX = n/a CK 28 MIN = Greater of 10CK or 24ns; MAX = n/a BL8 (OTF, MRS) BC4OTFtWRAPDENMIN = WL + 4 + WR + 1 CK MIN = WL + 2 + WR + 1 BL8 (OTF, MRS) BC4OTFtWRPDEN tWRPDEN MIN = WL + 4 + tWR/tCK (AVG)CK tWRAPDEN BC4MRSMIN = WL + 2 + tWR/tCK (AVG) WRITE with AUTO PRECHARGE command to POWER-DOWN entryBC4MRS DLL on, any valid command, or DLL off to commands not requiring DLL locked tXP READ/READ with AUTO PRECHARGE commant to POWER-DOWN entrytRDPDENMIN = RL + 4 + 1 CK WRITE Command to POWER- DOWN entry REFRESH command to POWER-DOWN entrytREFPDENMIN = 1 MRS command to POWER-DOWN entrytMRSPDEN MIN = tMOD (MIN) tACTPDENMIN = 1 PRECHARGE/PRECHARGE ALL command to POWER-DOWN entrytPRPDENMIN = 1 CK Command pass disable delaytCPDEDMIN = 1; MAX = n/a POWER-DOWN entry to POWER-DOWN exit /g415mingtPDMIN = tCKE (MIN); MAX = 60ms POWER-DOWN entry period: ODT e/g415her synchronous or asynchronousPDE Greater of tANPD or tRFC - REFRESH command to CKE LOW /g415me CK CK POWER-DOWN exit period: ODT either synchronous or asynchronousPDXtANPD + tXPDLLCK Greater of 3CK or 7.5ns Greater of 3CK or 5.625ns Greater of 3CK or 5.625ns Begin POWER-DOWN period prior to CKE registered HIGHtANPDWL - 1CK POWER-DOWN Timing POWER-DOWN Entry MINIMUM Timing POWER-DOWN Exit Timing PRECHARGE POWER-DOWN with DLL off to command requiring DLL locked tXPDLL CKE MIN pulse widthtCKE (MIN) ACTIVATE command to POWER-DOWN entry CK Parameter Units Notes Symbol

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 50 (SHEET 6 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS MIN MAX MIN MAX MIN MAX CK 38 CK 40 -400 400 -300 300 -250 250 ps 23,38 CK CK CK 40 - 40 - 40 - CK 25 - 25 - 25 - CK 090909 n s 020202 n s WRITE Leveling output errortWLOE tWLS tWLH195 - ps WRITE Leveling output delaytWLO WRITE Leveling HOLD from rising DQS, DQS\\ crossing to rising CK, CK\\ crossing325 - 245 DQS; DQS\\ delaytWLDQSEN WRITE Leveling SETUP from rising CK, CK\\ crossing to rising DQS, DQS\\ crossing325 - 245 - 195 - 6CK + ODTL OFF RTT dynamic change skewtADC First DQS, DQS\\ RISING edgetWLMRD ps RTT_NOM-to=RTT_WR change skewODTLCNWWL - 2CK RTT_WR-to-RTT_NOM change skew - BC4ODTLCNW44CK + ODTL OFF RTT_WR-to-RTT_NOM change skew - BC8ODTLCNW8 ODT HIGH /g415me without WRITE command or with WRITE command and BC8ODTH8MIN = 6; MAX = n/a CK ODT HIGH /g415me without WRITE command or with WRITE command and BC4ODTH4MIN = 4; MAX = n/a CK ns 38 Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL OFF)tAOFPDMIN = 2; MAX = 8.5 ns 40 tAON RTT TURN-OFF from ODTL OFF referencetAOF Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL OFF)tAONPDMIN = 2; MAX = 8.5 ODT Timing Dynamic ODT Timing WRITE Leveling Timing RTT synchronous TURN-ON delayODTL on RTT synchronous TURN-OFF delayODTL off RTT TURN-ON from ODTL ON reference Parameter Units Notes Symbol

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product NOTES Parameters are applicable with 0˚C ≤ Tc ≤ +95˚C and Vcc/VccQ = + 1. 1.5V ± 0.075V. All voltages are referenced to Vss.2. Output timings are only valid for R3. ON34 output buffer selection. Unit 4. tCK (AVG) represents the actual tCK (AVG) of the input clock under operation. Unit CK represents one clock cycle of the input clock, counting the actual clock edges. AC timing and I5. CC tests may use a V IL-to-VIH swing of up to 900mV I the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK\\ and DQS, DQS\\ use their crossing points). The minimum slew rate for the input signals used to test the device is 1V/ns for single-ended inputs and 2V/ ns for differential inputs in the range between V IL (AC) and VIH (AC). All timings that use time-based values (ns, μs, ms) should use 6. tCK (AVG) to determine the correct number of clocks (Table 50 uses CK or CK (AVG) interchangeably). In the case of non-interger results, all minimum limits are to be rounded up to the nearest whole integer. The use of STROBE or DQSDIFF refers to the DQS and DQS\\ differen-7. tial crossing point when DQS is the rising edge. The use of CLOCK or CK refers to the CK and CK\\ differential crossing point when CK is the rising edge. This output load is used for all AC timing (except ODT reference timing) 8. and slew rates. The actual test load may be different. The output signal voltage reference point is VccQ/2 for single-ended signals and the crossing point for differential signals. When operating in DLL disable mode, LOGIC Devices, Inc. (LDI) does 9. not warrant compliance with normal mode timings or functionality. The clock’s 10. tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. Spread spectrum is not included in the jitter specification values. How-11. ever, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60kHz with and additional 1% of tCK (AVG) as a long-term jitter component; however, the spread-spectrum may not use a clock rate below tCK (AVG) MIN. The clock’s 12. tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of values speci fied and must of a random Gaussian distribution in nature. The period jitter (13. tJITPER) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. t14. CH (ABS) is the absolute instantaneous clock high pulse width as mea- sured from one rising edge to the following falling edge. t15. CL (ABS) is the absolute instantaneous clock low pulse width as mea- sured from one falling edge to the following rising edge. The cycle-to-cycle jitter (16. tJITCC) is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. The cumulative jitter error (17. tERRnPER), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accu- mulate consecutively away from the average clock over n number of clock cycles. t18. DS (base) and tDH (base) values are for a single-ended 1V/ns DQ slew rate and 2V/ns for differential DQS, DQS\\ slew rate. These parameters are measured from a data signal (DM, DQ0, DQ1 … 19. DQn and so forth) transition edge to its respective data strobe signal (DQS, DQS\\) crossing. The setup and hold times are listed converting the base speci fication 20. values (to which derating tables apply) to V REF when the slew rate is 1V/ns. These values, with a slew rate of 1V/ns are for reference only. When the device is operated with input clock jitter, this parameter 21. needs to be derated by the actual tJITPER (larger of tJITPER (MIN) or tJITPER (MAX) of the input clock (output deratings are relative to the SDRAM input clock). Single-ended signal parameter.22. The SDRAM output timing is aligned to the nominal or average clock. 23. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX); tDQSCK (MIN), tLZ (DQS) MAX, tLZ (DQ) MAX, and tAON (MAX). The parame- ter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX) is derated by tJITPER (MIN). The maximum preamble is bound by 24. tLZDQS (MAX). These parameters are measured from a data strobe signal (DQS, DQS\\) 25. crossing to its respective clock signal (CK, CK\\) crossing. The speci- fication values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present or not. The 26. tDQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command. The maximum postamble is bound by 27. tHZDQS (MAX). Commands requiring a locked DLL are: READ (and RDAP) and syn-28. chronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met. t29. IS (base) and tIH (base) values are for a single-ended 1 V/ns con- trol/command/ address slew rate and 2 V/ns CK, CK# differential slew rate. These parameters are measured from a command/address signal tran-30. sition edge to its respective clock (CK, CK\\) signal crossing. The speci- fication values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present or not. For these parameters, the DDR3 SDRAM device supports tnPARAM 31. (nCK) = RU ( tPARAM [ns]/ tCK[AVG][ns]), assuming all input clock

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product NOTES CONTINUED jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU ( tRP)/tCK[AVG]) if all input clock jitter speci fications are met. This means for DDR2-800; 6-6-6, of which tRP = 15ns, the device will support tnRP = RU (tRP/tCK [AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0+6 are valid even if six clocks are less than 15ns due to input clock jitter. During READs and WRITEs with AUTO PRECHARGE, the DDR3 32. SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. When operating in DLL disable mode, the greater of 4CK or 15ns is 33. satisfied for tWR. The start of the write recovery time is defined as follows: 34. For BL8 ( fixed by MRS and OTF): Rising clock edge four clock • cycles after WL. For BC4 (OTF): Rising clock edge four clock cycles after WL. • For BC4 (fixed by MRS): Rising clock edge two clock cycles after • WL. RESET\\ should be LOW as soon as power starts to ramp to ensure 35. the outputs are in HIGH-Z Until RESET\\ is LOW, the outputs are at risk of driving the bus and could result in excessive current, depending on the bus activity. The refresh period is 64ms when Tc is less than or equal to 85 ˚C. 36. This equates to an average refresh rate of 7.8124 μs. However, nine REFRESH commands should be asserted at least once every 70.3μs. When Tc is greater than 85˚C, the refresh period is 32ms and when Tc is greater than 105˚C, the refresh period is 24ms. Although CKE is allowed to be registered LOW after a REFRESH 37. command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. ODT turn-on time MIN is when the device leaves HIGH-Z and ODT 38. resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 23. Half-clock output parameters must derated by the actual 39. tERR10PER and tJITDTY when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF(MIN) are each required to be derated by subtracting both tER- R10PER (MAX) and tJITDTY (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by subtracting both tER- R10PER (MAX) and tJITDTY (MAX). ODT turn-off time minimum is when the device starts to turn off ODT 40. resistance. ODT turn-off time maximum is when the SDRAM buffer is in HIGH-Z. The ODT reference load is shown in Figure 24. This output load is used for ODT timings (see Figure 31). Pulse width of an input signal is defined as the width between the first 41. crossing of V REF (DC) and the consecutive crossing of VREF(DC). Should the clock rate be larger than 42. tRFC(MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25MHz) all REFRESH commands should be fol- lowed by a PRECHARGE ALL command.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product COMMAND AND ADDRESS SETUP, HOLD, AND DERATING The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH (base) values (Tables 51) to the ∆tIS and ∆tIH derating values (Table 52), respectively. Although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the transition and to reach VIH(AC)/VIL(AC) (see Figure 14 for input signal requirements). For slew rates which fall between the values listed in Table 52 and Table 53, the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded “VREF(DC)-to-AC region”, use the nominal slew rate for derating value (see Figure 25). If the actual signal is later than the nominal slew rate line anywhere between the shaded “V REF(DC)-to-AC region”, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see Figure 27). Hold (tIH) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of V IL(DC) MAX and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded “DC-to-V REF(DC) region”, use the nominal slew rate for derating value (see Figure 26). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded ”DC-to-VREF(DC) region”, the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for the derating value (see Figure 28). Symbol DDR3-800 DDR3-1066 DDR3-1333 UNITS REFERENCE tIS(base)AC175 tIS(base)AC150 tIH(base)DC100 VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) TABLE 51: COMMAND AND ADDRESS SETUP AND HOLD VALUES REFERENCED AT 1V/NS – AC/DC BASED 190 140 200 350 275 125 275 200 ps ps ps 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 TABLE 52: DERATING VALUES FOR tIS/tIH – AC175/DC100-BASED CMD/ADDR Slew Rate V/ns -11 -17 -35 -62 -10 -16 -26 -40 -60 -11 -17 -35 -62 -10 -16 -26 -40 -60 -11 -17 -35 -62 -10 -16 -26 -40 -60 -27 -54 -18 -32 -52 -27 -54 -10 -24 -44 112 -11 -38 -16 -36 120 -30 -26 128 -22 100 -10 CK, CK\\ Differential Slew Rate Shaded cells indicate slew-rate combinations not supported ∆tIS, ∆tIH Derating (ps) - AC/DC-Based, AC175 Threshold; VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 TABLE 53: DERATING VALUES FOR tIS/tIH – AC150/DC100-BASED CMD/ADDR Slew Rate V/ns -10 -25 -10 -16 -26 -40 -60 -10 -25 -10 -16 -26 -40 -60 -10 -25 -10 -16 -26 -40 -60 -17 -18 -32 -52 -10 -24 -44 -16 -36 107 -26 115 100 -10 CK, CK\\ Differential Slew Rate ∆tIS, ∆tIH Derating (ps) - AC/DC-Based, AC150 Threshold; VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV Shaded cells indicate slew-rate combinations not supported Slew Rate (V/ns) tVAC at 175mV(ps) tVAC at 150mV(ps) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 175 170 167 163 162 161 159 155 150 150 TABLE 54: MINIMUM REQUIRED TIME tVAC ABOVE VIH(AC) FOR A VALID TRANSITION Below VIL(AC)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Setup slew rate rising signal Setup slew rate falling signal ∆TF ∆TR VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(DC) MAX Nominal slew rate VREF to AC region tVAC tVAC DQS DQS# CK# CK tIS tIH tIS tIH Nominal slew rate VREF to AC region VREF(DC) - VIL(AC) MAX ∆TF VIH(AC) MIN - VREF(DC) ∆TR FIGURE 25 - NOMINAL SLEW RATE AND tVAC FOR tIS (COMMAND AND ADDRESS – CLOCK)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 26 - NOMINAL SLEW RATE FOR tIH (COMMAND AND ADDRESS – CLOCK) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hold slew rate falling signal Hold slew rate rising signal ∆TR ∆TF = = VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Nominal slew rate DC to VREF region DQS DQS# CK# CK tIS tIH tIS tIH DC to VREF region Nominal slew rate VREF(DC) - VIL(DC) MAX ∆TR VIH(DC) MIN - VREF(DC) ∆TF

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 27 - TANGENT LINE FOR tIS (COMMAND AND ADDRESS – CLOCK) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Setup slew rate rising signal Setup slew rate falling signal ∆TF ∆TR VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Tangent line VREF to AC region Nominal line tVAC tVAC DQS DQS# CK# CK tIS tIH tIS tIH VREF to AC region Tangent line Nominal line Tangent line (VIH [DC] MIN - VREF[DC ]) ∆TR Tangent line (VREF [DC] - VIL[AC] MAX) ∆TF

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 28 - TANGENT LINE FOR tIH (COMMAND AND ADDRESS – CLOCK) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hol d slew rate falling signal ∆TR VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Tangent line DC to VREF region Hol d slew rate rising signal = DQS DQS # CK# CK tIS tIH tIS tIH DC to VREF region Tangent line Nominal line Nominal line ∆TR Tangent line (VREF [DC] - VIL[DC] MAX) ∆TR Tangent line (VIH [DC] MIN - VREF[DC]) ∆TF

2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 TABLE 56: DERATING VALUE FOR tDS/tDH – AC175/DC100 - BASED DQ DQS, DQS# Differential Slew Rate ∆tDS, ∆tDH Derating (ps) – AC175/D100-Based Shaded cells indicate slew-rate combinations not supported LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product DATA SETUP, HOLD AND DERATING The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see Table 55) to the ∆tDS and ∆tDH derating values (see Table 56), respectively. Although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the transition and to reach VIH/VIL(AC). For slew rates which fall between the values listed in Table 57, the derating values may be obtained by linear interpolation. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded “VREF(DC)-to-AC region”, use the nominal slew rate derating value (see Figure 29). If the actual signal is later than the nominal slew rate line anywhere between the shaded “VREF(DC)-to-AC region”, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see Figure 31). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded “DC-to-V REF(DC) region”, use the nominal slew rate for derating value (see Figure 30). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded “DC-to-VREF(DC) region”, the slew rate of a tangent line to the actual signal from the “DC-to-VREF(DC) region”, is used for the derating value (see Figure 32). Symbol DDR3-800 DDR3-1066 DDR3-1333 UNITS REFERENCE tDS(base)AC175 tDS(base)AC150 tDS(base)DC100 VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) TABLE 55: DATA SETUP AND HOLD VALUES AT 1V/NS (DQSX, DQSX\\ AT 2V/NS) – AC/DC BASED 125 150 100 ps ps ps -10 -10 -11 -16 -30 -26 -22 -10

2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 TABLE 57: DERATING VALUE FOR tDS/tDH – AC150/DC100 - BASED DQ Slew DQS, DQS# Differential Slew Rate ∆tDS, ∆tDH Derating (ps) – AC150/DC100-Based Shaded cells indicate slew-rate combinations not supported LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product -10 -10 -16 -26 -10 Slew Rate (V/ns) tVAC at 175mV(ps) [MIN] tVAC at 150mV(ps) [MIN] >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 175 170 167 163 162 161 159 155 150 150 TABLE 58: REQUIRED TIME tVAC ABOVE VIH(AC) (BELOW VIL[AC]) FOR A VALID TRANSITION

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 29 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Setup slew rate rising signal Setup slew rate ∆TF ∆TR = = VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Nominal slew rate VREF to AC region tVAC tVAC tDHtDS DQS DQS# tDHtDS CK# CK VREF to AC region Nominal slew rate VIH(AC) MIN - VREF (DC) ∆TR VREF(DC) - VIL(AC) MAX ∆TF rising signal

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 30 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hold slew rate falling signal Hold slew rate rising signal ∆TR ∆TF VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Nominal slew rateDC to VREF region tDHtDS DQS DQS# tDHtDS CK# CK DC to VREF region Nominal slew rate VREF(DC) - VIL(DC) MAX ∆TR VIH(DC) MIN - VREF(DC) ∆TF

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 31 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Setup slew rate rising signal Setup slew rate falling signal ∆TF ∆TR VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Tangent line VREF to AC region Nominal line tVAC tVAC tDHtDS DQS DQS# tDHtDS CK# CK VREF to AC region Tangent line Nominal line ∆TR Tangent line (VREF[DC] - VIL[AC] MAX) ∆TF Tangent line (V IH[AC] MIN - VREF [DC])

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 32 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hold slew rate falling signal ∆TF∆TR VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Tangent line DC to VREF region Hold slew rate DQS DQS# CK# CK DC to VREF region Tangent line Nominal line Nominal line Tangent line (VIH [DC] MIN - VREF[DC]) ∆TF Tangent line (VREF[DC] - VIL[DC] MAX) ∆TR tDS tDH tDS tDH falling signal

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product PACKAGE OUTLINE DIMENSIONS Function Symbol Cycle Cycle CS\\ RAS\\ CAS\\ WE\\ BA[2:0] An A12 A10 A[11,0:0] Notes Mode Register Set REFRESH SELF REFRESH entry SELF REFRESH exit Single-Bank PRECHARGE PRECHARGE all banks Bank ACTIVATE NO OPERATION Device DESELECTED POWER-DOWN entry POWER-DOWN exit ZQ CALIBRATION LONG ZQ CALIBRATION SHORT 6,7 6,11 TABLE 59: TRUTH TABLE - COMMAND L L L L L L L L L L L L L L L L L L L H L L L L L L L L H H H H H H H H H H H H H X H H L L L L L L H H H H H H H H H H H H H X H H L H H L L H L L L L L L H H H H H H H X L L BA V V V VBA V BA BA BA BA BA BA BA BA BA BA BA BA BA V X V V X X V V V V V RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU V X V V X X V V V V V V L H V L H V L H V L H V X V V X X V V V L H L L L H H H L L L H H H V X V V H L V V V V V CA CA CA CA CA CA CA CA CA CA CA CA CA V X V V X X MRS REF SRE SRX PRE PREA ACT WR WRS4 WRS8 WRAP WRAPS4 WRAPS8 RD RDS4 RDS8 RDAP RDAPS4 RDAPS8 NOP DES PDE PDX ZQCL ZQCS H H H L H H H H H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H H H H H L H H H WRITE WRITE with AUTO PRECHARGE READ READ with AUTO PRECHARGE BL8MRS BC4MRS BC4OTF BL8OTF BL8MRS BC4MRS BC4OTF BL8OTF BL8MRS BC4MRS BC4OTF BL8OTF BL8MRS BC4MRS BC4OTF BL8OTF H L L H L H V H V H V H H V H V H V H V H V H V CKE Prev Next Burst READs or WRITEs cannot be terminated or interrupted, MRS 8. (fixed) and OTF BL/BC are defined in MR0. The purpose of the NOP command is to prevent the SDRAM from reg-9. istering any unwanted commands. A NOP will not terminate and opera- tion that is in execution. The DES and NOP commands perform similarly.10. The POWER-DOWN mode does not perform any REFRESH opera-11. tions. ZQ CALIBRATION LONG is used for either ZQINT ( first ZQCL com-12. mand during initialization) or ZQOPER (ZQCL command after initializa- tion). NOTES: Commands are defined by states of CS\\, RAS\\, CAS\\, WE\\, and CKE at 1. the rising edge of the clock. The MSB of BA, RA, and CA are device- density and configuration-dependent. RESET\\ is LOW enabled and used only for asynchronous RESET. Thus, 2. RESET\\ must be held HIGH during any normal operation. The state of ODT does not affect the states described in this table.3. Operations apply to the bank defined by the bank address. For MRS, BA 4. selects one of four mode registers. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care”.5. See Table 59 for additional information on CKE transition.6. SELF REFRESH exit is asynchronous.7. COMMANDS TRUTH TABLE

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Current State 3 POWER-DOWN SELF REFRESH Bank(s) ACTIVE READING WRITING PRECHARGING REFRESHING All Banks IDLE TABLE 60: TRUTH TABLE - CKE L H L H L L L L L L (n-1) Previous Cycle 4 (n) Present Cycle 4 (RAS\\, CAS\\, WE\\, CS\\) Command 5 Action 5 Notes L L L H H H H H H H “Don’t Care” DES or NOP “Don’t Care” DES or NOP DES or NOP DES or NOP DES or NOP DES or NOP DES or NOP REFRESH Maintain POWER-DOWN POWER-DOWN exit Maintain SELF REFRESH SELF REFRESH exit Active POWER-DOWN entry POWER-DOWN entry POWER-DOWN entry PRECHARGE POWER-DOWN entry PRECHARGE POWER-DOWN entry SELF REFRESH 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,6 CKE CKE (n) is the logic state of CKE at clock edge n, CKE (n-1) was the 4. state of CKE at the previous clock edge. COMMAND is the command registered at the clock edge (must be a 5. legal command as de fined in Table 58). Action is a result of COM- MAND. ODT does not affect the states described in this table and is not listed. Idle state = all banks are closed, no data bursts are in progress, CKE is 6. HIGH and all timings from previous operations are satis fied. All SELF REFRESH exit and POWER-DOWN exit parameters are also satis- fied. NOTES: All states and sequences not shown are illegal or reserved unless explic-1. itly described elsewhere in this document. t2. CKE(MIN) means CKE must be registered at multiple consecutive posi- tive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE(MIN) + tIH. Current state = The state of the SDRAM immediately prior to clock edge 3. DESELECT (DES) The DES command (CS\\ HIGH) prevents new commands from being exe- cuted by the SDRAM. Operations already in progress are not affected. NO OPERATION (NOP) The NOP command (CS\\ LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ZQ CALIBRATION ZQ Calibration LONG (ZQCL) The ZQCL command is used to perform the initial calibration during a power-up initialization and reset sequence. This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the SDRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the SDRAM I/O, which are reflected as updated RON and ODT values. The SDRAM is allowed a timing window de fined by either tZQINIT or tZQOPER to perform the full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQINIT must be satis fied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQOPER to be satisfied. ZQ Calibration SHORT (ZQCS) The ZQCS command is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON and RTT impedance errors within 64 clock cycles, assuming the maximum sensitivities specified in Table 40 and Table 41.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ACTIVATE The ACTIVATE command is used to open (or ACTIVATE) a row in a particular bank for a subsequent access. The value on the BA [2:0] inputs selects the bank, and the address provided on inputs A[n:0] selects the row. This row remains open (or ACTIVE) for accesses until a PRE- CHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst READ access to an ACTIVE row. The address provided on inputs A[2:0] selects the starting column address depending on the burst length and burst type selected (see table 65). The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be PRE- CHARGED at the end of the READ burst. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the MODE REGISTER) when the READ command is issued, determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. A summary of READ commands is shown in Table 61. TABLE 61: READ COMMAND SUMMARY Function Symbol Cycle Cycle CS\\ RAS\\ CAS\\ WE\\ BA[2:0] An A12 A10 A[11,0:0] Notes L L L L L L H H H H H H L L L L L L H H H H H H BA BA BA BA BA BA RFU RFU RFU RFU RFU RFU V L H V L H L L L H H H CA CA CA CA CA CA RD RDS4 RDS8 RDAP RDAPS4 RDAPS8 H H H H H H CKE Prev Next READ READ with AUTO PRECHARGE BL8MRS BC4MRS BC4OTF BL8OTF BL8MRS BC4MRS BC4OTF BL8OTF WRITE The WRITE command is used to initiate a burst WRITE access to an ACTIVE row. The value on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or not AUTO PRECHARGE is used. The value on input A12 (if enabled in the MODE REGISTER [MR]) when the WRITE command is issued, determines whether BC4 (chop) or BL8 is used. The WRITE command summary is shown in Table 62. TABLE 62: WRITE COMMAND SUMMARY Function Symbol Cycle Cycle CS\\ RAS\\ CAS\\ WE\\ BA[2:0] An A12 A10 A[11,0:0] Notes L L L L L L H H H H H H L L L L L L L L L L L L BA BA BA BA BA BA RFU RFU RFU RFU RFU RFU V L H V L H L L L H H H CA CA CA CA CA CA WR WRS4 WRS8 WRAP WRAPS4 WRAPS8 H H H H H H CKE Prev Next WRITE WRITE with AUTO PRECHARGE BL8MRS BC4MRS BC4OTF BL8OTF BL8MRS BC4MRS BC4OTF BL8OTF

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product The PRECHARGE command is used to DEACTIVATE the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access at a specified time ( tRP) after the PRECHARGE command is issued, except in the case of concurrent AUTO PRECHARGE. A READ or WRITE command to a different bank is allowed during concurrent AUTO PRECHARGE as long as it does not interrupt the data transfer in the cur- rent bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are precharged. In the case where only one bank is recharged. Inputs BA[2:0] select the bank; otherwise, BA[2:0] are treated as “Don’t Care”. After a bank is PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE com- mands being issued to that bank. A PRECHARGE command is treated as a NOP if there is no open row in that bank (idle state) or if the previ- ously open row is already in the process of precharging. However, the PRECHARGE period is determined by the last PRECHARGE command issued to the bank. PRECHARGE REFRESH is used during normal operation of the SDRAM and is analogous to CAS\\-before RAS\\ (CBR) refresh or AUTO REFRESH. This command is non-persistent, so it must be issued each time a REFRESH is required. The addressing is generated by the internal REFRESH command. The SDRAM requires REFRESH cycles at an average interval of 7.8μs (maximum when Tc≤85˚C or 3.9 μs MAX when Tc ≤95˚C). The REFRESH period begins when the REFRESH command is registered and ends tRFC (MIN) later. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute REFRESH interval is provided. A maximum of eight REFRESH commands can be posted to any given SDRAM, mean- ing that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate. SELF REFRESH may be entered with up to eight REFRESH commands being posted. After exiting SELF REFRESH (when entered with posted REFRESH commands) additional posting of REFRESH commands is allowed to the extent the maximum number of cumulative posted REFRESH commands (both pre and post SELF REFRESH) does not exceed eight REFRESH commands. REFRESH FIGURE 33 - REFRESH MODE Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see “Power-Down Mode” on page 153). NOP1NOP1 NOP1PRE RA Bank(s) 3 BA REF NOP 1 REF2 NOP1 ACTNOP1 One bank All banks tCK tCH tCL RA tRFC2tRP tRFC (MIN) T0 T1 T2 T3 T4 Ta0 Tb0Ta1 Tb1 Tb2 Don’t CareIndicates A Break in Time Scale Valid1 Valid1 Valid1 CK CK# Command CKE Address A10 BA[2:0] DQ4 DM4 DQS, DQS#4

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product The SELF REFRESH command is used to retain data in the SDRAM, even if the rest of the system is powered down. When in the SELF REFRESH mode, the SDRAM retains data without external clocking. The SELF REFRESH mode is also a convenient method used to enable/disable the DLL as well as to change the clock frequency within the allowed synchronous operating range. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode operation. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode under certain conditions:

• Vss< VREFDQ< Vcc is maintained
• VREFDQ is valid and stable prior to CKE going back HIGH
• The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid
• All other SELF REFRESH mode exit time requirements are met. SELF REFRESH If the DLL is disabled by the MODE REGISTER (MR1[0] can be switched during initialization or later), the SDRAM is targeted, but not guaranteed to operate similarly to the NORMAL mode with a few notable exceptions: The SDRAM supports only one value of CAS latency (CL=6) and one value of CAS WRITE latency (CWL=6).• DLL DISABLE mode affects the READ data clock-to-data strobe relationship (• tDQSCK), but not the READ data-to-data strobe relationship (tDQSQ, tQH). Special attention is needed to line the READ data up with the controller time domain when the DLL is disabled. In NORMAL operation (DLL on), • tDQSCK starts from the rising clock edge AL + CL cycles after the READ command. In DLL DISABLE mode, tDQSCK starts AL = CL – 1 cycles after the READ command. Additionally, with the DLL disabled, the value of tDQSCK could be larger than tCK. The ODT feature is not supported during DLL DISABLE mode (including dynamic ODT). The ODT resistors must be disabled by contin uously registering the ODT ball LOW by programming RTT_NORM MR1[9,6,2] and RTT_WR MR2[10,9] to “0” while in DLL DISABLE mode. Specific steps must be followed to switch between the DLL enable and DLL DISABLE modes due to a gap in the allowed clock rates between the two modes (tCK[AVG]MAX and tCK[DLL DISABLE] MIN, respectively). The only time the clock is allowed to cross this clock rate gap is during SELF REFRESH mod e. Thus, the required procedure for switching from the DLL ENABLE to DLL DISABLE mode is to change frequency curing self refresh (see Figure 34): Starting from the IDLE state (all banks are PRECHARGED, all timings are ful filled, ODT is turned off, and R1. TT_NOM and R TT_WR are HIGH-Z), set MR1[0] to “1” to DISABLE the DLL. Enter SELF REFRESH mode after 2. tMOD has been satisfied. After 3. tCKSRE is satisfied, change the frequency to the desired clock rate. SELF REFRESH may be exited when the clock is stabled with the new frequency for 4. tCKSRX. The SDRAM will be ready for its next command in the DLL DISABLE mode after the greater of 5. tMRD or tMOD has been satisfied. A ZQCL command should be issued with appropriate timing met as well. DLL DISABLE MODE

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 34 - DLL ENABLE MODE TO DLL DISABLE MODE Command T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 CK CK# ODT9 Valid1 Don’t Care Valid1 SRE3 NOPMRS2 NOP SRX4 MRS5 Valid1NOP NOP Indicates a Break in Time Scale tMOD tCKSRE tMODtXS tCKESR CKE tCKSRX8 NOTES: Any valid command.1. Disable DLL by setting MR1[0] to “1.”2. Wait 3. tXS, then set MR1[0] to “0” to enable DLL. Wait 4. tMRD, then set MR0[8] to “1” to begin DLL RESET. Wait 5. tMRD, update registers (CL, CWL, and write recovery may be necessary). Wait 6. tMOD, any valid command. Starting with the idle state.7. Change frequency.8. Clock must be stable at least 9. tCKSRX. Static LOW in case R10. TT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changin g the frequency during self refresh mode (see Figure 44 on page 100). 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to “0” to enable the DLL. Wait tMRD, then set MR0[8] to “1” to enable DLL RESET. 4. After another tMRD delay is satisfied, then update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satisfied. A ZQCL command should be issued with the appropriate timings met as well.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 35- DLL DISABLE MODE TO DLL ENABLE MODE Indicates a Break in Time Scale tC tDLLK CKE T0 T a0T a1T b 0 T c0T c1T d 0T e0 Tf0 T g0 CK CK# ODT10 SRE1 NOPCommand NOP SRX2 MRS3 MRS4 MRS5 Valid6 Valid Don’t Care 87 tCKSRE Th0 tCKSRX9 ODTL off + 1 × tCK tXS tMRD tMRD KESR NOTES: Enter SELF REFRESH.1. Exit SELF REFRESH.2. Wait 3. tXS, then set MR1[0] to “0” to enable DLL. Wait 4. tMRD, then set MR0[8] to “1” to begin DLL RESET. Wait 5. tMRD, update registers (CL, CWL, and write recovery may be necessary). Wait 6. tMOD, any valid command. Starting with the idle state.7. Change frequency.8. Clock must be stable at least 9. tCKSRX. Static LOW in case R10. TT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. The clock frequency range for the DLL disable mode is speci fied by the parameter tCKDLL_DIS. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are supported. DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK) but not the data strobe to data relationship (tDQSQ, tQH). Special atten- tion is needed to the controller time domain. Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles after the READ command (see Figure 45 on page 101). WRITE operations function similarly between the DLL enable and DLL disable modes; however, ODT functionality is not allowed with DLL disable mode.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 36 - DLL DISABLE tDQSCK TIMING T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Don’t CareTransitioning Data Valid NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command Address DI b + 3DI b + 2DI b + 1DI b DI b + 7DI b + 6DI b + 5DI b + 4 DQ BL8 DLL on DQS , DQS# DLL on DQ BL8 DLL disable DQS , DQS# DLL off DQ BL8 DLL disable DQS , DQS# DLL off RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6 DI b + 3DI b + 2DI b + 1DI b DI b + 7DI b + 6DI b + 5DI b + 4 DI b + 3DI b + 2DI b + 1DI b DI b + 7DI b + 6DI b + 5DI b + 4 tDQSCK (DLL_DIS) MIN tDQSCK (DLL_ DIS) MAX RL (DLL disable) = AL + (CL - 1) = 5 When the DDR3 SDRAM is initialized, it requires the clock to be stable during most NORMAL states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another under two conditions: SELF REFRESH mode and PRECHARGE power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the SELF REFRESH mode condition, when the DDR3 SDRAM has been successfully placed into SELF REFRESH mode and tCKSRE has been satisfied, the state of the clock becomes a “Don’t Care”. When the clock becomes a “Don’t Care”, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the SELF REFRESH entry and exit specifications must still be met. The PRECHARGE power-down mode condition is when the DDR3 SDRAM is in PRECHARGE power-down mode (either fast exit mode or slow e xit mode). Either ODT must be at a logic LOW or RTT_NOM and RTT_WR must be disabled via MR1 and MR2. This ensures RTT_NOM and RTT_WR are in an off state prior to entering PRECHARGE power-down mode while maintaining CKE at a logic LOW. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency speci- fied for the particular speed/temperature grade (tCK [AVG] MIN to tCK [AVG] MAX) device. During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the SDRAM, tCKSRX before PRECHARGE power-down may be exited. After PRECHARGE power-down is exited and tXP has been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time, R TT_NOM and RTT_WR must remain in an off state. After the DLL lock time, the SDRAM is ready to operate with a new clock frequency (period). This process is depicted in Figure 37. INPUT CLOCK FREQUENCY CHANGE

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 37- CHANGE FREQUENCY DURING PRECHARGE POWER-DOWN CK CK# Command NOPNOPNOP Address CKE DQ DM DQS, DQS# NOP tCK Enter precharge power-down mode Exit precharge power-down mode T0 T1 Ta0 Tc0 Tb0T2 Don’t Care tCKE tXP MRS DLL RESET Valid Valid NOP tCH tIH tIS tCL Tc1 Td0 Te1 Td1 tCKSRE tCHb tCLb tCKb tCHb tCLb tCKb tCHb tCLb tCKb tCPDED ODT NOP Te0 Previous clock frequency New clock frequency Frequency change Indicates a Break in Time Scale tIH tIS tIH tIS tDLLK tAOFPD/ tAOF tCKSRX High-Z High-Z NOTES: Applicable for both slow-exit and fast-exit precharge power-down modes.1. t2. AOFPD and tAOF must be satis fied and outputs High-Z prior to T1 (see “On-Die Termination (ODT)” on page 161 for exact requirements). If the R3. TT_NOM feature was enabled in the mode register prior to entering precharge power-down mode, the ODT signal must be continuously registered LOW ensuring R TT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering precharge power-down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product For better signal integrity, DDR3 SDRAM memory sub-system designs have adopted use of fly-by topology for the commands, addresses, control signals and clocks. WRITE leveling is a scheme for the memory controller to de-skew the DQSx strobe (DQSx, DQSx\\) to CK relationship at th e SDRAM with a simple feedback feature provided it by the DDR3 SDRAM itself. WRITE leveling is generally used as part of the initialization process, if required. For NORMAL SDRAM operation, this feature must be disabled. This is the only SDRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQs function as outputs (to report the stat of the clock). Note that nonstandard ODT schemes are required. The memory controller using the WRITE leveling procedure must have adjustable delay setting on its DQS strobe to align the rising edge of DQS to the clock at the SDRAM pins. This is accomplished when the SDRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from “0” to “1” is detected. The DQS delay establi shed through this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly by topology by de-skewing the trace length mismatch. A conceptual timing of this procedure is shown in Figure 38. WRITE LEVELING FIGURE 38- WRITE LEVELING CONCEPT CK CK# Source Differential DQS Differential DQS Differential DQS DQ DQ CK CK# Destination Destination Push DQS to capture 0–1 transition T0 T1 T2 T3 T4 T5 T6 T7 T0 T1 T2 T3 T4 T5 T6 Tn CK CK# T0 T1 T2 T3 T4 T5 T6 Tn Don’t Care 1 1 0 0

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product When WRITE leveling is enabled, the rising edge of DQS samples CK and the rime DQ outputs the sampled CK’s status. The prime D Q for each of the (4) words contained in the iMOD is DQ0 for the low byte, DQ8 for the high byte. It outputs the status of CK sampled by LDQSx a nd UDQSx. All other DQs (DQ[7:1], DQ[15:9] for the low word, DQ[23:17],DQ[31:25] for the next word, DQ[39:33], DQ[47:41] for the next and DQ[55:49], DQ[63:57] for the HIGH word) continue to drive LOW. Two prime DQ on each of the (4) words contained in the LDI iMOD allow each byte lane to be leveled independently. WRITE LEVELING A memory controller initiates the SDRAM WRITE Leveling mode by setting the MR1[7] to a “1”, assuming the other programmable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the WRITE Leveling mode going from a “HIGH-Z” state to an undefined driv- ing state so the DQ bus should not be driven. During WRITE Leveling mode, only the NOP and DES commands are allowed. The memo ry controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to a “1”. The memory controller may assert ODT after a tMOD delay as the SDRAM will be ready to process the ODTL on delay (WL-2 tCK), provided it does not violate the aforementioned tMOD delay requirement. The memory controller may drive LDQSx, UDQSx LOW and LDQSx\\, UDQSx\\ HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle LDQSx, UDQSx after tWLMRD (one L[U]DQSs toggle is DQSs transitioning from a LOW state to a HIGH state with L[U]DQSx\\ transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a minimum, ODTL on and tAON must be satis fied at least one clock prior to DQS tog- gling. After tWLMRD and DQS LOW preamble (tWPRE) have been satisfied, the memory controller may provide either a single DQSx toggle or multiple DQSx toggles to sample CK for a given DQSx to CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH (MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable during WRITE leveling mode. The DQSx must be able to distinguish the CK’s rising edge within tWLS and tWLH. The prime DQ will output the CK’s status asynchronously from the associated DQSx rising edge CK capture within tWLO. The remaining DQs that always drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is satisfied (the prime DQs going LOW). As previously noted, DQSx is an input and not an output during this process. Figure 39 depicts the basic timing parameters for the overall write leveling procedure. The memory controller will likely sample each applicable prime DQ state and determine whether to increment or decrement it DQS delay setting. After the memory controller performs enough DQSx toggles to detect the CK’s “0-1” transition, the memory controller should lock the DQS delay setting for the SDRAM iMOD device. After locking the DQS setting, leveling for the rank will have been achieved, and the WRITE leveling mode for the rank should be disabled or reprogrammed (if WRITE leveling of another rank follows). WRITE LEVELING PROCEDURE

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 39- WRITE LEVELING SEQUENCE CK CK# Command T1 T2 Early remaining DQ Late remaining DQ tWLOE NOP2 NOP MRS1 NOP NOP tWLStWLH Don’t CareUndefined Driving ModeIndicates a Break in Time Scale Prime DQ5 Differential DQS4 ODT tMOD tDQSL3 tDQSH3 tDQSH3 tWLO tWLMRD tWLDQSEN tWLO tWLO tWLO tDQSL3 NOP NOP NOP NOP NOP NOP NOP NOTES: MRS: Load MR1 to enter write leveling mode.1. NOP: NOP or DES.2. DQS, DQS# needs to ful fill minimum pulse width requirements 3. tDQSH (MIN) and tDQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero 4. crossings. The solid line represents DQS; the dotted line represents DQS#. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven 5. LOW and remain in this state throughout the leveling procedure. After the DDR3 SDRAM iMOD has been WRITE leveled, the controller must exit from WRITE Leveling mode before the NORMAL mode can be used. Figure 40 depicts a general procedure in exiting WRITE Leveling. After the last rising DQS (capturing a “1” at T0), the memory controller should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at – Tb0). The DQ balls become undefined when DQS no longer remains LOW and they remain undefined until tMOD after the MRS command (at Te1). The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the DQSx is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at –Tb0) until the SDRAM is ready for either another rank to be leveled or until the NORMAL mode can be used. After DQS termination is switched off, WRITE level mode should be disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid command may be registered by the SDRAM. Some MRS commands may be issued after tMRD (at Td1). WRITE LEVELING EXIT MODE

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 40- EXIT WRITE LEVELING Notes: 1. The DQ result, “= 1,” between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state. NOP CK T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1 CK# Command ODT RTT_DQ NOP R MPONPONPONPONPON S NOP NOP Address MR1 Valid Valid Valid Valid Don’t CareTransitioning RTT DQS , RTT DQS R# TT_NOM Undefined Driving Mode tAOF (MAX) tMRD Indicates a Break in Time Scale DQS, DQS# CK = 1DQ tIS tAOF (MIN) tMOD tWLO + tWLOE ODTL off

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Initialization The following sequence is required for power up and initialization, as shown in Figure 41. Apply power. RESET\\ is recommended to be below 0.2 x VccQ during power ramp to ensure the outputs remain disabled (HIGH-Z) and 1. ODT off (RTT is also HIGH-Z). All other inputs, including ODT may be undefined. During power up, either of the following conditions may exist and must be met: Condition A:• Vcc and VccQ are driven from a single power source and are ramped with a maximum delta voltage between them of ∆V≤300mV. • Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than Vcc, VccQ, Vss and VssQ must be less than or equal to VccQ and Vcc on one side and must be greater than or equal to VssQ and Vss on the other side. Both Vcc and VccQ power supplies ramp to Vcc (MIN) and VccQ (MIN) within • tVccPR=200ms. Both Vcc and VccQ power supplies ramp to Vcc (MIN) and VccQ (MIN) within • tVccPR=200ms. V• REFDQ tracks Vcc x 0.5, VREFCA tracks Vcc x 0.5. V• TT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latchup.

• Condition B: Vcc may be applied before or at the same time as VccQ.• VccQ may be applied before or at the same time as V• TT, VREFDQ and VREFCA. No slope reversals are allowed in the power supply ramp for this condition.• Until stable power, maintain RESET\\ LOW to ensure the outputs remain disabled (HIGH-Z). After the power is stable, RESET\\ must be 2. LOW for at least 200 μs to begin the initialization process. ODT will remain in the HIGH-Z state while RESET\\ is LOW and until CKE is registered HIGH. CKE must be LOW 10ns prior to RESET\\ transitioning HIGH.3. After RESET\\ transitions HIGH, wait 500μs (minus one clock) with CKE LOW.4. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be 5. present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete. After CKE is registered HIGH and after 6. tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1). Issue an MRS command to MR3 with the applicable settings.7. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT.8. Issue and MRS command to MR0 with the applicable settings, including a DLL RESET command. 9. tDLLK (512) cycles of clock input are required to lock the DLL. Issue a ZQCL command to calibrate R10. TT and RON values for the process voltage temperature (PVT). Prior to NORMAL operation. tZQINIT must be satisfied. When 11. tDLLK and tZQINIT have been satisfied, the DDR3 SDRAM will be ready for normal operation. OPERATIONS

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 41- INITIALIZATION SEQUENCE CKE RTT BA[2:0] All voltage supplies vali d and stable T = 200μs (MIN) DM DQS Address A10 CK CK# tCL Command NOP T0 Ta0 Don’t Care tCL tIS tCK ODT DQ Tb0 tDLLK MR1 with DLL ena ble MR0 with DLL reset tMRD tMOD MRSMRS BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L C ode C ode C ode C ode Valid Valid Valid Valid Normal operation MR2 MR3 tMRD tMRD MRSMRS BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L C ode C ode C ode C ode Tc0 Td 0 VTT VREF VCCQ VCC RESET# T = 500μs (MIN) tCKS RX Stable and valid clock Valid Power-up ramp T (MAX) = 200ms DRAM ready for external commands tZQINIT ZQ calibration A10 = H ZQCL tIS See power-up c onditions in the initialization sequen ce text, set up 1 tXPR Valid = 20nstIOz Indicates a Break in Time Scale T (MIN) = 10ns tVTD

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Mode registers (MR0-MR3) are used to de fine various modes of programmable operation of the DDR3 SDRAM iMOD. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization and it retains the stored information (except for MR0[8] which is self-clearing) until it is either reprogrammed, RESET\\ goes LOW, or until the device loses power. Contents of a mode register can be altered by re-executing the MRS command. If the user chooses to modify only a subset of the mode register’s variables, all variables must be programmed when the MRS command is issued. Reprogramming the mode register will not alter the contents o f the memory array, provided it is performed correctly. The MRS command can only be issued (or re-issued) when all banks are idle and in the PRECHARGED state (tRP is satisfied and no data bursts are in prog- ress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands (see Figure 42). MODE REGISTERS FIGURE 42- MRS-TO-MRS COMMAND TIMING (tMRD) Valid Valid MRS1 MRS2NOP NOP NOP NOP T0 T1 T2 Ta0 Ta1 Ta2 CK# CK Command Address CKE3 Don’t CareIndicates a Break in Time Scale tMRD NOTES: Prior to issuing the MRS command, all banks must be idle and precharged, 1. tRP (MIN) must be satisfied, and no data bursts can be in progress.the leveling procedure. t2. MRD specifies the MRS-to-MRS command minimum cycle time. CKE must be registered HIGH from the MRS command until 3. tMRSPDEN (MIN) (see “Power-Down Mode” on page 153). For a CAS latency change, 4. tXPDLL timing must be met before any nonMRS command. The controller must also wait tMOD before initiating any nonMRS commands (excluding NOP and DES), as shown in Figure 52 on page 111. The DRAM requires tMOD in order to update the requested features, with the exception of DLL RESET, which requires additional time. Until tMOD has been satisfied, the updated features are to be assumed unavailable.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 43- MRS-TO-NONMRS COMMAND TIMING (tMOD) CK CK# Command T1 T2 Early remaining DQ Late remaining DQ tWLOE NOP2 NOP MRS1 NOP NOP tWLStWLH Don’t CareUndefined Driving ModeIndicates a Break in Time Scale Prime DQ5 Differential DQS4 ODT tMOD tDQSL3 tDQSH3 tDQSH3 tWLO tWLMRD tWLDQSEN tWLO tWLO tWLO tDQSL3 NOP NOP NOP NOP NOP NOP NOP NOTES: Prior to issuing the MRS command, all banks must be idle (they must be precharged, 1. tRP must be satisfied, and no data bursts can be in progress). Prior to Ta2 when 2. tMOD (MIN) is being satis fied, no commands (except NOP/DES) may be issued. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied prior 3. to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until tMOD (MIN) is satisfied at Ta2. CKE must be registered HIGH from the MRS command until 4. tMRSPDEN (MIN), at which time power-down may occur (see “Power-Down Mode” on page 133). MODE REGISTER 0 (MR0) The base register, MR0 is used to de fine various DDR3 iMOD modes of operation. These de finitions include the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, WRITE recovery and PRECHARGE power-down mode, as shown in Figure 44.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product MODE REGISTER 0 (MR0) Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3], as shown in Figure 44. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 65. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleaved address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries. BURST TYPE BURST LENGTH Burst length is de fined by MR0[1:0] (see Figure 44). READ and WRITE accesses to the DDR3 SDRAM iMOD are burst-oriented, with the burst length being programmable to “4” (chop mode). “8” (fixed burst), or select- able using A12 during a READ/WRITE command (on the fly). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to “01” during a READ/WRITE command, if A12=0, then BC4 (chop) mode is selected. If A12=1, then BL8 mode is selected. Speci fic timing diagrams, and turnaround between READ/WRITE are shown in the READ/WRITE sections of this document. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A[i:2] when the burst length is set to “4” and by A[i:3] when the burst length is set to “8” (where Ai is the most significant column address bit for a given starting loca- tion within the block. The programmed burst length applies to both READ and WRITE bursts. FIGURE 44- MODE REGISTER 0 (MR0) DEFINITIONS Notes: 1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to “0.”

01 BLCAS# latency BTPD

A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode register 0 (MR0) Address bus 97 6 5 4 3 281 0 A10A12 A111AB0 AB 312 11 10 1 READ Burst Type Se quential (nibble) Interleaved CAS Latency Reserved DLL Write Recovery Reserved Reserved WR00 M12 Precharge PD DLL off (slow exit) DLL on (fast exit) BA2 Burst Length Fixed BL8 4 or 8 (on-the-fly via A12) Fixed BC4 (chop) Reserved M10 M11 M14 M15 Mode Register Mode register 0 (MR0) Mode register 1 (MR1) Mode register 2 (MR2) Mode register 3 (MR3) A13 01 01 DLL Reset No Yes

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Burst Length Read/Write Address (A[2,1,0]) Type = Sequential Type = Interleaved

4 CHOP

0,1,2,3,Z,Z,Z,Z 1,0,3,2,Z,Z,Z,Z 2,3,0,1,Z,Z,Z,Z 3,2,1,0,Z,Z,Z,Z 4,5,6,7,Z,Z,Z,Z 5,4,7,6,Z,Z,Z,Z 6,7,4,5,Z,Z,Z,Z 7,6,5,4,Z,Z,Z,Z 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 0,1,2,3,4,5,6,7 TABLE 65: BURST ORDER Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,3,4 1,3,4 1,3 Burst Type (Decimal) 0,1,2,3,Z,Z,Z,Z 1,2,3,0,Z,Z,Z,Z 2,3,0,1,Z,Z,Z,Z 3,0,1,2,Z,Z,Z,Z 4,5,6,7,Z,Z,Z,Z 5,6,7,4,Z,Z,Z,Z 6,7,4,5,Z,Z,Z,Z 7,4,5,6,Z,Z,Z,Z 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,2.3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 0,1,2,3,4,5,6,7 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

0 V V

1 V V

Z = Data and Strobe output drivers in tri-state.2. X=”Don’t Care”3. NOTES: Internal READ and WRITE operations start at the same point in time for 1. BC4 as they do for BL8. DLL RESET is defined by MR0[8] (see Figure 44). Programming MR0[8] to “1” activates the DLL RESET function. MR0[8] is self-clearing, mean- ing it returns to a value of “0” after the DLL RESET function has been initiated. Anytime the DLL RESET function has been initiated, CKE must be HIGH and the clock held stable for 512 ( tDLLK) clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications such as tDQSCK timings. DLL RESET WRITE RECOVERY time is defined by MR0[11:9] (see Figure 44). WRITE RECOVERY values of 5,6,7,8,10 or 12 may be used by programming MR0[11:9]. The user is required to program the correct value of WRITE RECOVERY and is calculated by dividing tWR (ns) by tCK (ns) and round- ing up a non-integer value to the next integer: WR (cycles)=roundup tWR[ns]/tCK [ns]). WRITE RECOVERY

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product The PRECHARGE PD bit applies only when PRECHARGE power-down mode is being used. When MR0[12] is set to “0”, the DLL is off during PRECHARGE power-down providing a lower standby current mode; how- ever, tXPDLL must be satis fied when exiting. When MR0[12] is set to “1”, the DLL continues to run during PRECHARGE power-down mode to enable a faster exit of PRECHARGE power-down mode; however, tXP must be satisfied when exiting (see Power-Down mode on Page 133). PRECHARGE POWER-DOWN (PRECHARGE PD) The CL is defined by MR0[6:4], as shown in Figure 44. CAS latency is the delay, as measured in clock cycles, between the internal READ command and the availability of the first bit of valid output data. The CL can be set to 5,6, 8, or 10. DDR3 SDRAM iMODs do not support half-clock latencies. Examples of CL=6 and CL=8 are shown in Figure 45 (below). If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n+m. Table 49 indicates the CLs supported at available operating frequencies. CAS Latency (CL) FIGURE 45- READ LATENCY READ NOP NOP NOP NOP NOP NOPNOP CK CK# Command DQ DQS, DQS# DQS, DQS# T0 T1 T2 T3 T4 T5 T6 T7 T8 Don’t Care CK CK# Command DQ READ NOP NOP NOP NOP NOP NOPNOP T0 T1 T2 T3 T4 T5 T6 T7 T8 DI n + 3 DI n+ 1 DI n + 2 DI n + 4 DI n DI n NOP NOP AL = 0, CL = 8 AL = 0, CL = 6 Transitioning Data NOTES: For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are 1. possible. Shown with nominal 2. tDQSCK and nominal tDSDQ.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product The MODE REGISTER 1 (MR1) controls additional functions and features not available in the other mode registers; Q OFF (OUTPUT D ISABLE), DLL ENABLE/DLL DISABLE, RTT_NOM value (ODT), WRITE LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 46 below. The MR1 register is programmed via the MR5 command and retains the store d information until it is reprogrammed, until RESET\\ goes LOW (true), or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided the operation is performed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. The controller must satisfy the specified timing parameters tMRD and tMOD before initiating a subsequent operation. MODE REGISTER 1 (MR1) FIGURE 46- MODE REGISTER 1 (MR1) DEFINITION AL R TTQ Off A9 A7 A6 A5 A4 A3 2A 8AA 1 A0 Mode register 1 (MR1) Address bus 9 7 6 5 4 3 2 81 0 A10 A12 A11 1AB 0AB 31 21 11 01 DLL Enable Enable (normal) Disable Output Drive Strength RZQ/6 (40Ω [NOM]) RZQ/7 (34Ω [NOM]) Reserved Reserved WL

1 SDO 0 DLL RTTTDQS

Disable (normal) Enable Additive Latency (AL) Disabled (AL = 0) AL = CL - 1 AL = CL - 2 Reserved RTT ODS A13 M11 TDQS Disabled Enabled 01 01 RTT_NOM (ODT)2 Non-Writes RTT_NOM disabled RZQ/4 (60Ω [NOM]) RZQ/2 (120Ω [NOM]) RZQ/6 (40Ω [NOM]) RZQ/12 (20Ω [NOM]) RZQ/8 (30Ω [NOM]) Reserved Reserved R TT_NOM (ODT)3 Writes RTT_NOM disabled RZQ/4 (60Ω [NOM]) RZQ/2 (120Ω [NOM]) RZQ/6 (40Ω [NOM]) n/a n/a Reserved Reserved Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) M14 M15 NOTES: MR1[16, 13, 10, 8] are reserved for future use and must be programmed to “0.”1. During write leveling, if MR1[7] and MR1[12] are “1” then all R2. TT_NOM values are available for use. During write leveling, if MR1[7] is a “1,” but MR1[12] is a “0,” then only R3. TT_NOM write values are available for use.

using the appropriate LOAD MODE command. ODT is NOT ALLOWED to be used1. The OUTPUT DATA is no longer edge-aligned to the clock2. CL and CWL can only be six clocks3. ABLING the DLL also implies the need to change the clock frequency. (ODTLoff), assuming ODT has been ENABLED via MR1[9,6,2]. The DDR3 SDRAM iMOD uses a programmable impedance output buffer. (34Ω [NOM]) is the primary output driver impedance setting for the device. ings and current specifications are met during an update. that is part of the initialization and reset procedure. Figure 46. When enabled (MR1[12]=0), all outputs (DQx, DQSx, DQSx\\) topology for the commands, addresses, control signals and clocks. information is provided in “WRITE LEVELING.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product AL is supported to make the command and data bus ef ficient for sustainable bandwidths in DDR3 SRAMs. MR1[4,3] de fine the value of AL (see Figure 46). MR1[4,3] enables the user to program the DDR3 SDRAM with an AL=0, CL-1, or CL-2. With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to tRCD(MIN). The only restriction is ACTIVATE to READ or WRITE + AL ≥ tRCD(MIN) must be satisfied. Assuming tRCD(MIN) = CL, a typical application using this feature, sets AL=CL – 1tCK = tRCD(MIN-1tCK. The READ or WRITE command is held for the time of the AL before it is released internally to the DDR3 SDRAM iMOD device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL=AL+CL, WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL=AL + CWL (see “MODE REGISTER 2 (MR2))”. Examples of READ and WRITE latencies are shown in Figure 47 and Figure 49. POSTED CAS ADDITIVE LATENCY (AL) FIGURE 47- READ LATENCY (AL = 5, CL = 6) CK CK# Command DQ DQS, DQS# ACTIVE n T0 T1 Don’t Care NOP NOP T6 T12 NOPREAD n T13 NOP DO n+ 3 DO n + 2 DO n + 1 RL = AL + CL = 11 T14 NOP DO n tRCD (MIN) AL = 5 CL = 6 T11 BC4 Indicates a Break in Time Scale Transitioning Data NOP

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 48- MODE REGISTER 2 (MR2) DEFINITION Notes: 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.” M14 M15 Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) A9 A7 A 6 A5 A4 A3A8 A2 A1 A0 Mode Register 2 (MR2) Address bus 97 6 5 4 382 1 0 A10A12 ))* )* +3/ 2243 "=, &= ,# "=, (&= ,# ,*35: 8<",50# &,/" ,/>& ,/"& ,/> '& ',/" '& ,/>& ,/"& ,/>& -<:8 1-4 4475 4475 62$% 62$ The MODE REGISTER 2 (MR2) controls additional functions and features not available in the other mode registers. These addition al functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT) and DYNAMIC ODT (R TT_WR). These functions are con- trolled via the bits shown in Figure 48. The MR2 is programmed via the MRS command and will retain the stored information unti l it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided that the operation has been performed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress and the memory controlle r must wait for the specified time tMRD and tMOD before initiating a subsequent operation. MODE REGISTER 2 (MR2)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 49- CAS WRITE LATENCY CK CK# Command DQ DQS, DQS# ACTIVE n BC4 T0 T1 Don’t Care NOP NOP T6 T12 NOPWRITE n T13 NOP DI n + 3 DI n + 2 DI n + 1 T14 NOP DI n tRCD (MIN) NOP AL = 5 T11 Indicates A Break in Time Scale WL = AL + CWL = 11 Transitioning Data CWL = 6 CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal WRITE to the latching of the first data in. CWL must be correctly set to the corresponding operating clock frequency (see Figure 48). The overall WRITE LATENCY (WL) is equal to CWL + AL (see Figure 46). CAS WRITE LATENCY (CWL) Mode register MR2[6] is used to DISABLE/ENABLE the ASR function. When ASR is DISABLED, the SELF REFRESH mode’s REFRESH rate is assumed to be at the normal 85 ˚C limit (commonly referred to as the 1X REFRESH rate). In the DISABLED mode, ASR requires the user to ensure the SDRAM never exceeds a Tc of 85˚C while in SELF REFRESH unless the user enables the SRT feature listed below, supporting an ele- vated temp up to +95˚C while in SELF REFRESH. The standard SELF REFRESH current test speci fies test conditions to normal case temperature (85 ˚C) only, meaning if ASR is enabled, the standard SELF REFRESH current speci fication does not apply (see the “EXTENDED TEMPERATURE USAGE” description later in this DS). AUTO SELF REFRESH (ASR) optional extended temperature range of +95 ˚C while in SELF REFRESH mode. The standard SELF REFRESH current test specifies test conditions to normal case temperature (85 ˚C) only, meaning if SRT is enabled, the standard SELF REFRESH current specifications do not apply. SRT vs. ASR Mode register MR2[7] is used to DISABLE/ENABLE the SRT function. When SRT is Disabled, the SELF REFRESH mode’s refresh rate is assumed to be at the normal 85 ˚C limit. In the DISABLED mode, SRT requires the user to ensure the SDRAM never exceeds the Tc limit of 85˚C while in SELF REFRESH mode unless the user enables ASR. When SRT is enabled, the SDRAM SELF REFRESH is changed internally from 1X to 2X, regardless of the case temperature (Tc). This enables the user to operate the SDRAM beyond the standard 85 ˚C limit up to the SELF REFRESH TEMPERATURE (SRT) If the normal case temperature limit of 85 ˚C is not exceeded, then neither SRT nor ASR is required, and both can be DISABLED throughout opera- tion. If the extended temperature option is used, the user is required to pro- vide a 2X refresh rate during (manual) refresh for Extended temp devices or 3X refresh rate for Mil-temp devices. SRT and ASR should be enabled for automatic REFRESH services on all devices used in temperature envi- ronments ≤95˚C SRT forces the SDRAM to switch the internal SELF REFRESH rate from 1X to 2X. SELF REFRESH is performed at 2X regardless of Tc. ASR automatically switches the SDRAM’s internal SELF REFRESH rate from 1X to 2X, however, while in SELF REFRESH mode, ASR enables the REFRESH rate automatically adjust between 1X and 2X REFRESH rate over the supported temperature range. One other disadvantage with ASR is the SDRAM cannot always switch from a 1X to a 2X refresh rate at an exact case Temperature of 85 ˚C. Although the SDRAM will support data integrity when it switches from a 1X to 2X rate, it may switch at a lower temperature than 85˚C. Since only one mode is necessary at one instant in time, SRT and ASR cannot be simultaneously enabled.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product DYNAMIC ODT The mode register 3 (MR3) controls additional functions and features not available via MR0, MR1 or MR2. Currently defined as the MULTIPURPOSE REGIS- TER (MPR). This function is controlled via the bits shown in Figure 50. The MR3 is programmed via the LOAD MODE command and retains the stored infor- mation until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided the programming of the MR3 has been performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress and the memory controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. MODE REGISTER (MR3) The dynamic ODT (RTT_WR) feature is defined by MR2[10,9]. Dynamic ODT is enabled when a value is selected. This new DDR3 feature enables the ODT termination value to change without issuing an MRS command, essentially changing the ODT termination “on-the-fly”. With dynamic ODT (R TT_WR) when beginning a WRITE burst and subsequently switches back to ODT (R TT_WR) is enabled: ODTLCNW, ODTLCNW4, ODTLCNW* ODTH4, ODTH8 and tADC. Dynamic ODT is only applicable during WRITE cycles, If ODT (RTT_NOM) is disabled, dynamic ODT (RTT_WR) is still permitted. RTT_NOM and RTT_WR can be used independent of one another. Dynamic ODT is not available during WRITE LEVELING mode, regardless of the state of ODT (RTT_NOM). For details on ODT operation, refer to the “On-Die-Termination (ODT)” section. FIGURE 50 - MODE REGISTER 3 (MR3) DEFINITION A9 A7 A 6 A5 A4 A3A8 A2 A1 A0 Mode register 3 (MR3) Address bus 97 6 5 4 382 1 0 A10A12 A111AB0 AB 1011 12131415 A13 10 1 01 01 01 01 01 01 MPR 1 BA2 01 01 01 01 01 MPR Enable Normal DRAM operations 2 Dataflow from MPR MPR_RF M14 M15 Mode Register Mo de register set (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) MPR READ Function Predefined pattern 3 Reserved Reserved Reserved NOTES: MR3[16 and 13:4] are reserved for future use and must all be programmed to “0.”1. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.2. Intended to be used for READ synchronization.3.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product MULTIPURPOSE REGISTER (MPR) The MULTIPURPOSE REGISTER function is used to output a predefined system timing calibration bit sequence. Bit 2 is the master bit that enables or disables access to the MPR register and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose r egister is shown in Figure 51. If MR3[2] is a “0”, then the MPR access is disabled and the SDRAM operates in normal mode. However, if MR3[2] is a “1”, then SDRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0,1]. If MR3[0,1] is equal to “00”, then a predefined read pattern for system calibration is selected. To enable the MPR, the MRS command is issued to MR3 and MR3[2]=1 (see Table 66). Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged, and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when either a READ or a RDAP command is issued is de fined by MR3[1:0]when MPR is enabled (see Table 67). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2]=0). POWER-DOWN, SELF REFRESH and any other NON READ or RDAP command is not allowed. The RESET function is supported during MPR enable mode. FIGURE 51 - MULTIPURPOSE REGISTER (MPR) BLOCK DIAGRAM Memory core MR3[2] = 0 (MPR off) DQ, DM, DQS , DQS # Multipurpose register predefined data for READs MR3[2] = 1 (MPR on) NOTES: A predefined data pattern can be read out of the MPR with an external READ command.1. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the data 2. flow is de fined, the MPR contents can be read out continuously with a regular READ or RDAP command.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product MPR MPR READ Function Function Normal Operation, no MPR transaction. All subsequent READs come from the SDRAM memory array. All subsequent WRITEs go to the SDRAM memory array. Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2. TABLE 66: BURST ORDER “Don’t Care” A[1:0] (See Table 66) MR3[2] MR3[1:0] MPR FUNCTIONAL DESCRIPTION The MPR JEDEC definition allows for either a prime DQ0 for lower byte and DQ8 for the upper byte of each of the (4) words contained in the LDI iMOD, to output the MPR data with the remaining DQs driven LOW, or for all DQs to output the MPR data. The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable. This providing the DLL is locked as required. MPR addressing for a valid MPR READ is as follows: A[1:0] must be set to “00” as the burst order is fixed per nibble• A2 selects the burst order• BL8, A2 is set to “0”, and the burst order is fixed to 0,1,2,3,4,5,6,7• For burst chop 4 cases, the burst order is switched on the nibble base and:• A2=0: burst order =0,1,2,3 • A2=1: burst order =4,5,6,7• Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is assigned to MSB• A[9:3] are a “Don’t Care” • A10 is a “Don’t Care”• A11 is a “Don’t Care” • A12: Selects burst chop mode on-the-fly, if enabled within MR0• A13 is a “Don’t Care”• BA[2:0] are a “Don’t Care”•

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product MPR REGISTER ADDRESS DEFINITIONS and BURSTING ORDER The MPR currently supports a single data format. This data format is a prede fined READ pattern for system calibration. The prede fined pattern is always a repeating 0-1 bit pattern. Examples of the different type of predefined READ pattern bursts are shown in Figures 52, 53, and 54. MR3[2] MR3[1:0] Function Length A[2:0] Burst Order and Data Pattern Burst Order: 0,1,2,3,4,5,6,7 Predefined pattern: 0,1,0,1,0,1,0,1 Burst Order: 0,1,2,3 Predefined pattern: 0,1,0,1 Burst Order: 4,5,6,7 Predefined pattern: 0,1,0,1 n/a n/a n/a n/a n/a n/a n/a n/a n/a TABLE 67: BURST ORDER READ predefined pattern for system calibration RFU RFU RFU BL8 BC4 BC4 n/a n/a n/a n/a n/a n/a n/a n/a n/a 000 000 100 n/a n/a n/a n/a n/a n/a n/a n/a n/a Burst Read

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. T0 Ta0 Tb0Tb1Tc0Tc1Tc2Tc3 Tc4 Tc5Tc6 Tc7Tc8Tc9Tc10 CK CK# MRS PREAREAD1NOP NOP NOP NOP NOP NOP NOP NOP MRS NOP NOP Valid Command tMPRR Don’t Care Indicates a Break in Time Scale DQS , DQS# Bank address3 Valid3

0 A[1:0]Valid 02

1 A2020

00 A[9:3]Valid00

0 A12/BC#Valid10

0il aV ] 31: 51[ Ad0 DQ tMOD tRPtMOD RL Figure 52 - MPR System Read Calibration with BL8: Fixed Burst Order Single Readout

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 100 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. T0 Ta T bTc0Tc1Tc2Tc3Tc4 Tc5 Tc6Tc7 Tc8Tc9Tc10Td CK CK# tMPRR Don’t Care Indicates a Break in Time Scale RL

3 Valid3 Bank addressValid

A[1:0]Valid 02 02 0 A212 02 10

0 A[15:13]Valid Valid0

A[9:3]Valid Valid00 00 A11Valid Valid0 0 A12/BC#Valid10 0 A10/APValid Valid0 0 1 RL PREAREAD1NOP NOP NOP NO NOP NOP NOP MRS Valid CommandREAD1 MRS DQ Valid DQS , DQS# tRPtMODtCC DtMOD NOPNOP Figure 53 - MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 101 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. READ with BC4 either by MRS or OTF. 2. Memory controller must drive 0 on A[1:0]. T0 Ta Tb CK CK# DQ DQS , DQS# tMOD tMPRR Don’t Care Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 Td NOP NOP NOP NOP Valid Command MRSPREAREAD1READ1NOP NOP Indicates a Break in Time Scale Bank address3 Valid3 Valid

0 A[1:0]Valid 02 02

1 A214 030

00 il aV ] 3: 9[ Ad Valid00 0 1il aV PA/ 01 Ad Valid0 0il aV 11 Ad Valid0

0 A12/BC#Valid1Valid10

Figure 54 - MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 102 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. READ with BC4 either by MRS or OTF. 2. Memory controller must drive 0 on A[1:0]. T0 Ta T b 0 1il aV PA/ 01 AdV a l i d0 CK CK# MRS PREAREAD1READ1NOP NOP NOP S NOP NOP Valid Command 0 04 13 1 A2 tMOD tMPRR 3V a l i d3 Bank addressValid 02 02 0 A[1:0]Valid 0 0il aV ] 31: 51[ AdV a l i d 0 0il aV 11 Ad Valid 00 00 il aV ] 3: 9[ AdV a l i d Don’t Care Tc 0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 Td Indicates a Break in Time Scale RL DQ DQS , DQS# Figure 55 - MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 103 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product MPR READ PREDEFINED PATTERN The predetermined READ calibration pattern is a fixed pattern of 0,1,0,1,0,1,0,1. The following is an example of using the READ out predetermined READ calibration pattern. The example is to perform multiple READS from the MULTIPURPOSE REGISTER (MPR) in order to do system level READ timing calibra- tion based on the predetermined and standardized pattern. The following protocol outlines the steps used to perform the READ calibration: Precharge all banks• After • tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0]=00. This redirects all subsequent READs and Loads the predefined pattern into the MPR. As soon as tMRD and tMOD are satisfied, the MPR is available. Data WRITE operations are not allowed until the MPR returns to the normal SDRAM state• Issue a READ with burst order information (all other address pins are “Don’t Care”):• A[1:0] = 00 (data burst order is fixed starting at nibble)• A2 = 0 (for BL8, burst order is fixed as 0,1,2,3,4,5,6,7)• A12 = 1 (use BL8)• After RL = AL + CL, the SDRAM bursts out the predefined READ calibration pattern (0,1,0,1,0,1,0,1) • The memory controller repeats the calibration READs until READ data capture at the memory controller is optimized• After the last MPR READ burst and after • tMPRR has been satisfied, issue MRS, MR3[2] = 0 and MR3[1:0] = “Don’t Care” to the normal SDRAM state. All subsequent READ and WRITE accesses will be regular READS and WRITES from/to the SDRAM array When • tMRD and tMOD are satisfied from the last MRS, the regular SDRAM commands (such as ACTIVATE a Memory bank for regular READ or WRITE access) are permitted MODE REGISTER SET (MRS) The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determines which mode register is programmed: BA2 = 0, BA1 = 0, BA0 = 0 for MR0 • BA2 = 0, BA1 = 0, BA0 = 1 for MR1 • BA2 = 0, BA1 = 1, BA0 = 0 for MR2 • BA2 = 0, BA1 = 1, BA0 = 1 for MR3 • The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state ( tRP is satisfied and no data bursts are in progress). The controller must wait the specified time tMRD before initiating a subsequent operation such as an ACTIVATE command. There is also a restriction after issuing an MRS command with regard to when the updated functions become available. This parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Figure 42 and 43. Violating either of these requirements will result in unspecified operation. ZQ CALIBRATION The ZQ CALIBRATION command is used to calibrate the SDRAM output drivers (RON) and ODT values (R TT) over process, voltage, and temperature, pro- vided a dedicated 240Ω (±1%) external resistor is connected from the SDRAM’s ZQ ball to VssQ. DDR3 SDRAMs need a longer time to calibrate RON and ODT at power up INITIALIZATION and SELF REFRESH exit and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and ZQ CALIBRATION SHORT (ZQCS). An example of ZQ CALIBRATION timing is shown in Figure 56. All banks must be PRECHARGED and tRP must be met before ZQCL or ZQCS commands can be issued to the SDRAM. No other activities (other than another ZQCL or ZQCS command may be issued to the SDRAM) can be performed on the SDRAM array by the controller for the duration of tZQINIT or tZQOPER. The quiet time on the SDRAM array helps accurately calibrate RON and ODT. After SDRAM calibration is achieved, the SDRAM should disable the ZQ ball’s current consumption path to reduce overall power usage. ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time. Upon SELF REFRESH exit, an explicit ZQCL is required if ZQ CALI- BRATION is desired. In dual rank system designs that share the ZQ resistor between devices, the controller must not allow overlap of tZQINT, tZQOPER or tZQCS between ranks.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 104 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 56 - ZQ CALIBRATION TIMING (ZQCL AND ZQCS) NOPZQCL NOP NOP Valid Valid ZQCS NOP NOP NOP ValidCommand Indicates a Break in Time Scale T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 Address Valid Valid Valid A10 Valid Valid Valid CK CK# Don’t Care DQ High-Z High-Z 3A3 ctivities Activ- ities Valid ValidODT 2 2 Valid 1CKE 1 Valid Valid Valid tZQCStZQINIT or tZQOPER NOTES: CKE must be continuously registered HIGH during the calibration procedure.1. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.2. All devices connected to the DQ bus should be High-Z during calibration.3. ACTIVATE Before any READ or WRITE commands can be issued to a bank within the SDRAM, a ROW in that bank must be opened (ACTIVATED). This is accomplished via the ACTIVATE command, which selects both the BANK and the ROW to be ACTIVATED. After a ROW is opened with an ACTIVATE command, a READ or WRITE command may be issued to that ROW, subject to the tRCD specification. However, if the additive latency is programmed correctly, a READ or WRITE command may be issued prior to tRCD (MIN). In this operation, the SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank, but prior to tRCD (MIN) (see “POSTED CAS ADDITIVE LATENCY (AL)). tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVATE command on which the READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. When at least one bank is open, any READ-to-READ command delay or WRITE-to-WRITE command delay is restricted to tCCD (MIN). A subsequent ACTIVATE command to a different ROW in the same BANK can only be issued after the previous ACTIVE ROW has been clo sed (PRE- CHARGED). The minimum time interval between successive ACTIVATE commands to the same BANK is defined by tRC. A subsequent ACTIVATE command to another BANK can be issued while the first BANK is being accessed, which results in a reduction of total ROW-ACCESS overhead. The minimum time interval between successive ACTIVATE commands may be issued in a given tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies, regardless of the number of BANKS already opened or closed.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 105 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 57 - EXAMPLE: MEETING tRRD (MIN) AND tRCD (MIN) Command Don’t Care T1T0 T2 T3 T4 T5 T8 T9 tRRD Row Row Col Bank x Bank y Bank y NOPACT NOP NOPACT NOP NOP RD/WR tRCD BA[2:0] CK# Address CK T10 T11 NOP NOP Indicates a Break in Time Scale FIGURE 58 - EXAMPLE: tFAW Command Don’t Care T1T0 T4 T5 T8 T9 T10 T11 tRRD Row Row Bank a Bank b Row Bank c Row Bank d Bank y Row Bank y NOPAC T NOPAC ATC T N O P NOP tFAW BA[2:0] CK# Address CK T19 T20 NOPAC ATC T Bank e Indicates a Break in Time Scale

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 106 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 59 - READ LATENCY Notes: 1. DO n = data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO n.. CK CK# Command READ NOP NOP NOP NOP NOP NOP NOP Address Bank a, Col n CL = 8, AL = 0 DQ DQS , DQS # DO n T0 T7 T8 T9 T10 T11 Don’t CareTransitioning Data T12 T12 Indicates a Break in Time Scale READ READ bursts are initiated with a READ command. The starting COLUMN and BANK addresses are provided with the READ command and A UTO PRE- CHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the ROW being accessed is automatically PRECHARGED at the completion of the burst sequence. If AUTO PRECHARGE is disabled, the ROW will be left open after the completion of the burst. During READ bursts, the valid data out element from the starting column address is available at READ LATENCY (RL) clocks later. RL is defined as the sum of POSTED CAS ADDITIVE LATENCY (AL) and CAS LATENCY (CL) (RL = AL + CL). The value of AL and CL is programmable in the mode re gister via the MRS command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK\\). Figure 59 shows an example of RL based on a CL setting of 8 as well as AL=0. A READ burst may be followed by a PRECHARGE command to the same bank provided AUTO PRECHARGE is not ACTIVATED. The minimum READ-to-PRECHARGE command spacing to the same bank is four clocks and must also satisfy a minimum analog time from the READ command. This time is called tRTP (READ-to-PRECHARGE). tRTP starts AL cycles later than the READ command. Examples for BL8 are shown in Figure 65 and BC4 in Figure 66. Following the PRECHARGE command, a subse- quent command to the same bank cannot be issued until tRP is met. The PRECHARGE command followed by another PRECHARGE command to the same bank is allowed. However, the precharge period will be deter- mined by the last PRECHARGE command issued to the bank. If A10 is HIGH when a READ command is issued, the READ with AUTO PRECHARGE function is engaged. The SDRAM starts an AUTO PRE- CHARGE operation on the rising edge which is AL + tRTP cycles after the READ command. DDR3 SDRAMs support a tRAS lockout feature (see Figure 68). If tRAS (MIN) is not satis fied at the edge, the starting point of the AUTO PRECHARGE operation will be delayed until tRAS (MIN) is sat- isfied. In case the internal PRECHARGE operation is pushed out by tRTP, tRP starts at the point at which the internal PRECHARGE happens. The time from READ with AUTO PRECHARGE to the next ACTIVATE com- mand the same bank is AL + ( tRTP + tRP)*, where “*” means rounded up to the next integer. In any event, internal RECHARGE does not start earlier than four clocks after the last 8n-bit prefetch. L[U]DQSx, L[U]DQSx\\ is driven by the SDRAM along with the output data. The initial LOW state on L[U]DQSx and HIGH state on L[U]DQSx\\, is known as the READ preamble ( tRPRE). The LOW state on DQSx and the HIGH state on L[U]DQSx\\, coincident with the last data-out element, is known as the READ postamble ( tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go HIGH-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), and the valid data window are depicted in Figure 71. A detailed explanation of tDQSCK (DQS transition skew to CK) is also depicted in Figure 71. Data from any READ burst may be concatenated with data from a subse- quent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 60. If BC4 is enabled, tCCD must still be met which will cause a gap in the data output, as shown in Figure 61. Nonconsecutive READ data is reflected in Figure 62. DDR3 SDRAMs do not allow interrupting or truncating any READ burst. Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 63. To ensure the READ data is completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing is RL + tCCD – WL + 2tCK.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 107 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0 and T4. 3. DO n (or b) = data-out from column n (or column b). 4. BL8, RL = 5 (CL = 5, AL = 0). T0 T1 T2T3 T4T5T6T7 T8 T9T10 T11 Don’t Care Transitioning Data T12 T13 T14 tRPS T NOP DAER DAERPON PON PON PON PON PON PON PON PON PON PON PON CK CK# Command1 DQ3 DQS , DQS# Bank, Col n Bank, Col b Address2 RL = 5 tRPRE tCCD RL = 5 DO n+ 3 DO n+ 2 DO n + 1 DO nDO n+ 7 DO n + 6 DO n + 5 DO n+ 4DO b + 3 DO b + 2 DO b+ 1 DO bDO b + 7 DO b + 6 DO b + 5 DOb+ 4 Figure 60 - Consecutive READ Bursts (BL8)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 108 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0 and T4. 3. DO n (or b) = data-out from column n (or column b). 4. BC4, RL = 5 (CL = 5, AL = 0). NOP CK CK# Comman d1 DQ3 DQS , DQS # T0 T1 T2 T3 T4 T5T6T7 T8 T9 Address2 T10 T11 Don’t Care Transitioning Data T12 T13 T14 READREAD NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Bank, Col n Bank, Col b tRPST tRPREtRPSTtRPRE RL = 5 DO n+ 3 DO n + 2 DO n + 1 DO n DO b+ 3 DO b+ 2 DO b+ 1 DO b RL = 5 tCCD Figure 61 - Consecutive READ Bursts (BC4)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 109 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. AL = 0, RL = 8. 2. DO n (or b) = data-out from column n (or column b). 3. Seven subse quent elements of data-out appear in the programmed order following DO n. 4. Seven subse quent elements of data-out appear in the programmed order following DO b. Don’t Care Transitioning Data T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 DQS , DQS # CommandNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOP NOP READNOP READ AddressBank a, Col n Bank a, Col b CK CK# DQDOnDOb CL = 8 CL = 8 Figure 62 - Nonconsecutive READ Bursts

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 110 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. Don’t Care Transitioning Data T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK CK# Command1NOP NOP NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP tWPS T tRPREtWPRE tRP S T DQS , DQS# DQ3 WL = 5 tWR tWTR READ DO nDO n + 1DO n + 2DO n + 3DO n + 4DO n + 5DO n + 6DO n + 7DI nDI n + 1DI n + 2DI n + 3DI n + 4DI n + 5DI n + 6DI n + 7 READ-to-WRITE command delay = RL + tCCD + 2tCK - WLtBL = 4 clocks Address2Bank,Col b Bank,Col n RL = 5 Figure 63 - READ (BL8) to WRITE (BL8)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 111 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4. 3. DO n = data-out from column n; DI n = data-in from column b. 4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5). Don’t Care Transitioning Data T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK CK# Address2Bank,Col nBank,Col b Command1READ NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tWPS T tWPRE tRPS T DQS , DQS# DQ3 WL = 5 READ-to-WRITE command delay = RL + tCCD/2 + 2tCK - WL tWR tWTR tBL = 4 clocks tRPRE RL = 5 DO nDO n+ 1DO n+ 2DO n + 3DI nDI n + 1DI n + 2DI n+ 3 Figure 64 - READ (BC4) to WRITE (BC4) OTF

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 112 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. 3. DO n = data-out from column, DI b = data-in for column b. 4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). Don’t Care Transitioning Data T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK CK# Command1NOP NOP NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP tWPS T tRPREtWPRE tRP S T DQS , DQS# DQ3 WL = 5 tWR tWTR READ DO nDO n + 1DO n + 2DO n + 3DO n + 4DO n + 5DO n + 6DO n + 7DI nDI n + 1DI n + 2DI n + 3DI n + 4DI n + 5DI n + 6DI n + 7 READ-to-WRITE command delay = RL + tCCD + 2tCK - WLtBL = 4 clocks Address2Bank,Col b Bank,Col n RL = 5 Figure 65 - READ to PRECHARGE (BL8)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 113 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product CK CK# Don’t Care Transitioning Data T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 CommandNOP NOP NOP NOP NOP NOP NOP NOP NOP ACT NOP NOPNOP NOP NOP READ NOP PRE AddressBank a, Col n Bank a, (or all) Bank a, Row b tRP tRTP DQS , DQS# DQDO n DO n+ 1 DO n+ 2 DO n+ 3 tRAS Figure 66 - READ to PRECHARGE (BC4)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 114 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product CK CK# Command DQ DQS, DQS# ACTIVE n T0 T1 Don’t Care NOPNOP T6T12 NOP READ n T13 NOP DO n+ 3 DO n + 2 DO n + 1 RL = AL + CL = 11 T14 NOP DO n tRCD (MIN) AL = 5CL = 6 T11 BC4 Indicates a Break in Time Scale Transitioning Data NOP Figure 67 - READ to PRECHARGE (AL = 5, CL = 6)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 115 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product CK CK# Command NOP NOP NOP NOP Address DQ DQS , DQS# Don’t Care Transitioning Data NOP NOP NOP NOP NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Ta0 tRTP (MIN) NOP READNOP AL = 4 NOPNOP CL = 6 NOP tRAS (MIN) AC T Indicates A Break in Time Scale tRP Bank a,Col nBank a,Row b DOnDOn+ 1DOn+ 2DOn+ 3 Figure 68 - READ with Auto Precharge (AL = 4, CL = 6)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 116 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product A DQSx to DQ output timing is shown in Figure 69. The DQ transitions between valid data outputs must be within tDQSQ of the crossing point of L[U]DQSx, L[U]DQSx\\. DQS must also maintain a minimum HIGH and LOW time of tQSH and tQSL. Prior to the READ preamble, the DQ balls will either be floating or terminated depending on the status of the ODT signal. Figure 70 shows the strobe-to-clock timing during a READ. The crossing point DQSx, DQSx\\ must transition with ± tDQSCK of the clock crossing point. The data out has no timing relationship to clock, only to DQS, as shown in Figure 70. Figure 70 also shows the READ preamble and postamble. Normally, both DQSx and DQSx\\ are HIGH-Z to save power (VccQ). Prior to data output from the SDRAM, DQSx is driven LOW and DQSx\\ driven HIGH for tRPRE. This is known as the READ preamble. The READ postamble, tRPST, is one half clock from the last L[U]DQSx, L[U]DQSx\\ transition. During the READ postamble, L[U]DQSx is driven LOW and L[U] DQSx\\ driven HIGH. When complete, the DQ will either be disabled or will continue terminating depending on the state of the OD T signal. Figure 75 demon- strates how to measure tRPST. READ

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 117 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. 3. DO n = data-out from column n. 4. BL8, RL = 5 (AL = 0, CL = 5). 5. Output timings are referenced to VCCQ/2 and DLL on and locked. 6.tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock. 7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. T0 T1 T2T3 T4T5T6T7 T8 T9T10 Bank,Col n tRPST NOP READNOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 Address 2 tDQSQ (MAX) DQS , DQS# DQ3 (last data valid) DQ3 (first data no lon ger valid) All DQ collectively DOnDOn+ 3 DOn + 2 DOn+ 1DOn+ 7 DOn+ 6 DOn+ 5 DOn+ 4 DOn + 2 DOn+ 1DOn+ 7 DOn + 6 DOn+ 5 DOn+ 4 DO n+ 3 DO n+ 2 DO n+ 1 DO n DO n+ 7 DO n+ 6 DO n+ 5 DO nDOn + 3 tRPRE Don’t Care Transitioning Data Data valid Data valid tQH tQH tHZ (DQ) MAX DO n+ 4 RL = AL + CL tDQSQ (MAX) tLZ (DQ) MIN Figure 69 - Data Output Timing – tDQSQ and Data Valid Window

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 118 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a speci fic voltage level which speci fies when the device output is no longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS). tLZ (DQ), Figure 71 shows a method to calculate the point when the device is not longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS), tLZ (DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ (DQS), tLZ (DQ), tHZ (DQS) and tHZ (DQ) are defined as single-ended. OUTPUT TIMING

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 119 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product RL measured to this point DQS, DQS# early strobe CK tDQSCK (MIN) tLZ (DQS) MIN tHZ (DQS) MIN DQS, DQS# late strobe tDQSCK (MAX) tLZ (DQS) MAX tHZ (DQS) MAX tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MIN) CK# tRPRE tQSHtQSLtQSL tQSLtQSL tQSH tQSHtQSH Bit 0 Bit 1 Bit 2 Bit 7 tRPRE Bit 0 Bit 1 Bit 2 Bit 7Bit 6 Bit 3 Bit 4 Bit 5 Bit 6 Bit 4 Bit 3 Bit 5 tRPST tRPST T0 T1 T2 T3 T4 T5 T6 Figure 70 - Data Strobe Timing – READs

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 120 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Notes: 1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK (MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK (MAX). 2. The DQS high pulse width is defined by tQSH, and the DQS low pulse width is defined by tQSL. Likewise, tLZ (DQS) MIN and tHZ (DQS) MIN are not tied to tDQSCK (MIN) (early strobe case) and tLZ (DQS) MAX and tHZ (DQS) MAX are not tied to tDQSCK (MAX) (late strobe case); however, they tend to track one another. 3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The minimum pulse width of the READ postamble is defined by tRPST (MIN). tHZ (DQS), tHZ (DQ) tHZ (DQS), tHZ (DQ) end point = 2 × T1 - T2 VOH - xmV VTT - xmV VOL + xmV VTT + xmVVOH - 2xmV VTT - 2xmV VOL + 2xmV VTT + 2xmV tLZ (DQS), tLZ (DQ) tLZ (DQS), tLZ (DQ) begin point = 2 × T1 - T2 T1T2 Figure 71 - Method for Calculating tLZ and tHZ

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 121 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 72 - tRPRE TIMING tRPRE DQS - DQS# DQS DQS # tRPRE begins tRPRE ends CK CK# VTT Resulting differential signal relevant for tRPRE specification tC tA tB tD VTT VTT Single-ended signal, provided as background information Single-ended signal, provided as background information FIGURE 73 - tRPST TIMING tRPST DQS - DQS # DQS DQS # tRP ST begins T2 tRPST ends Resulting differential signal relevant for tRPS T specification CK CK# VTT tC tA tB tD Single-ended signal, provided as background information VTT VTT Single-ended signal, provided as background information

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 122 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 74 - tWPRE TIMING DQS - DQS# tWPRE begins tWPRE ends tWPRE Resulting differential signal relevant for tWPRE specification CK CK# VTT FIGURE 75 - tWPST TIMING tWPST DQS - DQS # tWPST begins tWPST ends Resulting differential signal relevant for tWPST specification CK CK# VTT

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 123 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product WRITE WRITE bursts are initiated with a WRITE command. The starting COLUMN and BANK addresses are provided with the WRITE command, a nd AUTO PRE- CHARGE is selected, the ROW being accessed will be PRECHARGED at the end of WRITE burst. If AUTO PRECHARGE is not selected, the ROW will remain open for subsequent accesses. After a WRITE command has been issued, the WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 76 though Figure 84, AUTO PRECHARGE is disabled. During WRITE bursts, the first valid data-in element is registered on a rising edge of DQSx following the WRITE LATENCY (WL) clocks later and subsequent data elements will be registered on successive edges of DQSx. WRITE LATENCY (WL) is defined as the sum of POSTED CAS ADDITIVE LATENCY (AL) and CAS WRITE LATENCY (CWL): WL = AL + CWL. The values of AL and CWL are programmed in the MR- and MR2 registers, respectively. P rior to the first valid DQSx edge, a full cycle is needed (including a dummy crossover of DQSx, DQSx\\) and speci fied as the WRITE preamble shown in Figure 76. The half cycle on DQSx following the last data-in element is known as the WRITE postamble. The time between the WRITE command and the first valid edge of DQSx is WL clocks ± tDQSS. Figure 77 through Figure 84 show the nominal case where tDQSS = 0ns; however, Figure 76 includes tDQSS (MIN) and tDQSS (MAX) cases. Data may be masked from completing a WRITE using data mask. The mask occurs on the DM ball aligned to the WRITE data. If DM i s LOW, the WRITE completes normally. If DM is HIGH, that bit of data is masked. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain HIGH-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous flow of input data. The new WRITE command can be tCCD clocks following the previous WRITE command. The first data element from the new burst is applied after the last element of a completed burst. Figures 77 and 78 show concatenated bursts. An example of nonconsecutive WRITES is shown in Figure 79. Data for any WRITE burst may be followed by a subsequent READ command after tWTR has been met (see Figures 80, 81 and 82). Data for any WRITE burst may be followed by a subsequent PRECHARGE command providing tWR has been met, as shown in Figure 83 and Figure 84. Both tWTR and tWR starting time may vary depending on the mode register settings (fixed BC4, BL8 vs. OTF).

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 124 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 76 - WRITE BURST Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0. 3. DI n = data-in for column n. 4. BL8, WL = 5 (AL = 0, CWL = 5). 5. tDQSS must be met at each rising clock edge. 6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH. DI n + 3DI n + 2DI n + 1DI n T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Don’t CareTransitioning Data DI n + 7DI n + 6DI n + 5DIn + 4 Bank,Col n NOPWRITE NOPNOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command 1 DQ3 DQS , DQS# Address 2 tWPST tWPRE tWPST tDQSL DQ3 DQ3 tWPS T DQS , DQS# DQS , DQS# tDQSL tWPRE tDQSS tDQSS tDSH tDSH tDSH tDSH tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSH tDSH tDSH tDSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSL tDQSL tDQSL tDQSLtDQSHtDQSH tDQSH tDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH WL = AL + CWL tDQSS (MIN) tDQSS (NOM) tDQSS (MAX) tDQSL tWPRE DI n + 3DI n + 2DI n + 1DI n DI n + 7DI n + 6DI n + 5DIn + 4 DI n + 3DI n + 2DI n + 1DI n DI n + 7DI n + 6DI n + 5DIn + 4

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 125 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 77 - CONSECUTIVE WRITE (BL8) TO WRITE (BL8) Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at T0 and T4. 3. DI n (or b) = data-in for column n (or column b). 4. BL8, WL = 5 (AL = 0, CWL = 5). WL = 5 WL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tCCD tWPRE T10 T11 Don’t CareTransitioning Data T12 T13 T14 ValidValid NOPWRITE WRITENOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 DQ3 DQS , DQS# Address 2 tWPST tWR tWTR tBL = 4 clocks DI n + 3DI n + 2DI n + 1DI n DI n + 7DI n + 6DIn + 5DIn + 4 DI b + 3DI b + 2DI b + 1DI b DI b + 7DI b + 6DI b + 5DIb + 4 FIGURE 78 - CONSECUTIVE WRITE (BC4) TO WRITE (BC4) VIA MRS OR OTF Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BC4, WL = 5 (AL = 0, CWL = 5). 3. DI n (or b) = data-in for column n (or column b). 4. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4. WL = 5 WL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tCCD tWPRE T10 T11 Don’t CareTransitioning Data T12 T13 T14 Valid Valid NOPWRITE WRITENOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 DQ3 DQS , DQS# Address2 tWPST tWR tWTR tWPST tWPRE DI n + 3DI n + 2DI n + 1DIn DI b + 3DI b + 2DI b + 1DI b tBL = 4 clocks

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 126 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 79 - NONCONSECUTIVE WRITE TO WRITE Notes: 1. DI n (or b) = data-in for column n (or column b). 2. Seven subsequent elements of data-in are applied in the programmed order following DO n. 3. Each WRITE command may be to any bank. 4. Shown for WL = 7 (CWL = 7, AL = 0). CK CK# Command NOP NOP NOP Address DQ DM DQS , DQS# Transitioning Data NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOPWRITE NOP WRITE ValidValid NOP DIn DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 Don't Care DIn + 7 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7 WL = CWL + AL = 7 WL = CWL + AL = 7 FIGURE 80 - WRITE (BL8) TO READ (BL8) Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T9. 3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0. 4. DI n = data-in for column n. WL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tWPRE T10 T11 Don’t CareTransitioning Data Ta0 NOPWRITE READ ValidValid NOP NOP NOP NOP NOP NOP NOP NOPNOP NOP CK CK# Comman d1 DQ4 DQS , DQS # Address 3 tWPST tWTR 2 Indicates a Break in Time Scale DIn + 3DIn + 2DIn + 1DIn DIn + 7DIn + 6DIn + 5DIn + 4

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 127 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 81 - WRITE TO READ (BC4 MODE REGISTER SETTING) Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2.tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T7. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5). WL = 5 T0 T1 T2T3T4T5T6T7 T8 T9Ta0 Don’t Care Transitioning Data NOP WRITE Valid READ Valid PON PON PON PON PON PON PON NOP CK CK# Command1 DQ4 DQS , DQS# Address3 tWPST tWTR2 tWPRE Indicates a Break in Time Scale DIn + 3 DIn + 2 DIn + 1 DIn

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 128 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 82 - WRITE (BC4 OTF) TO READ (BC4 OTF) Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2.tWTR controls the WRITE-to -READ delay to the same device and starts after tBL. 3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A 12 = 0 during the WRITE command at T0 and the READ command at Tn. 4. DI n = data-in for column n. 5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). WL = 5RL = 5 T0 T1 T2T3T4T5T6T7 T8 T9 tWPRE T10 T11 Don’t Care Transitioning Data Tn NOP WRITEREAD Valid Valid NOP NOP NOP NOP NOP NOP NOP NOPNOP CK CK# C ommand1 DQ4 DQS , DQS# Address3 tWPS T tBL = 4 clocks NOP tWTR2 Indicates a Break in Time Scale DI n + 3 DI n + 2 DI n + 1 DI n

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 129 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 83 - WRITE (BL8) TO PRECHARGE Notes: 1. DI n = data-in from column n. 2. Seven subsequent elements of data-in are applied in the programmed order following DO n. 3. Shown for WL = 7 (AL = 0, CWL = 7). T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1 DIn + 3DIn + 2DIn + 1DIn DIn + 6 DIn + 7DIn + 5DIn + 4 NOPWRITE Valid NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE CK CK# Command DQ BL8 DQS , DQS# Address Don’t CareTransitioning DataIndicates a Break in Time Scale tWRWL = AL + CWL Valid FIGURE 84 - WRITE (BC4 MODE REGISTER SETTING) TO PRECHARGE Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time ( tWR) is referenced from the first rising clock edge after the last write data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5, RL = 5. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1 DIn + 3DIn + 2DIn + 1DIn NOPWRITE Valid NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE CK CK# Comman d DQ BC4 DQS , DQS# Address Don’t CareTransitioning DataIndicates a Break in Time Scale tWRWL = AL + CWL Valid

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 130 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 85 - WRITE (BC4 OTF) TO PRECHARGE Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time ( tWR) is referenced from the rising clock edge at T9. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (OTF), WL = 5, RL = 5. WL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn Don’t Care Transitioning Data Bank, Col n NOP WRITE PRENOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 DQ4 DQS , DQS # Address 3 tWPST tWPRE Indicates a Break In Time Scale DI n + 3 DI n + 2 DI n + 1 DI n tWR2 Valid DQ INPUT TIMING FIGURE 86 - DATA INPUT TIMING tDH tDS DM DQ DI b DQ S, DQS# Don ’t CareTransitioning Data tDQSH tDQSLtWPRE tWPST memory controller after the last data is written to the SDRAM during the WRITE postamble,tWPST. Data setup and hold times are shown in Figure 86. All setup and hold times are measured from the crossing points of DQSx and DQSx\\. These setup and hold values pertain to data input and data mask input. Additionally, the half period of the data input strobe is speci fied by tDQSH and tDQSL. Figure 76 shows the strobe to clock timing during a WRITE. DQSx, DQSx\\ must transition within 0.25tCK of the clock transitions as limited by tDQSS. All data and data mask setup and hold timings are measured relative to the DQSx, DQSx\\ crossings, not the clock crossing. The WRITE preamble and postamble are also shown. One clock prior to data input to the SDRAM, DQSx must be HIGH and DQSx\\ must be LOW. Then for a half clock, DQSx is driven LOW (DQSx\\ is driven HIGH) during the WRITE preamble. tWPRE, likewise, DQSx must be kept LOW by the

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 131 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product PRECHARGE Input A10 determines whether one bank or all banks are to be PRECHARGED and in the case where only one bank is to be precharged, inputs BA[2:0] select the array BANK. When all banks are to be PRECHARGED, inputs BA[2:0] are treated as “Don’t Care”. After a bank is PRECHARGED, it is in the IDLE State and must be ACTIVATED prior to any READ or WRITE commands being issued. SELF REFRESH The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. All power supply inputs (including V REFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode operation. V REFDQ may float or not drive VccQ/2 while in the SELF REFRESH mode under certain conditions: Vss<V• REFDQ<Vcc is maintained V• REFDQ is valid and stable prior to CKE going back HIGH The first WRITE operation may not occur earlier than 512 clocks after V• REFDQ is valid All other SELF REFRESH mode exit timing requirements are met• The SDRAM must be idle with all BANKS in the PRECHARGE state (tRP is satisfied and no bursts are in progress) before a SELF REFRESH entry command can be issued. ODT must also be turned off before SELF REFRESH entry by registering the ODT ball LOW prior to the SELF REFRESH entry command (see “On-Die Termination (ODT) for timing requirements). If RTT_NOM and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care”. After the SELF REFRESH entry command is registered, CKE must be held LOW to keep the SDRAM in SELF REFRESH mode. After the SDRAM has entered SELF REFRESH mode, all external control signals, except CKE and RESET\\, become “Don’t Care”. The S DRAM initiates a minimum of one REFRESH command internally within the tCKE period when it enters SELF REFRESH mode. The requirements for entering and exiting SELF REFRESH mode depend on the state of the clock during SELF REFRESH mode. First and foremost, the clock must be stable (meeting tCK specifications) when SELF REFRESH mode is entered. If the clock remains stable and the frequency in not altered while in SELF REFRESH mode, then the SDRAM is allowed to exit SELF REFRESH after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR later than when CKE was registered LOW). Since the clock remains stable in SELF REFRESH mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the clock is altered during SELF REFRESH mode, then tCKSRE and tCKSRX must be satisfied. When entering SELF REFRESH, tCKSRE must be satisfied prior to altering the clock’s frequency. Prior to exiting SELF REFRESH, tCKSRX must be satisfied prior to registering CKE HIGH. When CKE is HIGH during SELF REFRESH exit, NOP or DES must be issued for tXS time. tXS is required for the completion of any internal REFRESH that is already in progress and must be satisfied before a valid command not requiring a locked DLL can be issued to the device. tXS is also the earliest time that a SELF REFRESH re-entry may occur (see Figure 87). Before a command requiring a locked DLL can be applied, a ZQCL command must be issued. tZQOPER timing must be met and tXSDLL must be satisfied. ODT must be off during tXSDLL.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 132 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 87 - SELF REFRESH ENTRY/EXIT TIMING Notes: 1. The clock must be valid and stable meeting tCK specifications at least tCKSRE after entering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not apply; however , tCKESR must be satisfied prior to exiting at SRX. 2. ODT must be disabled and R TT off prior to entering self refresh at state T1. If both RTT_NOM and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care.” 3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW. 4. A NOP or DES command is required at T2 after the SRE command is issued prior to the inputs becoming “Don’t Care.” 5. NOP or DES commands are required prior to exiting self refresh mode until state Te0. 6. tXS is required before any commands not requiring a locked DLL. 7. tXSDLL is required before any commands requiring a locked DLL. 8. The device must be in the all banks idle state prior to entering self refresh mode. For exam- ple, all banks must be precharged, tRP must be met, and no data bursts can be in progress. 9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that tISXR is satisfied at Tc1. CK CK# Command NOP NOP4SRE(REF)3 Address CKE ODT2 RESET#2 Valid Valid6SRX (NOP) NOP5 tRP 8 tXS 6 , 9 tXSDLL7, 9 ODTL tIStCPDEDtIS tIS Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) T0 T1 T2 Tc 0 Tc1 Td0 Tb0 Don’t Care Te0 Valid Valid7 Valid Valid Valid tIH Ta0 Tf0 Indicates a Break in Time Scale tCKSRX1tCKSRE1 tCKESR (MIN)1

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 133 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Self Refresh Temperature (SRT) EXTENDED TEMPERATURE USAGE LOGIC Devices, Inc iMOD DDR3 SDRAM module supports the optional extended temperature range up to ≤95˚C while supporting SELF REFRESH/AUTO REFRESH and support Tc temperatures >95 ˚C ≤125˚C with MANUAL REFRESH only. When using SELF REFRESH/AUTO REFRESH and the case tem- perature is >85˚C, SRT and ASR options must be used. The extended range temperature range SDRAM must be REFRESHED externally at 2X anytime the case temperature is >85˚C. The external REFRESHING requirement is accomplished by reducing the REFRESH PERIOD from 64ms to 32ms. SELF REFRESH mode requires the use of ASR or SRT to support the extended temperature. Field MR2 Bits Description SRT ASR TABLE 68: SELF REFRESH TEMPERATURE AND AUTO SELF REFRESH DESCRIPTION If ASR is disabled (MR2[6]=0), SRT must be programmed to indicate tOPER during SELF REFRESH; * MR2[7] = 0: Normal operating temperature range (0˚C to ≤ 85˚C) * MR2[7] = 1: Extended operating temperature range (>85˚C to ≤ 105˚C) If ASR is enabled (MR2[7]=1), SRT must be set to 0, even if the extended temperature range is supported. *MR2[7]=0: SRT is disabled. When ASR is enabled, the SDRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values) *MR2[6]=1: ASR is enabled (M7 must = 0) When ASR is not enabled, the SRT bit must be programmed to indicate tOPER during SELF REFRESH operation. *MR2[6]=0: ASR is disabled, must use manual SELF REFRESH (SRT) Auto Self Refresh (ASR) SELF REFRESH Operation TABLE 69: SELF REFRESH MODE SUMMARY SELF REFRESH Mode is supported in the normal temperature range. SELF REFRESH Mode is supported in normal and extended (≤ 95˚C MAX) temperature ranges; When SRT is enabled, it increases self refresh power consumption. Self refresh mode is supported in normal and extended temperature ranges; Self refresh power consumption may be temperature-dependent. Illegal. Permitted Operating Temperature Range for Self Refresh Mode MR2[7] (SRT) MR2[6] (ASR) Normal (0°C to 85°C) Normal and extended (0°C to 95°C) Normal and extended (0°C to 95°C) POWER-DOWN MODE Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ or WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations are in progress. However, the POWER-DOWN Icc specifications are not applicable until such operations have been completed. Depending on the previous SDRAM state and the command issued prior to CKE going LOW, certain timing constraints must be satis fied (as noted in Table 70). Timing diagrams detailing the different POWER-DOWN mode entry and exits are shown in Figure 88 through Figure 97.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 134 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Idle or Active Idle or Active Active Active Active Active Active Idle POWER-DOWN Idle TABLE 70: COMMAND TO POWER-DOWN ENTRY PARAMETERS tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRAPDEN tREFPDEN tXPDLL tMRSPDEN ACTIVATE PRECHARGE READ or READAP WRITE: BL8OTF, BL8MRS, BC4OTF WRITE: BC4MRS WRITEAP: BL8OTF, BL8MRS, BC4OTF WRITEAP: BC4MRS REFRESH REFRESH MODE REGISTER SET Last Command prior to CKE Low 1 1tCK 1tCK RL = 4tCK + 1tCK WL + 4tCK + tWR/ tCK WL + 2tCK + tWR/ tCK WL + 4tCK + WR + 1tCK WL + 2tCK + WR + 1tCK 1tCK Greater of 10tCK or 24ns tMOD Figure 95 Figure 96 Figure 91 Figure 92 Figure 92 Figure 93 Figure 93 Figure 94 Figure 98 Figure 97 SDRAM Status Parameter (MIN) Parameter Value Figure Entering POWER-DOWN mode disables the input and output buffers, excluding CK, CK\\, ODT, CKE and RESET\\. NOP or DES commands are required until tCPDED has been satis fied, at which time all speci fied input/output buffers will be disabled. The DLL should be in a locked state when POWER-DOWN is entered for the fastest mode timing. If the DLL is not locked during the POWER-DOWN entry, the DLL must be reset after exiting POWER-DOWN for proper READ operation as well as synchronous ODT operation. During POWER-DOWN entry, if any bank remains open after all in-progress commands are complete, the SDRAM will be in ACTIVE POWE R-DOWN. If all banks are closed after all in-progress commands are complete, the SDRAM will be in PRECHARGE POWER-DOWN mode or fast EXIT mode. When entering PRECHARGE POWER-DOWN, the DLL is turned off in slow exit mode or kept on in fast EXIT mode. The DLL remains on when entering ACTIVE POWER-DOWN as well. ODT has special timing constraints when slow EXIT mode, PRECHARGE POWER- DOWN is enabled and entered. Refer to “Asynchronous ODT Mode” for detailed ODT usage requirements in slow EXIT mode PRECHARGE POWER-DOWN. A summary of the two POWER-DOWN modes is listed in Table 71. While in either POWER-DOWN state, CKE is held LOW, RESET\\ is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are a “Don’t Care”. If RESET\\ goes LOW during POWER-DOWN, the SDRAM will switch out of POWER-DOWN and go into the RESET state. After CKE is registered LOW, CKE must remain LOW until tPD (MIN) has been satis fied. The maximum time allowed for POWER-DOWN duration is tPD (MAX) (9 x tREFI). The POWER-DOWN states are synchronously exited when CKE is registered HIGH (with a required NOP or DES command). CKE must be maintained HIGH until tCKE has been satisfied. A valid, executable command may be applied after POWER-DOWN EXIT LATENCY, tXP, tXPDLL have been satisfied. A sum- mary of the POWER-DOWN modes is listed in Table 71. D L L S t a t e ACTIVE (any bank open) PRECHARGE (all banks PRECHARGED) TABLE 71: POWER-DOWN MODES ON ON OFF Relevant ParametersMR1[12] tXP to any other valid COMMAND tXP to any other valid COMMAND tXDLL to COMMANDS that require the DLL to be locked (READ, RDAP, ODT ON). tXP to any other valid COMMAND. SDRAM State “Don’t Care” FAST FAST SLOW POWER-DOWN exit

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 135 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 88 - ACTIVE POWER-DOWN ENTRY AND EXIT CK CK# Command NOP NOP NOP NOP Address CKE tCK tCH tCL Enter power-down mode Exit power-down mode Don’t Care ValidValid Valid tCPDED Valid tIS tIH tIH tIS T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 NOP tXP tCKE (MIN) Indicates a Break in Time Scale tPD FIGURE 89 - PRECHARGE POWER-DOWN (FAST-EXIT MODE) ENTRY AND EXIT tCKEmin tCKEmin CK CK# PONPONPONPONdnammoC CKE tCK tCH tCL Enter power-down mode Exit power-down mode tPD Valid tCPDED tIS tIHtIS T0 T1 T2 T3 T4 T5 Ta0 Ta1 NOP Don’t CareIndicates a Break in Time Scale tCKE (MIN) tXP

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 136 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 90 - PRECHARGE POWER-DOWN (SLOW-EXIT MODE) ENTRY AND EXIT Notes: 1. Any valid command not requiring a locked DLL. 2. Any valid command requiring a locked DLL. CK CK# Command PON PON PON CKE tCK tCH tCL Enter power-down mode Exit power-down mode tPD Valid2Valid1PRE tXPDLL tCPDED tIS tIH tIS T0 T1 T2 T3 T4 Ta Ta1 Tb NOP Don’t Care Indicates a Break in Time Scale tXP tCKE (MIN) FIGURE 91 - POWER-DOWN ENTRY AFTER READ OR READ WITH AUTO PRECHARGE (RDAP) T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Don’t CareTransitionin g Data Ta10 Ta11 Ta12 NOP Valid READ/ RDAP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command DQ BL8 DQ BC4 DQS , DQS# Address CKE tCPDEDtIS tPD Power-down or self refresh entry Indicates a Break In Time Sc ale tRDPDEN DIn + 3DIn + 1 DIn + 2DIn RL = AL + CL DI n + 3DI n + 2DI n + 1DIn DI n + 6 DI n + 7DI n+ 5DI n + 4

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 137 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 92 - POWER-DOWN ENTRY AFTER WRITE Notes: 1. CKE can go LOW 2 tCK earlier if BC4MRS. T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 Tb4 NOPWRITE Valid NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command DQ BL8 DQ BC4 DQS , DQS# Address CKE tCPDED Power-down or self refresh entry 1 Don’t Car eTransitioning Data tWRPDEN DIn + 3DIn + 1 DIn + 2DIn tPD Indicates A Break in Time Scale DI n + 3DI n + 2DI n + 1DI n DI n + 6 DI n + 7DI n + 5DI n+ 4 tIS WL = AL + CWL tWR FIGURE 93 - POWER-DOWN ENTRY AFTER WRITE WITH AUTO PRECHARGE (WRAP) Notes: 1. tWR is programmed through MR0[11:9] and represents tWR (MIN)ns/ tCK rounded up to the next integer tCK. 2. CKE can go LOW 2 tCK earlier if BC4MRS. T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta 6 Ta7 Tb0 Tb1 Don’t Car eTransitioning Data Tb2 Tb3 Tb4 NOPWRAP Valid NOP NOP NOP CK CK# Command DQ BL8 DQ BC4 DQS , DQS# Address A10 CKE tPD tWRAPDEN Power-down or self refresh entry 2 Start internal precharge tCPDEDtIS Indicates a Break in Time Scale DI n + 3DI n + 2DI n + 1DIn DI n + 6 DI n + 7DI n + 5DI n + 4 DI n + 3DI n + 2DI n + 1DI n WR1WL = AL + CWL NOP NOP NOP NOP NOP NOP NOP NOP

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 138 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 94 - REFRESH TO POWER-DOWN ENTRY Notes: 1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied. CK CK# Command REFRESH NOP NOP NOP NOP Valid CKE tCK tCH tCL tCPDED tREFPDEN tIS T0 T1 T2 T3 Ta0 Ta1 Ta2 Tb0 tXP (MIN) tRFC (MIN)1 Don’t CareIndicates a Break In Time Scale tCKE (MIN) tPD FIGURE 95 - ACTIVATE TO POWER-DOWN ENTRY tCKE CK CK# Command Address ACTIVE NOP NOP CKE tCK tCH tCL Don’t Care tCPDED tACTPDEN Valid tIS T0 T1 T2 T3 T4 T5 T6 T7 tPD

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 139 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 96 - PRECHARGE TO POWER-DOWN ENTRY CK CK# Command Address CKE tCK tCH tCL Don’t Care tCPDED tPREPDEN tIS T0 T1 T2 T3 T4 T5 T6 T7 tPD All/single bank PRE NOP NOP FIGURE 97 - MRS COMMAND TO POWER-DOWN ENTRY CK CK# CKE tCK tCH tCL tCPDED Address tIS T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 tPD Don’t CareIndicates a Break in Time Scale Valid Command MRS NOP NOP NOP NOP NOP tMRSPDEN

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 140 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 98 - POWER-DOWN EXIT TO REFRESH TO POWER-DOWN ENTRY Notes: 1. tXP must be satisfied before issuing the command. 2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. CK CK# CKE tCK tCH tCL Enter power-down mode Enter power-down mode Exit power-down mode tPD tCPDED tIS tIHtIS T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Don’t CareIndicates a Break in Time Scale Command NOP NOP NOP NOP REFRESH NOPNOP tXP1 tXPDLL2 RESET The RESET signal (RESET\\) is an asynchronous signal that triggers any time it drops LOW and there are no restrictions about whe n it can go LOW. After RESET\\ is driven LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off (HIGH-Z) and the DDR3 SDRAM resets itself. CKE should be brought LOW prior to RESET\\ being driven HIGH. After RESET\\ goes HIGH, the SDRAM must be re-initialized as though a normal power up were executed (see Figure 99). All refresh counters on the SDRAM are RESET and data stored in the SDRAM is assumed un known after RESET\\ has been driven LOW.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 141 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 99 - RESET SEQUENCE CKE RTT BA[2:0] All voltage supplies valid and stable High-Z DM DQS High-Z Address A10 CK CK# tCL Command NOP T0 Ta0 Don’t Care tCL tIS ODT DQ High-Z Tb0 tDLLK MR1 with DLL ENABLE MRS MRS BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Code Code Code Code Vali d Valid Valid Valid Normal operation MR2 MR3 MRS MRS BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L Code Code Code Code Tc0 Td0 RESET# Stable and valid clock Vali d Vali d DRAM ready for external commands tZQINIT A10 = H ZQCL tIS tIOZ Vali d Vali d Vali d System RESET (warm boot) ZQ CAL MR0 with DLL RESET T=10ns (MIN) T = 100ns (MIN) Indicates a Break in Time Scale T = 500μs (MIN) tXPR tMRD tMRD tMRD tMOD T (MIN) = MAX (10ns, 5tCK) tCK

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 142 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ON-DIE TERMINATION (ODT) ODT is a feature that enables the SDRAM to enable/disable on-die termina- tion resistance for each DQ, LDQSx, LDQSx\\ , UDQSx, UDQSx\\ LDMx and UDMx for the four words contained in LDI’s DDR3 iMOD. The ODT feature is designed to improve signal integrity of the memory array/ sub-system by enabling the DDR3 memory controller to independently turn on or off the SDRAMS internal termination resistance for any grouping of SDRAM devices. The ODT feature is not supported during DLL disable mode. A simple functional representation of the SDRAM ODT feature is shown in Figure 100. The switch is enabled by the internal ODT control logic, which uses the external ODT ball and other control information. FUNCTIONAL REPRESENTATION OF ODT The value of RTT (ODT termination value) is determined by the settings of several mode register bits (see Table 75). The ODT ball is ignored while in SELF REFRESH mode (must be turned off prior to SELF REFRESH entry) or if mode registers MR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT and dynamic ODT modes and either of these can function in synchronous or asynchronous modes (when the DLL is off during PRECHARGE POWER-DOWN or when the DLL is synchroniz- ing). Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic ODT is applied only during WRITEs and provides OTF switching from no R TT or RTT_NOM to RTT_WR. The actual effective termination, R TT_EFF may be different from the R TT targeted due to nonlinearity of the termination. For R TT_EFF values and calculations, see “ODT Characteristics”. ODT VCCQ/2 RTT Switch DQ, DQS , DQS #, To other circuitry such as RCV, . . . DM FIGURE 100 - ON-DIE TERMINATION NOMINAL ODT ODT (NOM) is the base termination resistance for each applicable ball, enabled or disabled via MR1[9,6,2] (see Figure 46), and it is turned on or off via the ODT ball. TABLE 72: POWER-DOWN MODES MR1[9,6,2] ODT Pin SDRAM Termination State SDRAM State N o t e s RTT_NOM disabled, ODT OFF RTT_NOM disabled, ODT ON RTT_NOM enabled, ODT OFF RTT_NOM enabled, ODT ON RTT_NOM reserved, ODT ON or OFF Any valid Any valid except SELF REFRESH, READ Any valid Any valid except SELF REFRESH, READ Illegal 1,2 1,3 1,2 1,3 000 000 000-101 000-101 110 and 111 X ODT must be disabled during READs. The 3. R TT_NOM value is restricted during WRITES. Dynamic ODT is applicable if enabled. NOTES: Assumes dynamic ODT is disabled.1. ODT is enabled and active during most WRITES for proper termination, 2. but it is not illegal to have it off during WRITES.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 143 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product Nominal ODT resistance RTT_NOM is defined by MR1[9,6,2], as shown in Figure 46. The R TT_NOM termination value applies to the output pins previously mentioned. DDR3 SDRAM iMODs support multiple RTT_NOM values based on RZQ/n where n can be 2,4,6,8 or 12 and RZQ is 240Ω±1%. RTT_NOM termina- tion is allowed any time after the SDRAM is initialized, calibrated and not performing READ accesses or when it is not in SELF REFRESH mode. WRITE access uses RTT_NOM id dynamic ODT (RTT_WR) is disabled. If RTT_NOM is used during WRITEs, only RZQ/2, RZQ/4 and RZQ/6 are allowed (see Table 71). ODT timings are summarized in Table 73, as well as, listed in Table 50. Examples of nominal ODT timing are shown in conjunction with the synchronous mode of operation in “Synchronous ODT Mode”. TABLE 73: ODT PARAMETER Symbol Description Begins at Defined to Units ODT registered HIGH ODT registered HIGH ODT registered HIGH ODT registered HIGH ODT registered HIGH or WRITE registration with ODT HIGH WRITE registration with ODT HIGH Completion of ODTL on Completion of ODTL off ODTL ON ODTL OFF tAONPD tAOFFPD ODTH4 ODTH8 tAON tAOF ODT synchronous turn on delay ODT synchronous turn off delay ODT asynchronous on delay ODT asynchronous on delay ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODT minimum HIGH time after WRITE (BL8) ODT turn-on relative to ODTL on completion ODT turn-off relative to ODTL off completion RTT_ON ± tAON RTT_ON ± tAOF RTT_ON RTT_OFF ODT registered LOW ODT registered LOW RTT_ON RTT_OFF CWL + AL - 2 CWL + AL - 2 1-9 1-9 TcK 6TcK See Table 50 0.5TcK ± 0.2TcK tCK tCK ns ns tCK tCK ps tCK Definition for All DDR3 bins DYNAMIC ODT In certain applications, to further enhance signal integrity on the data bus, it is desirable that the termination strength, be changed without issuing an MRS command, essentially changing the ODT termination resistance on-the- fly. With dynamic ODT (R TT_WR) enabled, the SDRAM switches from nominal ODT (RTT_NOM) to dynamic ODT when beginning a WRITE burst and subsequently switches back to nominal ODT at the completion of the WRITE burst sequence. This requirement and the supporting DYNAMIC ODT feature of the DDR3 SDRAM makes it feasible and is described in further detail below: DYNAMIC ODT FUNCTIONAL DESCRIPTION: The dynamic ODT mode is enabled if either MR2[9] or mR2[10] is set to “1”. Dynamic ODT is not supported during DLL disable mod e, so RTT_WR must be disabled. The dynamic ODT function is described, as follows: Two R• TT values are available – RTT_NOM and RTT_WR: The value of R• TT_NOM is preselected via MR1[9,6,2] The value for R• TT_WR is preselected via MR2[10,9] During SDRAM operations without READ or WRITE commands, the termination is controlled as follows:• Termination ON/OFF timing is controlled via the ODT ball and LATENCIES ODTl on and ODTL off• Nominal termination strength R• TT_NOM is used When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered and if dynamic ODT is enabled, the ODT ter-• mination is controlled as follows: A latency of ODTLCNW after the WRITE command: termination strength R• TT_NOM switches to RTT_WR A Latency of ODTLCWN8 (for BL8, fixed or OTF) or ODTLCWN4 (for BC4, fixed or OTF) after the WRITE command: termination • strength RTT_WR switches back to RTT_NOM ON/OFF termination timing is controlled via the ODT ball and determined by ODTL on, ODTL off, ODTH4 and ODTH8.• During the • tADC transition window, the value of RTT is undefined ODT is constrained during WRITEs and when dynamic ODT is enabled (see Table 74). NOMINAL ODT

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 144 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 74: DYNAMIC ODT SPECIFIC PARAMETERS Symbol Description Begins at Defined to Units WRITE registration WRITE registration WRITE registration ODTL CNW ODTLCNW ODTLCWN4 ODTLCWN8 tADC Change from RTT_NOM to RTT_WR Change from RTT_WR to RTT_NOM (BC4) Change from RTT_WR to RTT_NOM (BL8) RTT change skew RTT switched from RTT_NOM to RTT_WR RTT switched from RTT_WR to RTT_NOM RTT switched from RTT_WR to RTT_NOM RTT trans complete WL - 2 4tCK + ODTL OFF 6tCK + ODTL OFF 0.5tCK ± 0.2tCK tCK tCK tCK tCK Definition for All DDR3 bins TABLE 75: MODE REGISTERS FOR RTT_NOM M9 M6 M2 RTT_NOM (RZQ) RTT_NOM(Ohms) RTT_NOM Mode Restriction Off RZQ/4 RZQ/2 RZQ/6 RZQ/12 RZQ/8 Reserved Reserved n/a SELF REFRESH SELF REFRESH, WRITE n/a n/a Off 120 Reserved Reserved MR1(RTT_NOM) TABLE 76: MODE REGISTERS FOR RTT_WR M10 M2 RTT_NOM (RZQ) RTT_NOM(Ohms) n/a n/a n/a n/a RZQ/4 RZQ/2 Reserved n/a n/a n/a n/a n/a n/a n/a n/a 120 Reserved n/a n/a n/a n/a MR1(RTT_NOM) Dynamic ODT OFF: WRITE does not affect RTT_NOM TABLE 77: TIMING DIAGRAMS FOR DYNAMIC ODT Figure Title Figure 101 Figure 102 Figure 103 Figure 104 Figure 105 Dynamic ODT: ODT asserted before and after the WRITE, BC4 Dynamic ODT: Without WRITE command Dynamic ODT: ODT pin asserted together with WRITE command for 6 CK cycles, BL8 Dynamic ODT: ODT pin asserted with WRITE command for 6 CK cycles, BC4 Dynamic ODT: ODT pin asserted with WRITE command for 4 CK cycles, BC4

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 145 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 101 - DYNAMIC ODT: ODT ASSERTED BEFORE AND AFTER THE WRITE, BC4 Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. R TT_NOM and RTT_WR are enabled. 2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example, ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command). T0 T1 T2 T3 T4 T5 T 6T 7T 8T 9 ODTL on ODTL CWN4 ODTLCNW WL ODTL off T10 T11 T12 T13 T14 T15 T17T16 CK CK# Command Address RTT ODT DQ DQS , DQS# Valid WRS 4 P ONPONPONPONPON NOP NOP Don’t CareTransitioning RTT_WRRTT_NOM RTT_NOM DIn + 3DIn + 2DIn + 1DIn NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP ODTH4 ODTH4 tAON (MIN) tADC (MIN) tADC (MIN) tAOF (MIN) tAON (MAX) tADC (MAX) tADC (MAX) tAOF (MAX) FIGURE 102 - DYNAMIC ODT: WITHOUT WRITE COMMAND Notes: 1. AL = 0, CWL = 5. R TT_NOM is enabled and R TT_WR is either enabled or disabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 ODTL off T10 T11 CK CK# RTT Don’t CareTransitioning Command Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Address DQS , DQS# DQ ODTH4 ODTL on tAON (MAX) tAON (MIN) tAOF (MIN) tAOF (MAX) ODT RTT_NOM

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 146 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 103 - DYNAMIC ODT: ODT PIN ASSERTED TOGETHER WITH WRITE COMMAND FOR 6 CLOCK CYCLES, BL8 Notes: 1. Via MRS or OTF; AL = 0, CWL = 5. If R TT_NOM can be either enabled or disabled, ODT can be HIGH. RTT_WR is enabled. 2. In this example, ODTH8 = 6 is satisfied exactly. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 ODTLCWN8 ODTLON ODTLCNW WL tAOF (MAX) T10 T11 CK CK# Address RTT ODT DQ DQS , DQS# DI b + 3DI b + 2DI b + 1DI b DI b+ 7DI b + 6DI b + 5DI b + 4 Valid Don’t CareTransitioning Command WRS 8NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP RTT_WR ODTH8 ODTLOFF tADC (MAX) tAON (MIN) tAOF (MIN) FIGURE 104 - DYNAMIC ODT: ODT PIN ASSERTED WITH WRITE COMMAND FOR 6 CLOCK CYCLES, BC4 Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. R TT_NOM and RTT_WR are enabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 ODTL on ODTLCNW WL T10 T11 CK CK# ODTLCWN4 DQS , DQS# Address Valid Don’t CareTransitioning ODTL off Command WRS 4NOP NOP NOP NOP NOP NOP NOP NOP DQ DIn+ 3DIn + 2DIn + 1DIn tADC (MIN) tAOF (MIN) tAOF (MAX)tADC (MAX) tADC (MAX) tAON (MIN) ODTH4 ODT RTT RTT_WR RTT_NOM NOP NOP NOP

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 147 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 105 - DYNAMIC ODT: ODT PIN ASSERTED WITH WRITE COMMAND FOR 4 CLOCK CYCLES, BC4 Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. R TT_NOM can be either enabled or disabled. If disabled, ODT can remain HIGH. RTT_WR is enabled. 2. In this example ODTH4 = 4 is satisfied exactly. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 ODTL on ODTLCNW WL T10 T11 CK CK# ODTLCWN4 DQS , DQS# Address Valid RTT_WR Command WRS4NOP NOP NOP NOP NOP NOP NOP NOP NOP Don’t CareTransitioning DQ DI n DI n + 3 DI n + 2 DI n + 1 ODTH4 tADC (MAX) tAON (MIN) tAOF (MIN) tAOF (MAX) ODTL off RTT RTT_WR ODT NOP NOP SYNCHRONOUS ODT MODE Synchronous ODT is selected whenever the DLL is turned on and locked while RTT_NOM or R TT_WR is enabled. Based on the POWER-DOWN definition, these modes are: Any bank ACTIVE with CKE HIGH• REFRESH mode with CKE HIGH• DLE mode with CKE HIGH• ACTIVE POWER-DOWN mode (regardless of • MR0[12]) PRECHARGE POWER-DOWN mode if DLL is • enabled during PRECHARGE POWER-DOWN by MR0[12] ODT LATENCY AND POSTED ODT In synchronous ODT mode, RTT turns on ODTL on clock cycles after ODT is sampled HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around each clock edge (see Table 78). The ODT LATENCY is tied to the WRITE LATENCY (WL) by ODTL on =WL-2 and ODTL off = WL- 2. Since WRITE LATENCY is made up of CAS WRITE LATENCY (CWL) and ADDITIVE LATENCY (AL), the AL value programmed into the mode regis- ter MR1[4,3], also applies to the ODT signal. The SDRAM’s internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus, ODTL on = CWL + AL – 2 and ODTL off = CWL + AL – 2.

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 148 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product SYNCHRONOUS ODT TIMING PARAMETERS Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off, ODTH4, ODTH8, tAON and tAOF (see Table 78 and Figure 106). The minimum RTT turn-on time ( tAON [MIN]) is the point at which the device leaves HIGH-A and ODT resistance begins to turn on. Maximum R TT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on. Both are measured relative to ODTL on. The minimum R TT turn-off time ( tAOF [min]) is the point at which the device starts to turn-off ODT resistance. Maximum RTT turn-off time (tAOF [MAX]) is the point at which ODT has reached HIGH-Z. Both are measured from ODTL off. When ODT is asserted, it must remain HIGH until ODTH4 is satis fied. If a WRITE command is registered by the SDRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 107). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW or from the registration of a WRITE command until ODT is registered LOW. TABLE 78: SYNCHRONOUS ODT PARAMETERS Symbol Description Begins at Defined to Units ODT registered HIGH ODT registered HIGH ODT registered HIGH, or WRITE registration with ODT HIGH WRITE registration with ODT HIGH Completion of ODTL on Completion of ODTL off ODTL ON ODTL OFF ODTH4 ODTH8 tAON tAOF ODT synchronous TURN-ON delay ODT synchronous TURN-OFF delay ODT Minimum HIGH time after ODT assertion or WRITE (BC4) ODT Minimum HIGH time after WRITE (BL8) ODT TURN-ON relative to ODTL on completion ODT TURN-OFF relative to ODTL off completion RTT_ON ± tAON RTT_OFF ± tAOF ODT registered LOW ODT registered LOW RTT_ON RTT_OFF CWL + AL - 2 CWL + AL - 2 4tcK 6tcK See Table 50 0.5tcK ± 0.2tcK tCK tCK tCK tCK ps tCK Definition for All DDR3 bins FIGURE 106 - SYNCHRONOUS ODT Notes: 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. R TT_NOM is enabled. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CWL -AL = 3AL = 3 tAON (MAX) T10 T11 T12 CK CK# RTT ODT RTT_NOM CKE ODTL off = CWL + AL - 2 ODTL on = CWL + AL - 2 ODTH4 (MIN) tAON (MIN)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 149 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 107 - SYNCHRONOUS ODT (BC4) Notes: 1. WL = 7. R TT_NOM is enabled. RTT_WR is disabled. 2. ODT must be held HIGH for at least ODTH4 after assertion (T1). 3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). 4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tAOF (MAX) tAOF (MIN) tAON (MAX) tAOF (MAX) T10 T11 T12 T13 T14 T15 T17 T16 CK CK# RTT CKE NOP WRS4NOP NOPNOP NOP NOP NOPCommand Don’t CareTransitioning tAON (MIN) RTT_NOM ODTLoff = WL - 2 ODTH4 (MIN) ODTH4 ODTL off = WL - 2 ODTL on = WL - 2 tAON (MIN) tAON (MAX) ODTH4 ODTL on = WL - 2 tAOF (MIN) ODT RTT_NOM NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP ODT OFF DURING READS As the DDR3 SDRAM cannot terminate and drive at the same time, R TT must be disabled at least one-half clock cycle before the READ preamble by driving the ODT ball LOW. RTT may not be enabled until the end of the postamble as shown in Figure 108. FIGURE 108 - ODT DURING READS Notes: 1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT_NOM is enabled. RTT_WR is a “Don’t Care.” T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T17T16 CK CK# ValidAddress DI b + 3 DI b + 2 DI b + 1 DI b DI b + 7 DI b + 6 DI b+ 5 DI b+ 4 DQ DQS , DQS# Don’t CareTransitioning Command NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOPNOPREAD ODTL on = CWL + AL - 2 ODT tAON (MAX)RL = AL + CL ODTL off = CWL + AL - 2 tAOF (MIN) RTT RTT_NOMRTT_NOM tAOF (MAX)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 150 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ASYNCHRONOUS ODT MODE Asynchronous ODT mode is available when the SDRAM runs in DLL ON mode and when either R TT_NOM or RTT_WR is enabled; however, the DLL is tem- porarily turned off in PRECHARGED POWER-DOWN standby via MR0[12]. Additionally, ODT operates asynchronously when the DLL is sy nchronizing after being RESET. See “POWER-DOWN MODE” for definition and guidance over POWER-DOWN details. In asynchronous ODT timing mode, the internal ODT command is not delayed by AL relative to the external ODT command. In asynchronous ODT mode, ODT controls RTT by analog time. The timing parameters tAONPD and tAOFPD (see Table 79) replace ODTL on/tAON and ODTL off/tAOF respectively, when ODT operates asynchronously (see Figure 109). The minimum RTT turn-on time (tAONPD [MIN]) is the point at which the device termination circuit leaves HIGH-Z and ODT resistance begins to turn-on. Maxi- mum RTT turn-on time (tAONPD [MAX]) is the point at which ODT resistance is fully on. tAONPD (MIN) and tAONPD (MAX) are measured from ODT being sampled HIGH. The minimum RTT turn-off time (tAOFPD [MIN]) is the point at which the device termination circuit starts to turn off ODT resistance. Maximum RTT turn-off time (tAOFPD [MAX]) is the point at which ODT has reached HIGH-Z. tAOFPD (MIN) and tAOFPD (MAX) are measured from ODT being sampled LOW. TABLE 79: ASYNCHRONOUS ODT TIMING PARAMETERS FOR ALL SPEED BINS Symbol Description MIN MAX Units tAONPD tAOFPD Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL off) Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL off) 8.5 8.5 ns ns FIGURE 109 - ASYNCHRONOUS ODT TIMING WITH FAST ODT TRANSITION Notes: 1. AL is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tAONPD (MAX) tAOFPD (MAX) T10 T11 T12 T13 T14 T15 T17T16 CK CK# RTT ODT RTT_NOM Don’t CareTransitioning CKE tIH tIS tIH tIS tAOFPD (MIN)tAONPD (MIN)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 151 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product TABLE 80: ODT PARAMETERS FOR POWER-DOWN (DLL OFF) ENTRY AND EXIT TRANSITION PERIOD Description MIN MAX POWER-DOWN entry transition period (POWER-DOWN entry) POWER-DOWN entry transition (POWER-DOWN exit) ODT to RTT TURN-ON delay (ODTL on = WL - 2) ODT to RTT TURN-OFF delay (ODTL off = WL - 2) tANPD Greater of: tANPD or tRFC - REFRESH to CKE LOW tANPD + tXPDLL WL - 1 (Greater of ODTL off + 1 or ODTL on + 1) Lesser of: tANPD (MIN) [1ns] or ODL on x tCK + tAON (MIN) Lesser of: tAOFPD (MIN) [1ns] or ODL off x tCK + tAOF (MIN) Lesser of: tANPD (MIN) [1ns] or ODL on x tCK + tAON (MIN) Lesser of: tAOFPD (MIN) [1ns] or ODL off x tCK + tAOF (MIN) SYNCHRONOUS TO ASYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN ENTRY) There is a transition period around POWER-DOWN ENTRY (PDE) where the SDRAM’s ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in PRECHARGE POWER-DOWN mode by the setting of MR0[12] = 0. POWE R-DOWN entry begins tANPD prior to CKE first being registered LOW and it ends when CLE is first registered LOW. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. If a REFRESH command has been issued, and it is in progress when CKE goes LOW, POWER-DOWN entry will end tRFC after the REFRESH command rather than when CKE is first registered LOW. POWER-DOWN ENTRY will then become the greater of tANPD and tRFC – REFRESH command to CKE registered LOW. ODT assertion during POWER-DOWN ENTRY results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT de-assertion during POWER-DOWN ENTRY may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 80 summarizes these parameters. If the AL has a large value, the uncertainty of the state of RTT becomes quite large. This is because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL. Figure 110 shows three different cases; ODT_A: Synchronous behavior before • tANPD ODT_B: ODT state changes during the transition period with • tAONPD (MIN) less than ODTL on x tCK + tAON (MIN) and tAONPD (MAX) greater than ODTL on x tCK + tAON (MAX) ODT_C: ODT state changes after the transition period with asynchronous behavior•

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 152 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN EXIT) The SDRAM’s ODT may exhibit either asynchronous or synchronous behavior during POWER-DOWN EXIT (PDX). This transition period occurs if the DLL is selected to be off when in PRECHARGE POWER-DOWN mode by setting MR0[12] to “0”. POWER-DOWN exit begins tANPD prior to CKE first being regis- tered HIGH and it ends tXPDLL after CKE is first registered HIGH. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. The transition period is tANPD plus tXPDLL. ODT assertion during POWER-DOWN exit results in an R TT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT de-assertion during POWER-DOWN EXIT may result in an RTT change as early as the lesser of tAOFPD (MIN) and OFTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 80 summarizes these parameters. If the AL has a large value, the uncertainty of the RTT state becomes quite large. This is because ODTL on and ODTL off are derived from the WL, and the WL is equal to CWL + AL. Figure 111 shows three different cases. ODT C: Asynchronous behavior before • tANPD ODT B: ODT state changes during the transition period with • tAOFPD (MIN) less than ODTL off x tCK + tAOF (MIN) and ODTL off x tCK + tAOF (MAX) greater than tAOFPD (MAX) ODT A: ODT state changes after the transition period with synchronous response• FIGURE 110 - SYNCHRONOUS TO ASYNCHRONOUS TRANSITION DURING PRECHARGE POWER-DOWN (DLL OFF) ENTRY Notes: 1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tAOFPD (MAX) ODTL off T10 T11 T12 T13 Ta0 Ta1 Ta3Ta2 CK CK# DRAM RTT B asynchronous or synchronous RTT_NOM DRAM RTT C asynchronous RTT_NOM Don’t CareTransitioning CKE NOP NOP NOPNOP NOPCommand NOP REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PDE transition period Indicates a Break In Time Scale ODTL off + tAOFPD (MIN) tAOFPD (MAX) tAOFPD (MIN) ODTL off + tAOFPD (MAX) tAOFPD (MIN) tANPD tAOF (MIN) tAOF (MAX) DRAM RTT A synchronous RTT_NOM ODT A synchronous ODT C asynchronous ODT B asynchronous or synchronous tRFC (MIN)

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 153 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 111 - ASYNCHRONOUS TO SYNCHRONOUS TRANSITION DURING PRECHARGE POWER-DOWN (DLL OFF) EXIT Notes: 1. CL = 6; AL = CL - 1; CWL = 5; ODTL off = WL - 2 = 8. T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta 6 Tb0 Tb1 Tb2 Tc0 Tc1 Td0 Td1 Tc2 CK CK# Don’t Care Transitioning ODT C synchronous PON PON NOP COMMAND NOP NOP NOP NOP RTT B asynchronous or synchronous DRAM RTT A asynchronous DRAM RTT C synchronous RTT_NOM NOP NOP ODT B asynchronous or synchronous CKE tAOF (MIN) RTT_NOM Indicates A Break in Time Scale ODTL off + tAOF (MIN) tAOFPD (MAX) ODTL off + tAOF (MAX) tXPDLL tAOF (MAX) ODTL off ODT A asynchronous PDX transition period tAOFPD (MIN) tAOFPD (MAX) tANPD tAOFPD (MIN) RTT_NOM NOP NOP NOP NOP NOP

LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 154 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (SHORT CKE PULSE) If the time in the PRECHARGE POWER DOWN or IDLE states is very short (short CKE LOW pules), the POWER-DOWN ENTRY and POWER-DOWN EXIT transition periods will overlap. When overlap occurs, the response of the SDRAM’s RTT to a change in the ODT state may be synchronous or asynchronous from the start of the POWER-DOWN ENTRY transition period to the end of the POWER-DOWN EXIT transition period even if the ENTRY period ends later than the EXIT period. (see Figure 112). If the time in the idle state is very short (short CKE HIGH pulse), the POWER-DOWN EXIT and POWER-DOWN ENTRY transition periods overlap. When this overlap occurs, the response of the SDRAM’s RTT to a change in the ODT state may be synchronous or asynchronous from the start of the POWER-DOWN EXIT transition period to the end of the POWER-DOWN ENTRY transition period (see Figure 113). FIGURE 112 - TRANSITION PERIOD FOR SHORT CKE LOW CYCLES WITH ENTRY AND EXIT PERIOD OVERLAPPING Notes: 1. AL = 0, WL = 5, tANPD = 4. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4 CK CK# CKE Command Don’t Care Transitioning tXPDLL tRFC (MIN) NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP REF PON PONNOP NOP PDE transition period PDX transition period Indicates a Break in Time Scale tANPD Short CKE LOW transition period (RTT change asynchronous or syn chronous) tANPD FIGURE 113 - TRANSITION PERIOD FOR SHORT CKE HIGH CYCLES WITH ENTRY AND EXIT PERIOD OVERLAPPING Notes: 1. AL = 0, WL = 5, tANPD = 4. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK CK# Command Don’t Care Transitioning NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PON PON NOP NOP NOP tANPD tXPDLL Indicates A Break in Time Scale Ta0 Ta1 Ta2 Ta3 Ta4 CKE S hort CKE HIGH transition period (RTT change asynchronous or synchonous) tANPD

LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant informa- tion before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursu- ant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical compo- nents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 155 PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product

REVISION HISTORY

Revision Engineer Issue Date Description Of Change A 05.19.2009 INITIATEDH/JM