L9D112G80BG4

L9D112G80BG4 LODEV | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 45

Technical content

LOGIC Devices Incorporated www.logicdevices.com 1 Feb 2, 2009 LDS-L9D112G80BG4-C

1.2 Gb, DDR - SDRAM Integrated Module (IMOD)

PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product DDR SDRAM Data Rate = 200, 250, 266, and 333 Mbps Package:

• 25mm x 25mm, Encapsulated Plastic Ball Grid array (PBGA), 219 balls, 1.27mm pitch. 2.5V ±0.2V Core Power supply 2.5V ±0.2V I/O Power supply (SSTL_2 compatible) Differential Clock inputs (CLKx, CLKx\\) Commands entered on each positive CLKx edge Internal pipelined double-data- rate (DDR) Architecture; two data accesses per clock cycle Programmable Burst Length: 2, 4, or 8 Bidirectional data strobe (DQSLx, DQsHx) per byte transmitted/ received with data i.e. source-synchronous data capture

FEATURES

MONOLITHIC SOLUTION IMOD SOLUTION 5 X 265mm/two.numerator = 1328mm/two.numerator PLUS

5 X 66 pins = 320 pins total

625mm/two.numerator

219 Balls/Locations

S A V I N G S O P T I O N S 53% 34% AREA I/O DQS edge-aligned with data for READ; center-aligned with data for WRITE DLL to align DQx and DQSLx, DQSHx transitions with CLKx Four internal banks for concurrent operation One data mask per byte, IMOD con - tains (10) bytes Programmable IOL/IOH Option Auto PRECHARGE option Auto REFRESH and SELF REFRESH Modes Available in INDUSTRIAL, EXTENDED and Mil-Temp ranges Organized as 16M x 72/80 Weight: LOGIC Devices, Inc. L9D112G80BG4 = 2.75 grams typical 53% SPACE savings vs. Monolithic, TSOPII-66 solution Reduced I/O routing (34%) Reduced trace length providing improved/reduced parasitic capaci- tance Impedance matched (60ohm) pack - aging High TCE organic laminate inter - poser Suitable for High Reliability applica - tions Upgradable to 32M x 72/80: L9D125G80BG4 Benefits *Note: This integrated product and/or its specifications are subject to change without notice. Latest document should be retrieved from LDI prior to your design consideration. 22.3 25mm 25mm

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 A DQ0 D Q14 D Q15 VSS V SS A9 A10 A 11 A8 VCCQ VCCQ DQ16 DQ17 DQ31 VSS A B DQ1 D Q2 DQ12 DQ13 VSS V SS A0 A7 A6 A1 VCC V CC DQ18 DQ19 DQ29 DQ30 B C DQ3 D Q4 DQ10 DQ11 VCC V CC A2 A5 A4 A3 VSS VSS DQ20 DQ21 DQ27 DQ28 C D DQ6 D Q5 DQ8 D Q9 VCCQ VCCQ A12 R FU RFU R FU VSS VSS DQ22 DQ23 DQ26 DQ25 D E DQ7 D QML0 VCC DQMH0 DQSH3 DQSL0 D QSH0 BA0 B A1 DQSL1 D QSH1 Vref DQML1 VSS NC DQ24 E F CAS0\\ W E0\\ VCC CLK0 DQSL3 RAS1\\ WE1\\ VSS DQMH1 C LK1 F G CS0\\ RAS0\\ VCC CKE0 CLK0\\ CAS1\\ CS1\\ VSS CLK1\\ C KE1 G H VSS VSS V CC VCCQ VSS VCC VSS VSS V CCQ VCC H J VSS VSS V CC VCCQ VSS VCC VSS VSS V CCQ VCC J K CLK3\\ C KE3 VCC CS3\\ DQSL4 CLK2\\ CKE2 VSS RAS2\\ C S2\\ K L NC CLK3 VCC CAS3\\ R AS3\\ DQSL2 CLK2 VSS WE2\\ CAS2\\ L M DQ56 DQMH3 VCC WE3\\ DQML3 CKE4 DQMH4 C LK4 C AS4\\ W E4\\ R AS4\\ C S4\\ D QMH2 VSS DQML2 DQ39 M N DQ57 DQ58 DQ55 DQ54 DQSH4 C LK4\\ DQ73 DQ72 DQ71 DQ70 DQML4 DQSH2 D Q41 D Q40 D Q37 D Q38 N P DQ60 DQ59 DQ53 DQ52 VSS V SS DQ75 DQ74 DQ69 DQ68 VCC V CC DQ43 DQ42 DQ36 DQ35 P R DQ62 DQ61 DQ51 DQ50 VCC V CC DQ77 DQ76 DQ67 DQ66 VSS VSS DQ45 DQ44 DQ34 DQ33 R T VSS DQ63 DQ49 DQ48 VCCQ VCCQ DQ79 DQ78 DQ65 DQ64 VSS VSS DQ47 DQ46 DQ32 VCC T 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 AddressUNPOPULATED Level REF V + (I/O Power) NC V + (Core Power) CNTRL VSS Data IO L9D112G80BG4, DDR1 SIGNAL LOCATION DIAGRAM

LOGIC Devices Incorporated www.logicdevices.com 3 Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product Fu n c t i o n a l Bl o c k Di a g r a m VCCQ VCC VRef VSS VSS VRef VCC VCCQ A0-A12, BA0-1 A, BA CS0\\ RAS0\\ CAS0\\ CKE0 CLK0 CLK0\\ WE0\\ DQML0 DQMH0 DQSL0 DQSH0 DQ 0 DQ 7 DQ 8 DQ 15 DQ 0 DQ 7 DQ 8 DQ 15 A, BA CS1\\ RAS1\\ CAS1\\ CKE1 CLK1 CLK1\\ WE1\\ DQML1 DQMH1 DQSL1 DQSH1 VSS VRef VCC VCCQ DQ 0 DQ DQ 8 DQ DQ 16 DQ DQ 24 DQ 31 A, BA CS2\\ RAS2\\ CAS2\\ CKE2 CLK2 CLK2\\ WE2\\ DQML2 DQMH2 DQSL2 DQSH2 VSS VRef VCC VCCQ DQ 0 DQ DQ 8 DQ DQ 32 DQ DQ 40 DQ 47 A, BA CS3\\ RAS3\\ CAS3\\ CKE3 CLK3 CLK3\\ WE3\\ DQML3 DQMH3 DQSL3 DQSH3 VSS VRef VCC VCCQ DQ 0 DQ DQ 8 DQ 15 DQ 48 DQ 55 DQ 56 DQ 63 A, BA CS4\\ RAS4\\ CAS4\\ CKE4 CLK4 CLK4\\ WE4\\ DQML4 DQMH4 DQSL4 DQSH4 VSS VRef VCC VCCQ DQ 0 DQ 7 DQ 8 DQ 15 DQ 64 DQ 71 DQ 72 DQ 79

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product Pin/Ba l l lo c a t i o n s/DeFinitions a nD Fu n c t i o n a l De s c r iPt i o n BGA Locations Symbol Type Description F4, F16, G5, G15, K1, K12, L2, L13, N6, M8 G4, G16, K2, K13, M6 G1, G13, K4, K16, M12 F12, G2, K15, L5, M11 F1, G12, L4, L16, M9 F2, F13, L15, M4, M10 E2, E4, E13, F15, M2, M5, M7, M13, M15, N11 E5, E6, E7, E10, E11, F5, K5, L12, N5, N12 E12 A7, A8, A9, A10, B7, B8, B9, B10, C7, C8, C9, C10, D7 E8, E9 CKX,CKX\\ CKEx CSX\\ RASX\\ CASX\\ WEX\\ DQMLX, DQMHX DQSLX, DQSHX Vref A0-A12 BA0, BA1 CNTL. Input CNTL. Input CNTL. Input CNTL. Input CNTL. Input CNTL. Input CNTL. Input Level REF Input Input Clock: CKx and CKx\\ are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CKx and negative edge of CKx\\. Output data (DQ’s and DQS) is referenced to the crossings of the differential clock inputs. Clock Enable: CKE controls the clock inputs. CKE High enables, CKE Low disables the clock input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE is synchronous for POWER-DOWN entry and exit, and for SELF-REFRESH entry CKE is asynchronous for SELF-REFRESH exit and disabling the outputs. CKE must be maintained High throughout READ and WRITE accesses. Input buffers are disabled during POWER-DOWN, input buffers are disabled during SELF-REFRESH. CKE is an SSTL-2 input but will detect an LVCMOS LOW level after VCC is applied. Chip Select: CSx\\ enables the COMMAND register(s) of each of the five (5) integrated words. All commands are masked (registered) HIGH with CSx\\ driven true. CSx\\ provides for external word/bank selection on systems with multiple banks. CSx\\ is considered part of the COMMAND CODE. Row Address Strobe: Command input along with CASx\\ and WEx\\ Column Address Strobe: Command input along with RASx\\ and WEx\\ WRITE (word): Command input along with CASx\\ and RASx\\ Input Data Mask: DQM is an input mask signal for WRITE operations. Input Data is masked when DQML/Hx is sampled HIGH at time of a WRITE access DQML/Hx is sampled on both edges of DQSL/Hx. Data Strobe: Output flag on READ data and Input flag on WRITE data. DQS is edge-aligned with READ data, centered in WRITE data operations. Reference Voltage Address input: Provide the ROW address for ACTIVE commands and the COLUMN address and AUTO PRE-CHARGE bit (A10) for READ/WRITE commands to select one location out of the total array within a selected bank A10 sampled during a PRE-CHARGE command deter- mines whether the PRE-CHARGE applies to one bank or all banks. The address inputs also provide the OP-CODE during a MODE REGISTER SET command. Bank Address input: define which BANK is active during a READ, WRITE, or PRE-CHARGE command.

LOGIC Devices Incorporated www.logicdevices.com 5 Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product Pin/Ba l l lo c a t i o n s/DeFinitions a nD Fu n c t i o n a l De s c r iPt i o n co n t i n u eD BGA Locations Symbol Type Description D8, D9, D10 A2, A3, A4, A13, A14, A15, B1, B2, B3, B4, B13, B14, B15, B16, C1, C2, C3, C4, C13, C14, C15, C16, D1, D2, D3, D4, D13, D14, D15, D16, E1, E16, M1, M16, N1, N2, N3, N4, N7, N8, N9, N10, N13, N14, N15, N16, P1, P2, P3, P4, P7, P8, P9, P10, P13, P14, P15, P16, R1, R2, R3, R4, R7, R8, R9, R10, R13, R14, R15, R16, T2, T3, T4, T7, T8, T9, T10, T13, T14, T15 B11, B12, C5, C6, E3, F3, G3, H3, H12, H16, J3, J12, J16, K3, L3, M3, P11, P12, R5, R6, T16 A11, A12, D5, D6, H4, H15, J4, J15, T5, T6 A5, A6, A16, B5, B6, C11, C12, D11, D12, E14, F14, G14, H1, H2, H5, H13, H14, J1, J2, J5, J13, J14, K14, L14, M14, P5, P6, R11, R12, T1, T11, T12 RFU DQ0-DQ79 VCC VCCQ VSS Input Input/Output Supply Supply Supply Reserved Future Use: Pins reserved for future Address and Bank Select inputs Data I/O Core Power I/O Power Ground (Digital)

LOGIC Devices Incorporated www.logicdevices.com 6 Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product The LOGIC Devices, 1.2Gb, DDR SDRAM IMOD, is one member of its Integrated Module family. This family of Integrated memory modules contains DDR3/DDR2 and DDR device definitions in three package foot - prints including this 25mm2, a 16mm x 22mm package and a 25mm x 32mm footprint. This device, a high speed CMOS random-access, inte - grated memory device based on use of (5) silicon devices each contain - ing 268,435,456 bits. Each chip is internally configured as a quad-bank SDRAM. Each of the chips 67,108,864 bit banks is organized as 8,192 rows by 512 columns by 16bits. Each of the Silicon devices equates to a WORD or DUAL-BYTES, each BYTE containing Data Mask and Data Strobes. The 1.2Gb DDR IMOD uses the double-data-rate (DDR) architecture to achieve high-speed operation. The double-data-rate architecture is a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle via the I/O pins. A single READ or WRITE access for the 1.2Gb DDR IMOD effectively consists of a single 2n-bit wide, one clock cycle transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock cycle data transfers at the DQ (I/O) pins. A bidirectional data strobe (DQSLx, DQSHx) is transmitted externally, along with data, for use in data capture at the end-point receiver. DQSLx, DQSHx are strobes transmitted by the DDR SDRAM during READ opera- tions and by the memory controller during WRITE operations. Each strobe, DQSLx, DQSHx control each of two bytes contained within each of the (5) silicon chips contained in LDI’s IMOD. The 1.2Gb DDR SDRAM operated from a differential clock (CLKx, CLKx\\); the crossing of CLKx going HIGH and CLKx\\ going LOW will be referred to as the positive edge of CLK. Commands (address and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CLK. READ and WRITE accesses to the DDR memory are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR IMOD provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An AUTO-PRECHARGE function may be enabled to provide a self-timed row PRECHARGE that is initiated at the end of the burst access. The pipelined, multi-banked architecture of the DDR SDRAM architecture allows for concurrent operations, therefore providing high effective band - width, by hiding row PRECHARGE and activation time. An AUTO REFRESH mode is provided, along with a power-saving power- down mode. GENERAL DESCRIPTION READ and WRITE accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A12 select the row). The address bits registered coincident with the READ or WRITE com - mand are used to select the starting column location for the burst access. Prior to normal operation, the IMOD must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to V CC and VCCQ simultaneously, and then to VREF (and to the System VTT). VTT must be applied after VCCQ to avoid device latch-up, which may cause permanent damage to the device. V REF can be applied after VCCQ but is expected to be nominally coincident with V TT. Except for CKE, inputs are not recognized as valid until after F REF is applied. CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a READ access). After all power supply and reference voltages are stable, and the clock is stable, the IMOD requires a 200us delay prior to applying an executable command. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP com- mand, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA 1 LOW and BA 0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA 0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO PRECHARGE cycles must be performed (tRFC must be satisfied). Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e. to program operat- ing parameters without resetting the DLL) is required. Following these require- ments, the DDR IMOD is ready for normal operation. FUNCTIONAL DESCRIPTION INITIALIZATION

LOGIC Devices Incorporated www.logicdevices.com 7 Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product The MODE REGISTER is used to define the spe- cific mode of operation of the DDR IMOD. This definition includes the selection of a burst length, a burst type, a CAS latency as shown in Figure 2 and the operating mode, as shown in Figure 3. The MODE REGISTER is programmed via the MODE REGISTER SET command (with BA 0=0 and BA1=0) and will retain the stored information until it is programmed again or the device real - izes a loss of power (except for bit A 8 which is self clearing). Reprogramming the MODE REGISTER will not alter the contents of the memory, provided it is performed correctly. The MODE REGISTER must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. MODE REGISTER bits A 0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A 4-A6 specify the CAS latency, and A7-A12 specify the operating mode. READ and WRITE accesses to the DDR IMOD are burst oriented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility issues with future version may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four and by A 3-Ai when the burst length is set to eight. The remaining (least significant) address bits are used to select the starting location within the block. The pro - grammed burst length applies to both the READ and WRITE bursts. moDe re g i s t e r Bu r s t le n g t h Accesses within a given burst may be pro - grammed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is deter - mined by the burst length, the burst type and the starting column address, as shown in Table 1. Bu r s t t yPe REGISTER DEFINITION Order of Accesses within a Burst Burst Length Starting Column Address Type = Sequential Type = Interleaved A 0 A 1 A0 0 0 0 1 1 0 1 1 A2 A 1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 taBl e 1: Bu r s t DeFinition Notes 1. For a burst length of two, A1-Ai selects a two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai selects a four-data-element block; A0-1 selects the starting column within the block. 3. For a burst length of eight, A3-Ai selects an eight-data-element block; A0-2 selects the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

LOGIC Devices Incorporated www.logicdevices.com 8 Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product The READ latency is the delay in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks. If a READ command is registered at clock edge [n], and the latency is [m] clocks, the data will be available by clock edge [n+m]. Table 2 indi - cates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompat - ibility with future versions may result. READ LATENCY The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A 7-A12, each set to zero, and bits A 0-A6, set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12, each set to zero, bit A8 set to one, and bits A0-A6, set to the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A 7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility from future versions may result. The EXTENDED MODE REGISTER controls functions beyond those controlled by the MODE REGISTER; these additional functions are DLL enable/disable, output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 4. The EXTENDED MODE REGISTER command to the MODE REGISTER (with BA 0=1, BA1=0) and the register will retain the stored information until it is programmed again or the device realizes loss of power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the MODE REGISTER (BA0=BA1=LOW) to reset the DLL. The EXTENDED MODE REGISTER must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. OPERATING MODE EXTENDED MODE REGISTER Table 2 - Ca s la t e n c y Speed CAS Latency = 2 CAS Latency = 2.5 Allowable Operating Frequency (MHz) -10 -75 ≤83 ≤100 ≤125 NA ≤100 ≤125 ≤133 ≤166

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product REGISTER DEFINITION Fi g u r e 1 - moDe re g i s t e r DeFinition Burst Type Sequential Interleaved CAS Latency Reserved Reserved 3 (-5B only) Reserved Reserved 2.5 Reserved Burst lengthCAS LatencyB T0 A9 A7 A6 A5 A4 A3 0A1A2A8A Mode register (Mx) Address bus 9 7 6 5 4 38 2 1 0 Operating mode . . .AnBA0BA1 . . .n1 Operating Mode Normal operation Normal operation/reset DLL All other states reserved . . . Mn M6–M0 Valid Valid Burst Length Reserved Reserved Reserved Reserved Reserved Mode Register Definition Base mode register Extended mode register Reserved Reserved Mn + 2 Note: 1. n is the most significant row address bit Mn + 1 n + 2 n + 1

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product REGISTER DEFINITION Fi g u r e 2 - ca s e la t e n c y Note: BL = 4 in the cases shown; shown with nominal tAC, tDQSCK, and tDQSQ. CK CK# Comman d DQ DQS CL = 2 READ NOP NOP NOP READ NOP NOP NOP CK CK# Comman d DQ DQS CL = 2.5 T0 T1 T2 T2n T 3 T 3n T0 T1 T2 T2n T 3 T 3n Don’tC areTransitioning Data READ NOP NOP NOP CK CK# Comman d DQ DQS CL = 3 T0 T1 T2 T3 T3n

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product REGISTER DEFINITION Fi g u r e 3 - ex t e nDeD moDe re g i s t e r Notes: 1. n is the most significant row address bit. . 2. The reduced drive strength option is available only on Design Revision F and K. 3. The QFC# option is not supported. Operating Mode Reserved Reserved E1, E0 Valid DLL Enable Disable A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Extended mode register (Ex) Address bus 9 7 6 5 4 38 2 1 Drive Strength Normal Reduced E12 Operating Mode . . .AnBA1 BA0 . . .n1n+ 1n+ 2 . . . En DS E23 Mn + 1 Mode Register Definition Base mode register Extended mode register Reserved Reserved Mn + 2 DLL The normal full drive strength for all outputs are specified to be SSTL2, Class II. The DDR IMOD supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environ - ments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54% of the SSTL, Class II drive strength. The DLL must be enabled for normal operation. The DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. When the device exits SELF REFRESH mode, the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. ou tPu t Dr i v e st r e n g t h Dll en aBl e/Di s aBl e

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product REGISTER DEFINITION The TRUTH TABLE (below) provides a quick reference of available commands, followed by a written description of each command. co m m a nDs Name (Function) CSx\\ RASx\\ CASx\\ WEx\\ ADDR Deselect (NOP) No Operation (NOP) ACTIVE (select bank and activate row) READ (select bank and column, and start READ burst) WRITE (select bank and column and start WRITE burst) BURST TERMINATE PRECHARGE (deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (enter soft refresh mode) LOAD MODE REGISTER X X Bank/Row Bank/Column Bank/Column X Code X OP Code 1,9 1,9 1,3 1,4 1,4 1,8 1,5 6,7 1,2 tr u t h taBl e Notes X H H H L L L H L X H H L L H H L L X H L H H H L L L H L L L L L L L L Name (Function) DQMLx, DQMHx DQSLx, DQSHx WRITE ENABLE WRITE INHIBIT 1,10 1,10 tr u t h taBl e - Dm oPe r a t i o n Notes Valid X L H NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-A12 define the op-code to be written to the selected MODE REGISTER BA0, BA1 select either the MODE REGISTER or the EXTENDED MODE REGISTER. 3. A0-A12 provide row addresses, and BA0, BA1 provide bank addresses. 4. A0-A8 provide column address; A10 HIGH enables the AUTO PRECHARGE feature (non-persistent), while A10 LOW disables the AUTO PRECHARGE feature; BA0, BA1 provide bank address. 5. A10 LOW; BA0, BA1 determine the bank being PRECHARGED. A10 HIGH all banks PRECHARGED and BA0, BA1 or “Don’t Care”. 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal REFRESH counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CLE. 8. Applies only to READ bursts with AUTO PRECHARGE disabled. This command is undefined (and should not be used) for READ burst with AUTO PRECHARGE enabled. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask WRITE data; provided coincident with the corresponding data. The DESELECT function (CSx\\=HIGH) prevents new commands from being executed by the DDR IMOD. The IMOD is effectively deselected. Operations already in progress are not affected. De s e l e c t

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product REGISTER DEFINITION The NO OPERATION command is used to perform a NOP to the selected DDR Silicon within the IMOD (CSx\\=LOW). This prevents unwanted com - mands from being registered during idle or wait states. Operations already in progress are not affected. no oPe r a t i o n (noP) The MODE REGISTER is loaded via inputs A0-A12. The LOAD MODE REG- ISTER command can only be issued when all banks idle and a subsequent executable command cannot be issued until tMRD is met. The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA 0, BA1 inputs selects the bank and the address provided on inputs A 0-A12, selects the row. This row remains active (or opens) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. Lo aD moDe re g i s t e r Ac t i v e ac t i v a t i n g a sPe c iFi c ro w in a sPe c iFi c Ba n k CS# WE# CAS# RAS# CKE Address Row HIGH BA0, BA1 Bank CK CK# Don’tCare

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product The READ command is used to initiate a burst READ access to an active row. The value on the BA 0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be PRECHARGED at the end of the READ burst; If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. re aD reaD co m m a nD Note: EN AP = enable auto precharge DISA P=d isable auto precharge. CS# WE# CAS# RAS# CKE Address A10 BA0, BA1 HIGH CK CK# Don’tCare Col DIS AP EN AP Bank

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product The WRITE command is used to initiate a burst WRITE access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A 0-A8 selects the starting column location. The value on the input A 10 determines whether or not AUTO PRECHARGE is used. If AUTO PRE - CHARGE is selected, the row being accessed will be AUTO PRECHARGED at the end of the WRITE burst; If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ lines is written to the memory array subject to DQMLx, DQMHx for each WORD. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte column location. wr i t e write co m m a nD Note: EN AP = enable auto precharge DIS AP =d isable auto precharge.. CS# WE# CAS# RAS# CKE A10 BA0, BA1 HIGH CK CK# Don’tCare Address Col EN AP DIS AP Bank

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank or banks will be available for a subsequent row access a specified time ( tRP) after the PRECHARGE command is issued. Except in the case of concurrent auto PRECHARGE, where a READ or WRITE command to a different bank is allowed as long as it does not violate any other timing parameters. Input A 10 determines whether one or all banks are to be PRECHARGED and in the case where only one bank is to be PRECHARGED, inputs BA 0, BA1 select the bank. In all other cases BA 0, BA1 are treated as “Don’t Care”. Once a bank has been PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of PRECHARGING. Pr e c h a r g e Precharge co m m a nD Note: 1. If A10 is HIGH, bank address becomes “Don’t Care.” CS# WE# CAS# RAS# CKE A10 BA0, BA1 HIGH Address CK CK# Don’tC are Bank1 Allb anks Oneb ank AUTO PRECHARGE is a feature which performs the same individual bank PRECHARGE function described prior, but without requiring an explicit command. This is accomplished by using A 10 to enable the command/function in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/ row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is non-persistent in that it is either enabled or disabled for each individual READ or WRITE command. The device supports concurrent AUTO PRECHARGE if the command to the other bank does not interrupt the data transfer to the current bank. AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. This earliest valid stage is determined as if an explicit PRECHARGE command was issued at the earliest possible time without violating tRAS (MIN). au t o Pr e c h a r g e

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product The BURST TERMINATE command is used to truncate READ bursts. The most recently registered READ command prior to the BURST TER - MINATE command will be truncated. The open page which the READ burst was terminated from, remains open. Bu r s t te r m i n a t e ABs o l u t e ma x i m u m ra t i n g s AUTO REFRESH is used during normal operations of the IMOD and is analogous to CASx\\-BEFORE-RASx\\ (CBR) REFRESH in conventional DRAMs. This command is non-persistent so it must be issued each time a REFRESH is required. The addressing is generated by the internal REFRESH controller. This makes the address bits “Don’t Care” during an AUTO REFRESH com - mand. Each DDR die within the IMOD, requires AUTO REFRESH cycles at an average of 7.8125 us (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute REFRESH interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR die, meaning that the maximum absolute interval between any AUTO REFRESH command is 9 x 7.8125uS (70.3uS). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM die. Although not a JEDEC requirement, to provide for future functionality enhancements, CKEx must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later. Au t o reFr e s h The SELF REFRESH command can be used to retain data in the DDR IMOD even if the rest of the system is powered down. When in the SELF REFRESH mode, the DDR IMOD retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH com- mand except CKEx is disabled (LOW). The DLL is automatically enabled upon entering SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CLEx are “Don’t Care” during SELF REFRESH. The procedure for exiting SELF REFRESH requires a sequence of com - mands. First, CLKx must be stable prior to CKEx going back to HIGH. Once CLEx is HIGH, the DDR die must have a NOP command issued for tXSNR, because time is required for the completion of any internal REFRESH in progress. A simple algorithm for meeting both REFRESH and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. Se lF reFr e s h Parameter MIN MAX UNITS V V V V C mA +3.6V +3.6V +3.6V VCCQ + 0.5V +150 -1.0V -1.0V -1.0V -0.5V -55 VCC Supply Voltage relative to VSS VCCQ I/O Supply Voltage relative to VSS VREF and inputs Voltage relative to VSS I/O pins Voltage relative to VSS Storage Temperature Short circuit current CaPa c i t a n c e Parameter SYMBOL MAX UNITS pF pF pF pF Input Capacitance [CKx\\CKx\\] Addresses, BA0-1 Input Capacitance [All other Input Pins] DQ line Cl1 CA C12 C10

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product Pa c k a g e ou t l i n e Di m e n s i o n s Parameter Symbol MIN TYP MAX UNITS Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage Input High Voltage Input Low Voltage Input Leakage Current: Any input 0V≤VIN≤VCC, VREF pin 0V≤VIN≤1.35V All other pins not under test = 0V Output Leakage Current: DQ lines disabled; 0V≤VOUT≤VCCQ Full Drive Output Option Reduced Drive Output Option Ambient Operating Temperature Industrial = “I” Extended = “E” Mil-Temp = “M” 2.7 2.7 0.51 x VCCQ VREF + 0.04 105 125 V V V V uA uA mA mA mA mA Dc el e c t r i c a l ch a r a c t e r i s t i c s a nD oPe r a t i n g co nDi t i o n s (no t e s 1, 6) 2.5 2.5 0.50 x VCCQ VREF 2.3 2.3 0.49 x VCCQ VREF - 0.04 -16.8 +16.8 -40 -40 -55 VCC VCCQ VREF VTT VIH VIL II IOZ IOH IOL IOH IOL TA TA TA VCC, VCCQ=+2.5V±0.2V;-55°C≤TA≤+125°C

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product Pa c k a g e ou t l i n e Di m e n s i o n s Parameter OPERATING current: One bank active - precharge tCL=tCK(MIN), tRC=tRC(MIN), tRAS=tRAS MIN(ICC); DQ, DQM, DQS inputs changing once per clock cycle; Address and Control inputs changing once every two clock cycles OPERATING current: One bank active - READ - precharge current Active-Read-Precharge; Burst=2; tRC=tRC(MIN); tCK=tCK(MIN); IOUT=0mA; Address and control inputs changing once per clock cycle (notes: 22, 48) Precharge POWER-DOWN current All banks idle; POWER-DOWN mode; tCK=tCK(MIN), CKE=LOW (notes: 23, 32, 50) IDLE STANDBY current CS\\=HIGH; All banks idle; POWER-DOWN mode; tCK=tCK(MIN); CKE=HIGH; Address and other Control inputs changing once per clock cycle; VSS=VREF for DQ, DQS and DM (note: 51) ACTIVE POWER-DOWN, STANDBY current One bank active; POWER-DOWN mode; tCK=tCK(MIN), CKE=LOW (notes: 23, 32, 50) ACTIVE STANDBY current CS\\=HIGH; CKE=HIGH; One bank Active Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DQM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per cycle (note: 22) OPERATING current Burst=2 READS Continuous Burst; One bank active; Address and Control inputs changing once per clock cycle; tCK=tCK(MIN); IOUT=0mA cycle (notes: 22, 48) OPERATING current Burst=2 WRITES Continuous Burst; One bank active; Address and Control inputs changing once per clock cycle; tCK=tCK(MIN); DQ, DQM and DQS inputs changing twice per clock cycle (note: 22) AUTO REFRESH current SELF REFRESH current; CKE=≤0.2V OPERATING current Four bank interleaving READS (BL=4) with AUTO PRECHARGE; tRC=tRC (MIN); tCK=tCK (MIN); Address and Control inputs change only during ACTIVE READ or WRITE commands (notes: 22, 49) 520 650 195 150 200 245 775 1400 1700 mA mA mA mA mA mA mA mA mA mA mA mA icc oPe r a t i n g sPe c iFi c a t i o n l i m i t s a nD co nDi t i o n s (no t e s 1-5, 10, 12, 14) Units 575 700 225 175 225 300 1025 1450 1925 625 775 225 175 225 350 1250 1450 2000 ICC0 ICC1 ICC2P ICC2F ICC3P ICC3N ICC4R ICC4W ICC5 ICC5A ICC6 ICC7 VCC, VCCQ=+2.5V±0.2V;-55°C≤TA≤+125°C 333 Mbps 266/250 Mbps 200 Mbps Symbol @CL=2.5 @CL=2 @CL=2 tREF=tRC (MIN) (notes: 27, 50) tREF=7.8125us (notes: 27, 50) =tRC (MIN)

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product Pa c k a g e ou t l i n e Di m e n s i o n s Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX UNITS Access window of DQs from CLKx / CLKx\\ CLKx High level Width CLKx Low level Width Clock Cycle Time DQ and DM Input Hold Time relative to DQS DQ and DM Input Setup Time relative to DQS DQ and DM Input Pulse Width Access window of DQs from CLKx / CLKx\\ DQS Input HIGH Pulse Width DQS Input LOW Pulse Width DQS-DQ Skew, DQS to last DQ valid, per grp. WRITE command to first DQS latching transition DQS falling edge to CLKx rising - setup time DQS falling edge to CLKx rising - hold time Half Clock period Data-Out HIGH impedance window from CLKx / CLKx\\ Data-Out LOW impedance window from CLKx / CLKx\\ Address and Control Input hold time Address and Control Input setup time Address and Control Input hold time Address and Control Input setup time Load Mode Register DQ-DQS hold. DQS to first DQ to go non-valid Data Hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with AUTO PRECHARGE command ACTIVE to ACTIVE/AUTO REFRESH command per. AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS READ Preamble DQS READ Postamble ACTIVE bank to ACTIVE bank b command DQS WRITE Preamble DQS READ Preamble Setup Time ns tCLK tCLK ns ns ns ns ns ns tCLK tCLK ns tCLK tCLK tCLK ns ns ns ns ns ns ns ms ms ms ns ns ns ns tCLK tCLK ns tCLK ns ac el e c t r i c a l sPe c iFi c a t i o n s a nD re c o m m e nD oPe r a t i n g ch a r a c t e r i s t i c s (no t e s 1-5, 14-17, 33) -6, 333 Mbps -75, 266 [250]Mbps -8, 250 [200]Mbps -10, 200 [167] Mbps

167 MHz, 133 MHz 125 MHz 100 MHz

CLKx CL = 2.5 CLKx CL = 2.5 [2] CLKx CL = 2.5 [2] CLKx CL = 2.5 [2] tAC tCH tCL tCK tCK tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHF tISF tHIS tISS tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRC tRPST tRRD tWPRC tWPRCS -0.7 0.45 0.45 7.5 0.45 0.45 1.75 -0.6 0.35 0.35 0.75 0.2 0.2 tCH,tCL -0.70 0.75 0.75 0.8 0.8 0.9 0.4 0.25 0.7 0.55 0.55 0.6 0.45 1.25 0.7 0.55 70000 1.1 0.6 tHP-tQHS tHP-tQHS tHP-tQHS tHP-tQHS -0.75 0.45 0.45 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 0.75 0.2 0.2 tCH,tCL -0.75 0.9 0.9 0.9 0.4 0.25 0.75 0.55 0.55 0.75 0.5 1.25 0.75 0.75 120000 1.1 0.6 -0.8 0.45 0.45 0.6 0.6 -0.8 0.35 0.35 0.75 0.2 0.2 tCH,tCL -0.8 1.1 1.1 1.1 1.1 0.9 0.4 0.25 0.8 0.55 0.55 0.8 0.6 1.25 0.8 120000 1.1 0.6 -0.8 0.45 0.45 -0.8 0.35 0.35 0.75 0.2 0.2 tCH,tCL -0.8 1.1 1.1 1.1 1.1 0.9 0.4 0.25 0.8 0.55 0.55 0.6 0.6 0.8 0.6 1.25 0.8 120000 1.1 0.6 CL=2.5 CL=2

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product Pa c k a g e ou t l i n e Di m e n s i o n s Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX UNITS DQS WRITE Postamble WRITE Recovery Time Internal WRITE to READ command delay Data Valid Output Window REFRESH to REFRESH command Interval (Industrial) REFRESH to REFRESH command Interval (Extended) REFRESH to REFRESH command Interval (Mil-Temp) Average Periodic REFRESH Interval (Industrial) Average Periodic REFRESH Interval (Extended) Average Periodic REFRESH Interval (Mil-Temp) Terminating delay reference to VDD Exit Self REFRESH to non-READ Command Exit Self REFRESH to READ Command ac el e c t r i c a l sPe c iFi c a t i o n s a nD re c o m m e nD oPe r a t i n g ch a r a c t e r i s t i c s (no t e s 1-5, 14-17, 33) -6, 333 Mbps -75, 266 [250]Mbps -8, 250 [200]Mbps -10, 200 [167] Mbps CLKx CL = 2.5 CLKx CL = 2.5 [2] CLKx CL = 2.5 [2] CLKx CL = 2.5 [2] tWPST tWR tWTR na tREFC tREFC tREFC tREFI tREFI tREFI tVTD tXSNR tXSRD 0.4 200 70.3 7.8 3.9 5.9 3.9 tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ 0.4 200 70.3 7.8 5.9 3.9 0.4 200 0.6 70.3 7.8 5.9 3.9 0.4 200 0.6 70.3 7.8 5.9 3.9 tCLK ns tCLK us us us us us us us ns ns tCLK

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product ac sPe c iFi c a t i o n no t e s 1.All voltages referenced to VSS 2.Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related speci - fications and the device operation are guaranteed for the full voltage range specified. 3. Outputs (except for IDD measurements) measured with equivalent load: Output (VOUT) Reference point 50Ω VTT 30pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to V REF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the spec- ified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1 V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 standard (that is, the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. All speeds may not be offered on all device grades. Refer to “Ordering Information” for availability. 7. VREF is expected to equal V DDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on V REF may not exceed ±2% of the DC value. Thus, from V DDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. 8. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, it is expected to be set equal to VREF, and it must track variations in the DC level of VREF. 9. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 10. The value of VIX and VMP is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 11. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle times. 12. Enables on-chip refresh and address counters. 13. IDD specifications are tested after the device is properly initialized and is averaged at the defined cycle rate. VREF = V SS, f = 100MHz, T A= 25°C, V OUT(DC) = V DDQ/2, V OUT (peak-to- peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an addi- tional 50ps per each 100 mV/ns reduction in slew rate from the 500 mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. 16. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 17. Inputs are not recognized as valid until V REF stabilizes. Once initialized, including self refresh mode, V REF must be powered within specified range. Exception: during the period before V REF stabilizes, CKE < 0.3 × V DD is recognized as LOW. 18. The output timing reference level, as measured at the timing reference point (indicated in Note 3), is VTT. 19. tHZ and tLZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (High-Z) or begins driving (Low-Z). 20. The intent of the “Don’t Care” state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above V IH[DC] MIN) then it must not transition LOW (below VIH[DC] prior to tDQSH [MIN]). 21. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 22. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previ - ous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 23. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for I DD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 24. The refresh period is 64ms. This equates to an average refresh rate of 7.8125μs (15.625μs for 128Mb DDR). However, an AUTO REFRESH command must be asserted at least once every 70.3μs (140.6μs for 128Mb DDR); burst refreshing or posting by the DRAM controller greater than 8 REFRESH cycles is not allowed. 25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 26. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, because functionality is uncertain when operating beyond a 45/55 ratio. 27. Referenced to each output group: x4 = DQS with DQ 0–DQ3; x8 = DQS with DQ0–DQ7; x16 = LDQS with DQ0–DQ7 and UDQS with DQ8–DQ15. 28. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during the REFRESH command period (tRFC [MIN]), else CKE is LOW (that is, during standby).

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product ac sPe c iFi c a t i o n no t e s 29. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 30. The input capacitance per pin group will not differ by more than this maxi- mum amount for any given device. 31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially). 32. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be der - ated: 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. 33. VDD must not vary more than 4% if CKE is not active while any bank is active. 34. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 35. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK and CK# inputs, collectively, during bank active. 36. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal PRECHARGE com - mand being issued. 37. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either –300mV or 2.2V, whichever is more positive. The average cannot be below the +2.5V minimum. 38. Normal output drive curves: a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 4. b. The driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 4. c. The full driver pull-up current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 5. d. The driver pull-up current variation within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 5. e. The full ratio variation of MAX to MIN pull-up and pull-down current should be between 0.71 and 1.4 for drain-to-source voltages from 0.1V to 1.0V at the same voltage and temperature. f. The full ratio variation of the nominal pull-up to pull-down current should be unity ±10% for device drain-to-source voltages from 0.1V to 1.0V. 39. Reduced output drive curves: a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 6. b. The driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 6. c. The full driver pull-up current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 7. d. The driver pull-up current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 7. e. The full ratio variation of the MAX-to-MIN pull-up and pull- down current should be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V at the same voltage and temperature. Fi g u r e 4 - Fu l l Dr i v e Pu l l-Do w n ch a r a c t e r i s t i c s 100 120 140 160 IOUT (mA) VOUT (V) Fi g u r e 5 - Fu l l Dr i v e Pu l l-uP ch a r a c t e r i s t i c s -200 -180 -160 -140 -120 -100 -8 0 -6 0 -4 0 -2 0 IOUT (mA) VDDQ - VOUT (V)

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product ac sPe c iFi c a t i o n no t e s f. The full ratio variation of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0V. 40. The voltage levels used are derived from a minimum V DD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 41. VIH overshoot: VIH (MAX) = V DDQ + 1.5V for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = –1.5V for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle rate. 42. VDD and VDDQ must track each other. 43. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 44. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST) or begins driving (tRPRE). 45. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, V TT may be 1.35V maximum during power-up, even if VDD/VDDQ are 0V, provided a minimum of 42Ω of series resistance is used between the VTT supply and the input pin. 46. The current LDI part operates below 83 MHz (slowest specified JEDEC operating frequency). As such, future die may not reflect this option. 47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 48. Random address is changing; 50% of data is changing at every transfer. 49. Random address is changing; 100% of data is changing at every trans - fer. 50. CKE must be active (HIGH) during the entire time a REFRESH com - mand is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. 51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although I DD2F, IDD2N, and I DD2Q are similar, IDD2F is “worst case.” 52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ com - mand. 53. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV. 54. The -6 speed grades will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. Fi g u r e 6 - reDu c eD Dr i v e Pu l l-Do w n ch a r a c t e r i s t i c s IOUT (mA) VOUT (V) Fi g u r e 7 - reDu c eD Dr i v e Pu l l-uP ch a r a c t e r i s t i c s -80 -70 -60 -50 -40 -30 -20 -10 IOUT (mA) VDDQ - VOUT (V)

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 8 - re aD Bu r s t Notes: 1. DO n = data-out from column n. 2. BL = 4. 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Shown with nominal tAC, tDQSCK, and tDQSQ. READ NOP NOP NOP NOP NOP READ NOP NOP NOP NOP NOP CL = 2 CL = 2.5 DO n DO n T0 T1 T2 T3T2n T 3n T4 T5 T0 T1 T2 T3T2n T 3n T4 T5 READ NOP NOP NOP NOP NOP CL = 3 DO n T0 T1 T2 T3 T4nT3n T 4 T 5 Bank a, Col n Bank a, Col n Bank a, Col n Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Transitioning Data Don’t Care AC Switching diagrams reference 16 bits, LDI’s IMOD contains (5) 16 bit devices totaling 80 bits

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 9 - co n s e c u t i v e re aD Bu r s t Notes: 1. DO n (or b) = data-out from column n (or column b). 2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts the first). 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Three (or seven) subsequent elements of data-out appear in the programmed order follow- ing DO b. 5. Shown with nominal tAC, tDQSCK, and tDQSQ. 6. Example applies only when READ commands are issued to same device. READ NOP READ NOP NOP NOP READ NOP READ NOP NOP NOP CL = 2 CL = 2.5 DO n DO b DO n DO b T0 T1 T2 T3T2n T3n T 4 T 5T4n T 5n T0 T1 T2 T3T2n T 3n T4 T5T4n T 5n READ NOP READ NOP NOP NOP CL = 3 DO n DO b T0 T1 T2 T3 T3n T 4 T 5T4n T 5n Bank, Col n Bank, Col b Bank, Col n Bank, Col b Bank, Col n Bank, Col b Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Transitioning Data Don’t Care

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 10 - no n c o n s e c u t i v e re aD Bu r s t Notes: 1. DO n (or b) = data-out from column n (or column b). 2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts the first). 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Three (or seven) subsequent elements of data-out appear in the programmed order follow- ing DO b. 5. Shown with nominal tAC, tDQSCK, and tDQSQ. READ NOP NOP NOP NOP NOPREAD CL = 2 CL = 2.5 DO n T0 T1 T2 T3T2n T 3n T4 T5 T5n T 6 READ NOP NOP NOP NOP NOPREAD T0 T1 T2 T3T2n T 3n T4 T5 T5n T 6 DO b DO n DO b CL = 3 READ NOP NOP NOP NOP NOPREAD T0 T1 T2 T3 T3n T 4 T 5 T 6 DO n DO b T4n Bank, Coln Bank, Colb Bank, Coln Bank, Colb Bank, Coln Bank, Colb Comman d Address DQS DQ CK# CK Comman d Address DQS DQ CK# CK Comman d Address DQS DQ CK# CK Transitioning Data Don’tC are

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 11 - ra nDo m re aD ac c e s s e s Notes: 1. DO n (or x or b or g) = data-out from column n (or column x (or column b or column g). 2. BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous). 3. n',x ', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively. 4. READs are to an active row in any bank . 5. Shown with nominal tAC, tDQSCK, and tDQSQ. READ READ READ NOP NOPREAD CL = 2 CL = 2.5 DO n DO DO g DO DO b DO x DO DO n DO DO DO b DO x DO T0 T1 T2 T3T2n T3n T 4 T 5T4n T 5n READ READ READ NOP NOPREAD T0 T1 T2 T3T2n T3n T4 T5T4n T 5n CL = 3 DO n DO DO DO b DO x DO READ READ READ NOP NOPREAD T0 T1 T2 T3 T3n T 4 T 5T4n T5n Bank, Coln Bank, Colb Bank, Colx Bank, Colg Bank, Coln Bank, Colb Bank, Colx Bank, Colg Bank, Coln Bank, Colb Bank, Colx Bank, Colg Comman d Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Transitioning Data Don’tC are

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 12 - te r m i n a t i n g a re aD Bu r s t Notes: 1 . Page remains open. 2. DO n = data-out from column n. 3. BL = 4. 5. Shown with nominal tAC, tDQSCK, and tDQSQ. READ NOP NOP NOP NOP Bank a, Col n READ NOP NOP NOP NOP Bank a, Col n CL = 2 CL = 2.5 DO n DO n T0 T1 T2 T3T2n T 4 T 5 T0 T1 T2 T3T2n T 4 T 5 READ NOP NOP NOP NOP Bank a, Col n CL = 3 DO n T0 T1 T2 T3 T3n T 4 T 5 BST1 BST1 BST1 Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Transitioning Data Don’t Care 4. Subseqent element of data-out appears in the programmed order following DO n.

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 13 - re aD t o wr i t e Notes: 1 . Page remains open. 2. DO n = data-out from column n; DI b = data-in from column b. 3. BL = 4 (applies for bursts of 8 as well; if BL = 2, the BURST command shown can be NOP). 4. One subsequent element of data-out appears in the programmed order following DO n. 5. Data-in elements are applied following DI b in the programmed order. 6. Shown with nominal tAC, tDQSCK, and tDQSQ. READ BST1 NOP NOP NOP Bank, Coln WRITE Bank, Colb T0 T1 T2 T3T2n T 4 T 5T4n T 5n t (NOM) DQSS DI b READ BST1 NOP WRITE NOP Bank a, Col n NOP T0 T1 T2 T3 T3n T 4 T 5 T 5n DO n DO n t (NOM) DQSS READ NOP NOP Bank, Coln WRITE Bank, Colb T0 T1 T2 T3T2n T 4 T 5 T 5n t (NOM) DQSS DI b DO n NOP CL = 2.5 CL = 2 T3n CL = 3 DI b BST1 Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Transitioning Data Don’tC are DM DM DM

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 14 - re aD t o Pr e c h a r g e Notes: 1 . Provided tRAS (MIN) is met, a READ command with auto precharge enabled would cause a precharge to be performed at x number of clock cycles after the READ command, where x= BL/2. 2. DO n = data-out from column n. 3. BL = 4 or an interrupted burst of 8. 4. Three subsequent elements of data-out appear in the programmed order following DO n. 5. Shown with nominal tAC, tDQSCK, and tDQSQ. 6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also assumed that tRAS (MIN) is met. 7. An ACTIVE command to the same bank is only allowed if tRC (MIN) is met. READ NOP PRE NOP NOP ACT Bank a, Coln Bank a, (a or all) Bank a, Row READ NOP PRE NOP NOP ACT Bank a, Coln CL = 2 tRP tRPCL = 2.5 DO n DO n T0 T1 T2 T3T2n T 3n T4 T5 T0 T1 T2 T3T2n T 3n T4 T5 Bank a, (a or all) Bank a, Row READ NOP PRE NOP NOP ACT Bank a, Coln tRPCL = 3 DO n T0 T1 T2 T3 T4nT3n T 4 T 5 Bank a, (a or all) Bank a, Row Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Transitioning Data Don’tC are

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 15 - Ba n k re aD wi t h o u t Pr e c h a r g e Notes: 1 . NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4. 3. The PRECHARGE command can only be applied at T5 if tRAS (MIN) is met. 4. Disable auto precharge. 5. “Don’t Care” if A10 is HIGH at T5. 6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in the programmed order. CK CK# CKE A10 BA0, BA1 tCK tCH tCL tIS tIS tIH tIS tIS tIH tIH tIH tIS tIH tRCD tRC tRP CL = 2 DM T0 T1 T2 T3 T4 T5 T5n T 6nT6 T7 T8 DQS Case 1: tAC (MIN) and tDQSCK(MIN) Case 2: tAC (MAX) and tDQSCK(MAX) DQS tRPRE tRPRE tRPST tRPST tDQSCK(MIN) tLZ (MIN) tAC (MIN)tLZ (MIN) DO n tHZ (MAX)tAC (MAX) DO n ACT Coln Bankx Bank x ACT Bankx tDQSCK (MAX) NOP1 NOP1 NOP1 NOP1 NOP1READ2 PRE3 Bank x5 tRAS3 Row Row Row Row DQ DQ Command Address Transitioning Data Don’t Care All banks One bank

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 16 - Da t a ou tPu t timing – tDQsQ, tQh, a nD Da t a va l iD wi nDo w Notes: 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 2. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transition, and ends with the last valid DQ transition. 3. DQ transitioning after DQS transition define the tDQSQ window. LDQS defines the lower byte, and UDQS defines the upper byte. 4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 5. tQH is derived from tHP: tQH = tHP - tQHS. 6. The data valid window is derived for each DQS transition and is tQH - tDQSQ. 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15. DQ (last data valid)4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 LDQS3 DQ (last data valid)4 DQ (first data no longer vali d)4 DQ (first data no longer valid)4 DQ0–DQ7 and LDQS Collectively6 T2n T2n T2n T3n T3n T3n CK CK# 4T3T2T1T n3Tn2T tQH5 tQH5 tDQSQ 2 Data valid window DQ (last data valid)7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 UDQS3 DQ (last data valid)7 DQ (first data no longer vali d)7 DQ (first data no longer vali d)7 DQ8–DQ15 and UDQS Collectively6 T2n T2n T2n T3n T3n T3n tQH5 tQH5 tQH5 tQH5 tHP1 tHP1 tHP1 tHP1tHP1tHP1 tQH5tQH5 Upperbyte Lowerbyte tDQSQ 2 tDQSQ 2 tDQSQ 2 tDQSQ 2 tDQSQ 2 tDQSQ 2 tDQSQ 2 Data valid window Data valid window Data valid window Data valid window Data valid window Data valid window Data valid window

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 17 - Da t a ou tPu t timing - tac a nD tDQsck Notes: 1 . R EAD command with CL = 2 issued at T0. 2. tDQSCK is the DQS output window relative to CK and is the “long term” component of the DQS skew. 3. DQ transitioning after DQS transition define the tDQSQ window. 4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC. 5. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew. 6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions. 7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions. CK CK# DQS or LDQS/UDQS3 T1 T2 T3 T4 T5T2n T3n T 4n T5n T6 tRPST tLZ (MIN) tDQSCK2 (MAX) tDQSCK2 (MIN) tDQSCK2 (MAX) tDQSCK 2 (MIN) tHZ (MAX) All DQ values collectively 4 tAC5 (MIN) tAC5 (MAX)tLZ (MIN) tHZ (MAX) T2n T 3n T4n T 5n T2n T2n T3n T3n T4n T4n T5n T5n T2 T3 T4 T5 T3DQ (last data valid) DQ (first data valid) T01 tRPRE

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 18 - wr i t e Bu r s t Notes: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. A10 is LOW with the WRITE command (auto precharge is disabled). DQS tDQSS (MAX) tDQSS (NOM) tDQSS (MIN) tDQSS DM DQ CK CK# Command WRITE NOP NOP Address Bank a, Col b NOP T0 T1 T2 T3T2n DQS tDQSS DM DQ DQS DM DQ DI b DI b DI b Don’t CareTransitioning Data tDQSS

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 19 - co n s e c u t i v e wr i t e t o wr i t e Notes: 1. DI b (or n) = data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. Three subsequent elements of data-in are applied in the programmed order following DI n. 4. An uninterrupted burst of 4 is shown. 5. Each WRITE command may be to any bank. Address tDQSS (NOM) CK CK# Command PONPONETIRWPONETIRW Bank, Col b NOP Bank, Col n T0 T1 T2 T3 5T4Tn2T T 4nT3nT1n DQ DQS DM DI n DI b Don’t CareTransitioning Data tDQSS

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 20 - no n c o n s e c u t i v e wr i t e t o wr i t e Notes: 1. DI b (or n) = data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. Three subsequent elements of data-in are applied in the programmed order following DI n. 4. An uninterrupted burst of 4 is shown. 5. Each WRITE command may be to any bank. CK Command PONPONPONPONETIRW Address Bank, Colb WRITE Bank, Col n T0 T1 T2 T3 5T4Tn2T T 4n n5Tn1T DQ DQS DM DI n DI b tDQSS (NOM) tDQSS Don’t CareTransitioning Data CK# Fi g u r e 21 - ra nDo m wr i t e cy c l e s Notes: 1. DI b (or x or no r a or g) = data-in from column b (or column x, or column n, or column a, or column g). 2. b' , x', n' , a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g, respectively. 3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown. 4. Each WRITE command may be to any bank. tDQSS (NOM) CK CK# Command PONWRITE Address Bank, Colb Bank, Colx Bank, Coln Bank, Colg WRITE Bank, Col a T0 T1 T2 T3 5T4Tn2T T 4n n5Tn3Tn1T DQ DQS DM DI b DI DI x DI DI n DI DI a DI DI g DI Don’t CareTransitioning Data WRITE WRITE WRITE

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 22 - wr i t e t o re aD un i n t e r r uPt eD Notes: 1. DI b = data-in for column b; DO n = data-out for column n. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. tWTR is referenced from the first positive CK edge after the last data-in pair. 5. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to different devices, in which case tWTR is not required, and the READ command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). tDQSS (NOM) CK CK# Command PONPONDAERPONPONETIRW Address Bank a, Col b Bank a, Col n NOP T0 T1 T2 T3T2n T4 T5T1n T6 T6n tWTR CL = 2 DQ DQS DM DI b DO n tDQSStDQSS (MIN) CL = 2 DQ DQS DM DI b DO n tDQSStDQSS (MAX) CL = 2 DQ DQS DM DI b DO n tDQSS Don’t CareTransitioning Data

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 23 - wr i t e t o re aD in t e r r uPt i n g Notes: 1. DI b = data-in for column b; DO n = data-out for column n. 2. An interrupted burst of 4 is shown; two data elements are written. 3. One subsequent element of data-in is applied in the programmed order following DI b. 4. tWTR is referenced from the first positive CK edge after the last data-in pair. 5. A10 is LOW with the WRITE command (auto precharge is disabled). 6. DQS is required at T2 and T2n (nominal case) to register DM. 7. If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ command will not mask these two data elements. tDQSS (NOM) CK CK# Command WRITE NOP NOP NOP NOP NOP Address Bank a, Col b Bank a, Coln READ T0 T1 T2 T3T2n T4 T5 T5nT1n T6 T6n tWTR CL = 2 DQ DQS DM DI b DO n tDQSS (MIN) CL = 2 DQ DQS DM DI b tDQSS (MAX) CL = 2 DQ DQS DM DI b DO n DO n Don’t CareTransitioning Data tDQSS tDQSS tDQSS T3n

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 24 - wr i t e t o re aD, oD D nu mBe r oF Da t a, in t e r r uPt i n g Notes: 1. DI b = data-in for column b; DO n = data-out for column n. 2. An interrupted burst of 4 is shown; one data element is written. 3. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements). 4. A10 is LOW with the WRITE command (auto precharge is disabled). 5. DQS is required at T1n, T2, and T2n (nominal case) to register DM. 6. If the burst of 8 is used, DM and DQS are required at T3–T3n because the READ command will not mask these data elements. tDQSS (NOM) CK CK# Command PONPONPONPONPONETIRW Address Bank a, Col b Bank a, Coln READ T0 T1 T2 T3 5T4Tn2TT1n T6 T6nT5n tWTR CL = 2 DQ DQS DM DI b DO n tDQSS (MIN) CL = 2 DQ DQS DM DI b DO n tDQSS (MAX) CL = 2 DQ DQS DM DI b DO n Don’t CareTransitioning Data tDQSS tDQSS tDQSS T3n

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 25 - wr i t e t o Pr e c h a r g e - un i n t e r r uPt eD Notes: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. tWR is referenced from the first positive CK edge after the last data-in pair. 5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). tDQSS (NOM) CK CK# Command WRITE NOP NOP NOP NOP Address Bank a, Col b Bank, (a or all) NOP T0 T1 T2 T3 5T4Tn2TT1n T6 tWR tRP DQ DQS DM DI b tDQSS (MIN) DQ DQS DM DI b tDQSS (MAX) DQ DQS DM DI b Don’t CareTransitioning Data tDQSS tDQSS tDQSS PRE

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 26 - wr i t e t o Pr e c h a r g e - in t e r r uPt i n g Notes: 1. DI b = data-in for column b. 2. Subsequent element of data-in is applied in the programmed order following DI b. 3. An interrupted burst of 8 is shown; two data elements are written. 4. tWR is referenced from the first positive CK edge after the last data-in pair. 5. A10 is LOW with the WRITE command (auto precharge is disabled). 6. DQS is required at T4 and T4n (nominal case) to register DM. 7. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n. tDQSStDQSS (NOM) CK CK# Command WRITE NOP NOP NOP NOP Address Bank a, Col b Bank, (a or all) NOP T0 T1 T2 T3 5T4Tn2TT1n T6 tWR tRP DQ DQS DM DI b tDQSStDQSS (MIN) DQ DQS DM DI b tDQSStDQSS (MAX) DQ DQS DM DI b Don’t CareTransitioning Data T3n T4n PRE

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product AC SWITCHING DIAGRAMS Fi g u r e 27 - Da t a inPu t timing Notes: 1 . WRITE command issued at T0. 2. tDSH (MIN) generally occurs during tDQSS (MIN). 3. tDSS (MIN) generally occurs during tDQSS (MAX). 4. For x16, LDQS controls the lower byte and UDQS controls the upper byte. 5. DI b = data-in from column b. T01 tDSH2 tDSH2tDSS3 tDSS3 DI b DQS tDQSS tDQSH tWPST tDHtDS tDQSL DM DQ CK CK# T1 T1n T2 T2n T3 Don’t CareTransitioning Data tWPREtWPRES

LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product 1.27 ± 0.10 1.27 ± 0.10 19.05 ± 0.10 SQ 0.60 ± 0.04 2.35 ± 0.15 219 X 0.76 ± 0.05 25 ± 0.15 25 ± 0.15 1.75 ± 0.11 8.89 ± 0.10 SQ me c h a n i c a l Dr a w i n g

LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant informa- tion before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursu- ant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical compo- nents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. LOGIC Devices Incorporated www.logicdevices.com Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L9D112G80BG4 High Performance, Integrated Memory Module Product Pa c k a g e ou t l i n e Di m e n s i o n s Part Number Core FREQ. Data Transfer Rate Package Grade L9D112G80BG4I6 L9D112G80BG4E6 L9D112G80BG4M6 L9D112G80BG4I75 L9D112G80BG4E75 L9D112G80BG4M75 L9D112G80BG4I8 L9D112G80BG4E8 L9D112G80BG4M8 L9D112G80BG4I10 L9D112G80BG4E10 L9D112G80BG4M10 orDe r i n g inFo r m a t i o n

166 MHz

133 MHz

125 MHz

100 MHz

333 Mbps

266 Mbps

250 Mbps

200 MHz

re v i s i o n hi s t o r y Revision Engineer Issue Date Description Of Change A B C 11/7/2008 01/21/2009 02/02/2009 INITIATE Pgs 1, 45: Change all incidences of “LBGA” to “PBGA”, revise wording to Plastic Ball Grid Array Pgs 4,5: Revision to include ball E12, Vref in Pin/Ball Locations/Definitions Section Pg 8 : Changes to allowable frequency parameters (CAS =2) in CAS latency table (speed -10 changes from ≤75 to ≤83, -75 changes from ≤100 to ≤125, -6 changes from ≤133 to NA) Pg 19: Revise CL parameter (333 Mbps: change CL from 2 to 2.5) Pg 20, 21: AC chart specs changes for 167 MHz, correct tLZ min. from -0.07 to -0.70 Pg 44: Correction to mechanical drawing DH/JM DH/JM CM/JM