L8C201

L8C201 LODEV | Alldatasheet

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512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products READ POINTER RAM ARRAY 512 x 9-bit 1K x 9-bit 2K x 9-bit 4K x 9-bit WRITE POINTER DATA OUTPUTS DATA INPUTS D 8-0 Q 8-0 THREE-STATE BUFFERS EXPANSION LOGIC WRITE CONTROL READ CONTROL FLAG LOGIC RESET LOGIC W R XI XO/HF FF EF FL/RT RS ❑ ❑❑ ❑❑ First-In/First-Out (FIFO) using Dual-Port Memory ❑ ❑❑ ❑❑ Advanced CMOS Technology ❑ ❑❑ ❑❑ High Speed — to 10 ns Access Time ❑ ❑❑ ❑❑ Asynchronous and Simultaneous Read and Write ❑ ❑❑ ❑❑ Fully Expandable by both Word Depth and/or Bit Width ❑ ❑❑ ❑❑ Empty and Full Warning Flags ❑ ❑❑ ❑❑ Half-Full Flag Capability ❑ ❑❑ ❑❑ Auto Retransmit Capability ❑ ❑❑ ❑❑ Package Styles Available:

• 28-pin Plastic DIP
• 32-pin Plastic LCC
• 28-pin Ceramic Flatpack FEATURES DESCRIPTION L8C201/202/203/204 512/1K/2K/4K x 9-bit Asynchronous FIFODEVICES INCORPORATED The L8C201, L8C202, L8C203, and L8C204 are dual-port First-In/First- Out (FIFO) memories. The FIFO memory products are organized as: L8C201 — 512 x 9-bit L8C202 — 1024 x 9-bit L8C203 — 2048 x 9-bit L8C204 — 4096 x 9-bit Each device utilizes a special algorithm that loads and empties data on a first- in/first-out basis. Full and Empty flags are provided to prevent data overflow and underflow. Three additional pins are also provided to allow for unlimited expansion in both word size and depth. Depth Expansion does not result in a flow-through penalty. Multiple devices are connected with the data and control signals in parallel. The active device is determined by the Expansion In (XI) and Expansion Out (XO) signals which are daisy chained from device to device. The read and write operations are internally sequential through the use of ring pointers. No address informa- tion is required to load and unload data. The write operation occurs when the Write (W) signal is LOW. Read occurs when Read (R) goes LOW. The nine data outputs go to the high impedance state when R is HIGH. Retransmit (RT) capability allows for reset of the read pointer when RT is pulsed LOW, allowing for retransmission of data from the beginning. Read Enable (R) and Write Enable (W) must both be HIGH during a retransmit cycle, and then R is used to access the data. A Half-Full (HF) output flag is available in the single device and width expansion modes. In the depth expansion configuration, this pin provides the Expansion Out (XO) information which is used to tell the next FIFO that it will be activated. These FIFOs are designed to have the fastest data access possible. Even in lower cycle time applications, faster access time can eliminate timing bottlenecks as well as leave enough margin to allow the use of the devices without external bus drivers. The FIFOs are designed for those applications requiring asychronous and simultaneous read/writes in multiprocessing and rate buffer applications. L8C201/202/203/204 BLOCK DIAGRAM

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products “final” read cycle but inhibiting further read operations with the data outputs remaining in a high imped- ance state. Once a valid write operat- ing has been accomplished, the Empty Flag (EF) will go HIGH after tWHEH and a valid read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO. FL/RT — First Load/Retransmit This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). The FIFOs can be made to retransmit data when the Retransmit Enable control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than the full memory has been written between resets. Retransmit will affect the Half-Full Flag (HF), depend- ing on the relative locations of the read and write pointers. The retransmit feature is not compatible with the Depth Expansion Mode. XI — Expansion In This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. D 8-0 — Data Input Data input signals for 9-bit wide data. Data has setup and hold time require- ments with respect to the rising edge of W. SIGNAL DEFINITIONS Inputs RS — Reset Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown (i.e., tWHSH before the rising edge of RS) and should not change until tSHWL after the rising edge of RS. Hall-Full Flag (HF) will be reset to high after Reset (RS). W — Write Enable A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data setup and hold time must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRHFH, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. R — Read Enable A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First- Out basis, independent of any ongo- ing write operation. After Read Enable (R) goes HIGH, the Data Outputs (D 8-0) will return to a high impedance condition until the next read operation. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the Outputs FF — Full Flag The Full Flag (FF) will go LOW, inhibiting further write operations, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go LOW after 512 writes for the L8C201, 1024 writes for the L8C202, 2048 writes for the L8C203, and 4096 writes for the L8C204. EF — Empty Flag The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. XO/HF — Expansion Out/Half-Full Flag This is a dual-purpose output. In the Single Device Mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is then deasserted by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the daisy chain by providing a pulse to the next device when the previous device reaches the last location of memory. Q 8-0 — Data Output Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read Enable (R) is in a HIGH state or the device is empty. OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e., all must be set to generate the correct composite FF or EF). 5. The Retransmit (RT) function and Half-Full Flag (HF) are not avail- able in the Depth Expansion Mode. Bidirectional Mode Applications which require data buffering between two systems (each system capable of read and write operations) can be achieved by pairing FIFOs. Care must be taken to assure that the appropriate flag is monitored by each system (i.e., FF is monitored on the device when W is used; EF is monitored on the device when R is used). Both Depth Expansion and Width Expansion may be used in this mode. OPERATING MODES Single Device Mode A single FIFO may be used when the application requirements are for the number of words in a single device. The FIFOs are in a Single Device Configuration when the Expansion In (XI) control input is grounded. In this mode the Half-Full Flag (HF), which is an active-low output, is the active function of the combination pin XO/ HF. Width Expansion Mode Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF, and HF) can be detected from any one device. Any word width can be attained by adding additional FIFOs. Flag detection is accomplished by monitoring the FF, EF, and HF signals on either (any) device used in the width expansion configuration. Do not connect any output signals together. Depth Expansion (Daisy Chain) Mode The FIFOs can easily be adapted to applications where the requirements are for greater than the number of words in a single device. Any depth can be attained by adding additional FIFOs. The FIFOs operates in the Depth Expansion configuration when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device with the last device connect- ing back to the first. OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products L8C201/202/203/204 Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = 4.5 V, IOH = –2.0 mA 2.4 V VOL Output Low Voltage VCC = 4.5 V, IOL = 8.0 mA 0.4 V VIH Input High Voltage 2.0 VCC V +0.3 VIL Input Low Voltage (Note 3) –0.5 0.8 V IIX Input Leakage Current Ground ≤ VIN ≤ VCC ±1 µA IOZ Output Leakage Current R ≥ VIH, GND ≤ VOUT ≤ VCC ±10 µA ICC2 VCC Current, TTL Inactive All Inputs = VIH MIN (Note 6) 15 mA ICC3 VCC Current, CMOS Standby All Inputs = VCC (Note 12) 5m A C IN Input Capacitance Ambient Temp = 25°C, VCC = 4.5 V 5 pF C OUT Output Capacitance Test Frequency = 1 MHz (Note 9) 7p F M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2) O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.5 V ≤ VCC ≤ 5.5 V Active Operation, Industrial –40°C to +85°C 4.5 V ≤ VCC ≤ 5.5 V Active Operation, Military –55°C to +125°C 4.5 V ≤ VCC ≤ 5.5 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5) L8C201/202/203/204- Symbol Parameter Test Condition 40 30 25 20 15 12 10 Unit ICC1 VCC Current, Active (Note 5) 90 95 100 110 120 150 180 mAOBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products L8C201/202/203/204– 25 15 12 10 Symbol Parameter Min Max Min Max Min Max Min Max tRLRL Read Cycle Time (MHz) 35 25 20 15 tRLQV Read Low to Output Valid (Access Time) 25 15 12 10 tRHRL Read High to Read Low (Notes 8, 9) 10 10 8 5 tRLRH Read Low to End of Read Cycle (Notes 8, 9) 25 15 12 10 tRHQV Read High to Output Valid 5 5 5 5 tRHQZ Read High to Output High Z (Note 14) 20 15 15 15 tWLWL Write Cycle Time (Note 9) 35 25 20 15 tWLWH Write Low to Write High (Notes 8, 9) 25 15 12 10 tWHWL Write High to End of Write Cycle (Notes 8, 9) 10 10 8 5 tDVWH Data Valid to Write High (Notes 8, 9) 15 10 8 8 tWHDX Write High to Data Change (Notes 8, 9) 0000 tSLSH Reset Cycle Time (Notes 9, 10) 25 15 12 10 tSLWL Reset Low to Write Low (Notes 9, 10) 35 25 20 15 tWHSH Write High to Reset High (Notes 9, 10) 25 15 12 10 tRHSH Read High to Reset High (Notes 9, 10) 25 15 12 10 tSHWL Reset High to Write Low (Notes 9, 10) 10 10 8 5 tSLEL Reset Low to Empty Flag Low 25 15 12 10 tSLHH Reset Low to Half-Full Flag High 25 15 12 10 tSLFH Reset Low to Full Flag High 25 15 12 10 SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range A SYNCHRONOUS AND RESET TIMING (ns) A SYNCHRONOUS READ AND WRITE OPERATION tRLQV R tRLRL tRLQV tRLRH tRHRL tRHQV tRHQZ tDVWH tWHDX tWLWH tWLWL tWHWL DATA-IN VALID DATA-IN VALID DATA-OUT VALIDDATA-OUT VALID W Q 8-0 D 8-0 R ESET TIMING tSLSH W tSLEL tSLHH , tSLFH tSLWL tWHSH tRHSH tSHWL RS R EF HF, FF OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range L8C201/202/203/204– 25 15 12 10 Symbol Parameter Min Max Min Max Min Max Min Max tRLQV Read Low to Output Valid (Access Time) 25 15 12 10 tRLEL Read Low to Empty Flag Low 25 15 12 10 tRHFH Read High to Full Flag High 25 15 12 10 tWHEH Write High to Empty Flag High 25 15 12 10 tWLFL Write Low to Full Flag Low 25 15 12 10 tTLAL Retransmit Cycle Time 35 25 20 15 tTLTH Retransmit Low to End of Retransmit Cycle (Notes 8, 9, 10) 25 15 12 10 tAHTH Read/Write High to Retransmit High (Notes 8, 9, 10) 25 15 12 10 tTHAL Retransmit High to Read/Write Low (Note 9) 10 10 8 5 FULL /EMPTY FLAG AND RETRANSMIT TIMING (ns) R ETRANSMIT FULL FLAG FROM LAST WRITE TO FIRST READ R tWLFL W tRHFH FF LAST WRITE IGNORED WRITE FIRST READ ADDITIONAL READS ADDITIONAL WRITES EMPTY FLAG FROM LAST READ TO FIRST WRITE R tRLEL W tWHEH EF LAST READ IGNORED READ FIRST WRITE ADDITIONAL WRITES FIRST READ VALID tRLQV DATA OUT VALID FLAG VALID tAHTH W, R tTLTH tTLAL tTHAL RT HF, EF, FF OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range L8C201/202/203/204– 25 15 12 10 Symbol Parameter Min Max Min Max Min Max Min Max tRHFH Read High to Full Flag High 25 15 12 10 tEHRH Read Pulse Width After Empty Flag High 25 15 12 10 tRHHH Read High to Half-Full Flag High 25 15 12 10 tWHEH Write High to Empty Flag High 25 15 12 10 tWLHL Write Low to Half-Full Flag Low 25 15 12 10 tFHWH Write Pulse Width After Full Flag High (Note 9) 25 15 12 10 FULL /HALF -FULL /EMPTY FLAG TIMING (ns) EMPTY FLAG TIMING FULL FLAG TIMING FF tRHFH W tFHWH R H ALF -FULL FLAG TIMING R tWLHL W HF HALF-FULL OR LESS MORE THAN HALF-FULL tRHHH HALF-FULL OR LESS EF tWHEH W tEHRH R OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range L8C201/202/203/204– 25 15 12 10 Symbol Parameter Min Max Min Max Min Max Min Max tALOL Read/Write to Expansion Out Low (Note 11) 25 15 12 12 tAHOH Read/Write to Expansion Out High (Note 11) 25 15 12 12 tXLXH Expansion In Pulse Width (Notes 9, 11) 25 15 12 10 tXHXL Expansion In High to Expansion In Low (Notes 9, 11) 10 10 10 10 tALXL Read/Write Low to Expansion In Low (Notes 9, 11) 15 12 8 8 EXPANSION TIMING (ns) EXPANSION OUT R W XO WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION tALOL tAHOH tALOL tAHOH EXPANSION IN R W WRITE TO FIRST PHYSICAL LOCATION READ FROM FIRST PHYSICAL LOCATION tALXL tALXL XI tXLXH tXHXL OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products L8C201/202/203/204– 40 30 20 Symbol Parameter Min Max Min Max Min Max tRLRL Read Cycle Time (MHz) 50 40 30 tRLQV Read Low to Output Valid (Access Time) 40 30 20 tRHRL Read High to Read Low (Notes 8, 9) 10 10 10 tRLRH Read Low to End of Read Cycle (Notes 8, 9) 40 30 20 tRHQV Read High to Output Valid 555 tRHQZ Read High to Output High Z (Note 14) 25 20 15 tWLWL Write Cycle Time (Note 9) 50 40 30 tWLWH Write Low to Write High (Notes 8, 9) 40 30 20 tWHWL Write High to End of Write Cycle (Notes 8, 9) 10 10 10 tDVWH Data Valid to Write High (Notes 8, 9) 20 18 12 tWHDX Write High to Data Change (Notes 8, 9) 000 tSLSH Reset Cycle Time (Notes 9, 10) 40 30 20 tSLWL Reset Low to Write Low (Notes 9, 10) 50 40 30 tWHSH Write High to Reset High (Notes 9, 10) 40 30 20 tRHSH Read High to Reset High (Notes 9, 10) 40 30 20 tSHWL Reset High to Write Low (Notes 9, 10) 10 10 10 tSLEL Reset Low to Empty Flag Low 50 40 30 tSLHH Reset Low to Half-Full Flag High 50 40 30 tSLFH Reset Low to Full Flag High 50 40 30 SWITCHING CHARACTERISTICS Over Military Operating Range A SYNCHRONOUS AND RESET TIMING (ns) A SYNCHRONOUS READ AND WRITE OPERATION tRLQV R tRLRL tRLQV tRLRH tRHRL tRHQV tRHQZ tDVWH tWHDX tWLWH tWLWL tWHWL DATA-IN VALID DATA-IN VALID DATA-OUT VALIDDATA-OUT VALID W Q 8-0 D 8-0 R ESET TIMING tSLSH W tSLEL tSLHH , tSLFH tSLWL tWHSH tRHSH tSHWL RS R EF HF, FF OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products SWITCHING CHARACTERISTICS Over Military Operating Range L8C201/202/203/204– 40 30 20 Symbol Parameter Min Max Min Max Min Max tRLQV Read Low to Output Valid (Access Time) 40 30 20 tRLEL Read Low to Empty Flag Low 30 30 20 tRHFH Read High to Full Flag High 35 30 20 tWHEH Write High to Empty Flag High 35 30 20 tWLFL Write Low to Full Flag Low 35 30 20 tTLAL Retransmit Cycle Time 50 40 30 tTLTH Retransmit Low to End of Retransmit Cycle (Notes 8, 9, 10) 40 30 20 tAHTH Read/Write High to Retransmit High (Notes 8, 9, 10) 40 30 20 tTHAL Retransmit High to Read/Write Low (Note 9) 10 10 10 FULL /EMPTY FLAG AND RETRANSMIT TIMING (ns) R ETRANSMIT FULL FLAG FROM LAST WRITE TO FIRST READ R tWLFL W tRHFH FF LAST WRITE IGNORED WRITE FIRST READ ADDITIONAL READS ADDITIONAL WRITES EMPTY FLAG FROM LAST READ TO FIRST WRITE R tRLEL W tWHEH EF LAST READ IGNORED READ FIRST WRITE ADDITIONAL WRITES FIRST READ VALID tRLQV DATA OUT VALID FLAG VALID tAHTH W, R tTLTH tTLAL tTHAL RT HF, EF, FF OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products SWITCHING CHARACTERISTICS Over Military Operating Range L8C201/202/203/204– 40 30 20 Symbol Parameter Min Max Min Max Min Max tRHFH Read High to Full Flag High 35 30 20 tEHRH Read Pulse Width After Empty Flag High 40 30 20 tRHHH Read High to Half-Full Flag High 50 40 30 tWHEH Write High to Empty Flag High 35 30 20 tWLHL Write Low to Half-Full Flag Low 50 40 30 tFHWH Write Pulse Width After Full Flag High (Note 9) 40 30 20 FULL /HALF -FULL /EMPTY FLAG TIMING (ns) EMPTY FLAG TIMING FULL FLAG TIMING FF tRHFH W tFHWH R H ALF -FULL FLAG TIMING R tWLHL W HF HALF-FULL OR LESS MORE THAN HALF-FULL tRHHH HALF-FULL OR LESS EF tWHEH W tEHRH R OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products SWITCHING CHARACTERISTICS Over Military Operating Range L8C201/202/203/204– 40 30 20 Symbol Parameter Min Max Min Max Min Max tALOL Read/Write to Expansion Out Low (Note 11) 40 30 20 tAHOH Read/Write to Expansion Out High (Note 11) 40 30 20 tXLXH Expansion In Pulse Width (Notes 9, 11) 40 30 20 tXHXL Expansion In High to Expansion In Low (Notes 9, 11) 10 10 10 tALXL Read/Write Low to Expansion In Low (Notes 9, 11) 10 10 10 EXPANSION TIMING (ns) EXPANSION OUT R W XO WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION tALOL tAHOH tALOL tAHOH EXPANSION IN R W WRITE TO FIRST PHYSICAL LOCATION READ FROM FIRST PHYSICAL LOCATION tALXL tALXL XI tXLXH tXHXL OBSOLETE

FIGURE 1. FIFO MEMORY (DEPTH EXPANSION ) BLOCK DIAGRAM TABLE 1. RESET AND RETRANSMIT (SINGLE DEVICE CONFIGURATION /WIDTH EXPANSION MODE ) TABLE 2. RESET AND FIRST LOAD TRUTH TABLE (DEPTH EXPANSION /COMPOUND EXPANSION MODE )

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products 0°C to +70°C — COMMERCIAL SCREENING –40°C to +85°C — COMMERCIAL SCREENING L8C201 — ORDERING INFORMATION 28-pin — 0.3" wide 28-pin — 0.6" wide W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R Speed 25 ns 15 ns 12 ns 10 ns 25 ns 15 ns 12 ns 10 ns Plastic DIP (P10) L8C201PC25 L8C201PC15 L8C201PC12 L8C201PC10 L8C201PI25 L8C201PI15 L8C201PI12 L8C201PI10 Plastic DIP (P9) L8C201NC25 L8C201NC15 L8C201NC12 L8C201NC10 L8C201NI25 L8C201NI15 L8C201NI12 L8C201NI10 OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products Speed 25 ns 15 ns 12 ns 10 ns 25 ns 15 ns 12 ns 10 ns 40 ns 30 ns 20 ns 40 ns 30 ns 20 ns –40°C to +85°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT 0°C to +70°C — COMMERCIAL SCREENING 32-pin — 0.490" x 0.590" 31134 201914 15 17 Top View D 2 D 1 D 0 XI FF Q 0 Q 1 NC Q 2 D 6 D 7 NC FL/RT RS EF XO/HF Q Q 6 Q 3 Q 8 GND NC R Q 4 Q 5 D 3 D 8 W NC V CC D 4 D 5 L8C201 — ORDERING INFORMATION Plastic J-Lead Chip Carrier (J6) L8C201JC25 L8C201JC15 L8C201JC12 L8C201JC10 L8C201JI25 L8C201JI15 L8C201JI12 L8C201JI10 W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R Ceramic Flatpack (M2) L8C201MM40 L8C201MM30 L8C201MM20 L8C201MMB40 L8C201MMB30 L8C201MMB20 28-pin OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products 28-pin — 0.3" wide 28-pin — 0.6" wide W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R L8C202 — ORDERING INFORMATION 0°C to +70°C — COMMERCIAL SCREENING –40°C to +85°C — COMMERCIAL SCREENING Plastic DIP (P10) L8C202PC25 L8C202PC15 L8C202PC12 L8C202PC10 L8C202PI25 L8C202PI15 L8C202PI12 L8C202PI10 Speed 25 ns 15 ns 12 ns 10 ns 25 ns 15 ns 12 ns 10 ns Plastic DIP (P9) L8C202NC25 L8C202NC15 L8C202NC12 L8C202NC10 L8C202NI25 L8C202NI15 L8C202NI12 L8C202NI10 OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products Speed 25 ns 15 ns 12 ns 10 ns 25 ns 15 ns 12 ns 10 ns 40 ns 30 ns 20 ns 40 ns 30 ns 20 ns –40°C to +85°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT 0°C to +70°C — COMMERCIAL SCREENING 32-pin — 0.490" x 0.590" 31134 201914 15 17 Top View D 2 D 1 D 0 XI FF Q 0 Q 1 NC Q 2 D 6 D 7 NC FL/RT RS EF XO/HF Q Q 6 Q 3 Q 8 GND NC R Q 4 Q 5 D 3 D 8 W NC V CC D 4 D 5 L8C202 — ORDERING INFORMATION Plastic J-Lead Chip Carrier (J6) L8C202JC25 L8C202JC15 L8C202JC12 L8C202JC10 L8C202JI25 L8C202JI15 L8C202JI12 L8C202JI10 W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R Ceramic Flatpack (M2) L8C202MM40 L8C202MM30 L8C202MM20 L8C202MMB40 L8C202MMB30 L8C202MMB20 28-pin OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products 28-pin — 0.3" wide 28-pin — 0.6" wide W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R L8C203 — ORDERING INFORMATION 0°C to +70°C — COMMERCIAL SCREENING –40°C to +85°C — COMMERCIAL SCREENING Plastic DIP (P10) L8C203PC25 L8C203PC15 L8C203PC12 L8C203PC10 L8C203PI25 L8C203PI15 L8C203PI12 L8C203PI10 Speed 25 ns 15 ns 12 ns 10 ns 25 ns 15 ns 12 ns 10 ns Plastic DIP (P9) L8C203NC25 L8C203NC15 L8C203NC12 L8C203NC10 L8C203NI25 L8C203NI15 L8C203NI12 L8C203NI10 OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products Speed 25 ns 15 ns 12 ns 10 ns 25 ns 15 ns 12 ns 10 ns 40 ns 30 ns 20 ns 40 ns 30 ns 20 ns –40°C to +85°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT 0°C to +70°C — COMMERCIAL SCREENING 32-pin — 0.490" x 0.590" 31134 201914 15 17 Top View D 2 D 1 D 0 XI FF Q 0 Q 1 NC Q 2 D 6 D 7 NC FL/RT RS EF XO/HF Q Q 6 Q 3 Q 8 GND NC R Q 4 Q 5 D 3 D 8 W NC V CC D 4 D 5 L8C203 — ORDERING INFORMATION Plastic J-Lead Chip Carrier (J6) L8C203JC25 L8C203JC15 L8C203JC12 L8C203JC10 L8C203JI25 L8C203JI15 L8C203JI12 L8C203JI10 W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R Ceramic Flatpack (M2) L8C203MM40 L8C203MM30 L8C203MM20 L8C203MMB40 L8C203MMB30 L8C203MMB20 28-pin OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products 0°C to +70°C — COMMERCIAL SCREENING –40°C to +85°C — COMMERCIAL SCREENING 28-pin — 0.3" wide 28-pin — 0.6" wide W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R L8C204 — ORDERING INFORMATION Plastic DIP (P10) L8C204PC25 L8C204PC15 L8C204PC12 L8C204PC10 L8C204PI25 L8C204PI15 L8C204PI12 L8C204PI10 Speed 25 ns 15 ns 12 ns 10 ns 25 ns 15 ns 12 ns 10 ns Plastic DIP (P9) L8C204NC25 L8C204NC15 L8C204NC12 L8C204NC10 L8C204NI25 L8C204NI15 L8C204NI12 L8C204NI10 OBSOLETE

512/1K/2K/4K x 9-bit Asynchronous FIFO FIFO Products Speed 25 ns 15 ns 12 ns 10 ns 25 ns 15 ns 12 ns 10 ns 40 ns 30 ns 20 ns 40 ns 30 ns 20 ns –40°C to +85°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT 0°C to +70°C — COMMERCIAL SCREENING 32-pin — 0.490" x 0.590" 31134 201914 15 17 Top View D 2 D 1 D 0 XI FF Q 0 Q 1 NC Q 2 D 6 D 7 NC FL/RT RS EF XO/HF Q Q 6 Q 3 Q 8 GND NC R Q 4 Q 5 D 3 D 8 W NC V CC D 4 D 5 L8C204 — ORDERING INFORMATION Plastic J-Lead Chip Carrier (J6) L8C204JC25 L8C204JC15 L8C204JC12 L8C204JC10 L8C204JI25 L8C204JI15 L8C204JI12 L8C204JI10 W D 8 D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 GND VCC D 4 D 5 D 6 D 7 FL/RT RS EF XO/HF Q Q 6 Q 5 Q 4 R Ceramic Flatpack (M2) L8C204MM40 L8C204MM30 L8C204MM20 L8C204MMB40 L8C204MMB30 L8C204MMB20 28-pin OBSOLETE