L7C108

L7C108 LODEV | Alldatasheet

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A A11 OE A CE DQ DQ7 DQ6 DQ5 DQ4 NC A16 A14 A12 DQ1 DQ2 DQ3 VSS VCC A15 CE2 WE A A11 OE A10 CE DQ8 DQ7 DQ6 DQ5 DQ4 Top View 14 19 20 4 3231 2 15 16 17 18 DQ1 WE A13 A11 OE A10 CE1 DQ8 NC V CC A16 NC DQ2 DQ3 VSS DQ4 DQ5 DQ6 DQ7 LOGIC Devices Incorporated www.logicdevices.com 1 Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 128K x 8 Static RAM with Chip Select Powerdown, Output Enable and Single or Dual Chip Selects High Speed — to 15 ns maximum Operational Power, -L Version Active: 140 mA at 15 ns Standby: 1 mA max Data Retention at 2 V for Battery Backup Operation Screened to MIL-STD-883, Class B or to SMD 5962-89598 Package Styles Available: x 32-pin Ceramic 400mil DIP D12 x 32-pin Ceramic LCC K11 x 32-pin Ceramic SO- x 32-pin 4uad Ceramic LCC KA1 Pin ConfigurationFEATURES 32-pin Ceramic DIP 32-pin Ceramic SOJ 32-pin Quad CLCC 32-pin Ceramic LCC The L7C108 and L7C109 are high-perfor- mance, low-power CMOS static RAMs. The storage circuitry is organized as 131,072 words by 8 bits per word. The

8 Data In and Data Out signals share I/O

pins. The L7C108 has a single active- low Chip Enable. The L7C109 has two Chip Enables one active-low . These devices are available in three speeds with maximum access times from 15 ns to 45 ns. Inputs and outputs are TTL compatible. Operation is from a single +5 V power supply. Power consumption is 140 mA -L Version at 15 ns. Data may be retained in inactive storage with a supply voltage as low as 2 V. The L7C108 and L7C109 provide asyn- chronous unclocked operation with matching access and cycle times. The Chip Enables and a three-state I/O bus with a separate Output Enable control simplify the connection of several chips for increased storage capacity. Memory locations are specified on address pins A 0 through A 16. For the L7C108, reading from a designated location is accomplished by present- ing an address and driving CE 1 and OE LOW while WE remains HIGH. For the L7C109, CE 1 and OE must be LOW while CE2 and WE are HIGH.The data in the addressed memory location will then appear on the Data Out pins within one access time. The output pins stay in a high-impedance state when CE 1 or OE is HIGH, or CE2 L7C109 or WE is LOW. Writing to an addressed location is accomplished when the active-low CE and WE inputs are both LOW, and CE 2 L7C109 is HIGH. Any of these signals may be used to terminate the write oper- ation. Data In and Data Out signals have the same polarity. Latchup and static discharge protection are provided on-chip. The L7C108 and L7C109 can withstand an injection cur- rent of up to 200 mA on any pin without damage. OVERVIEW

LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 ROW SELECT WE ROW ADDRESS I/O7 - 0 COLUMN SELECT & COLUMN SENSECONTROL COLUMN ADDRESS CE1 OE CE2 (L7C109 only)

128 K x 8

Mode OE CE1 CE2* WE DQ POWER Standby Standby Standby Standby Read Read Write TRUTH TABLE * Note: for L7C109 only X X X X L H X t V IH X t VCC - 0.2 V X L L L X d V IL X d GND + 0.2 V H H H X X X X H H L High - Z High - Z High - Z High - Z High - Z D

LOGIC Devices Incorporated www.logicdevices.com 3 Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 Supply Voltage 4.5 V d VCC d 5.5 V 2.0 V d VCC d 5.5 V Mode Active, Operation, Military Data Retention, Military OPERATING CONDITIONS To meet specified electrical and switching characteristics Temperature Range (Ambient) -55°C to +125°C -55°C to +125°C MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2) -65°C to +150°C -55°C to +125°C -0.5 V to +7.0 V -3.0 V to +7.0 V -3.0 V to +7.0 V 25 mA >200 mA L7C108/109 L7C108/109-L Symbol Parameter Test Condition Min Max Min Max Unit VOH VOL VIH VIL IIx IOZ ICC2 ICC3 ICC4 CIN COUT Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current V CC Current, TTL Standby VCC Current, CMOS Standby VCC Current, Data Retention Input Capacitance Output Capacitance VCC = 4.5V, IOH = -4 mA IOL = 8 mA Note 3 GND < VIN < VCC Note 4 Note 7 Note 8 VCC = 2 V Notes 9, 10 Ambient Temp = 25°C, VCC = 5 V Test FreTuency = 1 MHz Note 10 2.4 2.2 -0.5 -10 -10 0.4 Vcc +0.5 0.8 +10 +10 ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5) 2.4 2.2 -3.0 -10 -10 0.4 Vcc +0.3 0.8 +10 +10 0.75 V V V V μA μA mA mA mA pF pF Symbol Parameter Test Condition L7C108/109-L ICC1 VCC Current, Active Note 6 mA L7C108/109 140 140 140 135 125 140 140 140 130 125 Unit

LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 SWITCHING CHARACTERISTICS Over Operating Range READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 READ CYCLE - ADDRESS CONTROLLED Notes 13, 14 DATA OUT tAVAV tPU tPD tELQV HIGH IMPEDANCE CE OE tELQX tGLQV tGLQX DATA VALID Icc 50% 50% tGHQZ tEHQZ HIGH IMPEDANCE READ CYCLE - CE/OE CONTROLLED NOTES 13, 15 ADDRESS DATA OUT PREVIOUS DATA VALID ICC tAVAV tPU tAVQX tPD tAVQV DATA VALID Symbol Parameter Read Cycle Time Address Valid to Output Valid Notes 13, 14 Address Change to Output Change Chip Enable Low to Output Valid Notes 13, 15 Chip Enable Low to Output Low Z Notes 20, 21 Chip Enable High to Output High Z Notes 20, 21 Output Enable Low to Output Valid Output Enable Low to Output Low Z Notes 20, 21 Output Enable High to Output High Z Notes 20, 21 Input Transition to Power Up Notes 10, 19 tAVAV tAV4V tAV4X tEL4V tEL4X tEH4Z tGL4V tGL4X tGH4Z tPU Min Max Min Max Min Max Min Max Min Max

LOGIC Devices Incorporated www.logicdevices.com 5 Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 SWITCHING CHARACTERISTICS Over Operating Range READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 Symbol Parameter tPD tCDR Operation Recovery Time Notes 10, 19 Chip Enable High to Data Retention Note 10 DATA RETENTION MODE VCC tCDR 4.5 V4.5 V ≥ 2 V CE VIH tPD VIH DATA RETENTION Notes 9, 10 WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns) L7C108/109 Symbol Parameter Write Cycle Time Chip Enable Low to End of Write Cycle Address Valid to Beginning of Write Cycle Address Setup to End of Write Cycle Address Hold After End Of Write Write Enable Pulse Width Low Data Setup to End of Write Cycle Data Hold to End of Write Write Enable High to Output Low Z Notes 20, 21 Write Enable Low to Output High Z Notes 20, 21 tAVAV tELWH tAVWL tAVWH tWHAX tWLWH tDVWH tWHDX tWH4X tWL4Z Min Min Min Min Min Max Max Max Max Max Min Min Min Min Min Max Max Max Max Max

LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 SWITCHING CHARACTERISTICS Over Operating Range WRITE CYCLE - WE CONTROLLED Notes 16, 17, 18, 19 WRITE CYCLE - CE CONTROLLED Notes 16, 17, 18, 19

LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109

PACKAGE INFORMATION

0.825 ± 0.008 PIN 1 IDENTIFIER 0.400 ± 0.005 See detail A 0.025 ± 0.003

0.050 TYP

0.085 ± 0.008 0.006 ~ 0.22 TYP 0.003 ~ 0.015 detail A 0.070 ± 0.007 0.055 ± 0.006 0.082 ± 0.0083 PKG K: 32L CERAMIC DUAL LCC (MD-K11) *All measurements in inchesSMD 5962-89598 Case ‘U’ / Ordering Code ‘K’

LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 0.400 ± 0.005 0.300 ± 0.005 0.550 0.450 See detail A 0.085 ± 0.008 + 0.008 - 0.005 0.025 ± 0.003 0.050 ± 0.005 0.008R 0.020 ± 0.002 0.065 ± 0.006 + 0.10 - 0.05 0.0821 ± 0.0073 PKG KA: 32L CERAMIC QUAD LCC (MD-KA1) *All measurements in inchesSMD 5962-89598 Case ‘M’ / Ordering Code “KA”

LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 0.132 ± 0.0203 0.750 ± 0.007

0.050 BSC

0.012 ± 0.0013

0.005 TYP

0.822 ± 0.008

0.445 MAX

0.425 ± 0.006 CHAMFER

0.020 REF

0.370 ± 0.010 0.035R TYP

0.010 REF

0.005 MIN

0.038 TYP

0.025 REF

0.075 REF

0.035 ± 0.010 0.0205 ± 0.091 0.025 ± 0.003 TYP 0.017 ± 0.002 PKG Y: 32L CERAMIC SOJ (MD-Y1) *All measurements in inchesSMD 5962-89598 Case ‘Y’ and ‘7’ / Ordering Code ‘Y’ (Note: Case ‘Y’ ships for Case ‘7’ as compatible replacement)

LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 0.05 ± 0.07750.135 ± 0.005 1.600 ± 0.016 0.018 ± 0.002 0.050 ± 0.002 TYP 0.170 ± 0.005 0.22 ± 0.015 0.050 ± 0.0100.378 ± 0.005 0.400 ± 0.005 0.010 Base Plane Seating Plane Lead Location Guage Plane 0.100 ± 0.05 TYP + 0.002 - 0.001 0.1471 ± 0.0063 0.317 ± 0.011 PKG D: 32L CERAMIC DIP (MD-D12) *All measurements in inchesSMD 5962-89598 Case ‘Z’ / Ordering Code ‘D’

L7C109DMB45 5962-8959835MZA L7C108DMB45 5962-8959827MZA L7C109DMB35 5962-8959836MZA L7C108DMB35 5962-8959828MZA L7C109DMB25 5962-8959837MZA L7C108DMB25 5962-8959829MZA L7C109DMB20 5962-8959838MZA L7C108DMB20 5962-8959839MZA L7C109DMB15 5962-8959841MZA L7C108DMB15 5962-8959844MZA L7C109YMB45 5962-8959835M7A L7C108YMB45 5962-8959827M7A L7C109YMB35 5962-8959836M7A L7C108YMB35 5962-8959828M7A L7C109YMB25 5962-8959837M7A L7C108YMB25 5962-8959829M7A L7C109YMB20 5962-8959838M7A L7C108YMB20 5962-8959839M7A L7C109YMB15 5962-8959841M7A L7C108YMB15 5962-8959844M7A L7C109YMB45 5962-8959835MYA L7C108YMB45 5962-8959827MYA L7C109YMB35 5962-8959836MYA L7C108YMB35 5962-8959828MYA L7C109YMB25 5962-8959837MYA L7C108YMB25 5962-8959829MYA L7C109YMB20 5962-8959838MYA L7C108YMB20 5962-8959839MYA L7C109YMB15 5962-8959841MYA L7C108YMB15 5962-8959844MYA L7C109KAMB45 5962-8959835MMA L7C109KAMB35 5962-8959836MMA L7C109KAMB25 5962-8959837MMA L7C109KAMB20 5962-8959838MMA L7C109KAMB15 5962-8959841MMA L7C109KMB45 5962-8959835MUA L7C109KMB35 5962-8959836MUA L7C109KMB25 5962-8959837MUA L7C109KMB20 5962-8959838MUA L7C109KMB15 5962-8959841MUA LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 SMD Cross Reference Table LOGIC Part # LOGIC Part #SMD Part # SMD Part #

LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 SMD Cross Reference Table LOGIC Part # LOGIC Part #SMD Part # SMD Part # L7C109DMB45L 5962-8959818MZA L7C108YMB45L 5962-8959810M7A L7C109DMB35L 5962-8959819MZA L7C108YMB35L 5962-8959811M7A L7C109DMB25L 5962-8959820MZA L7C108YMB25L 5962-8959812M7A L7C109DMB20L 5962-8959821MZA L7C108YMB20L 5962-8959840M7A L7C109YMB45L 5962-8959818M7A L7C108YMB15L 5962-8959848M7A L7C109YMB35L 5962-8959819M7A L7C108YAMB45L 5962-8959810MYA L7C109YMB25L 5962-8959820M7A L7C108YMB35L 5962-8959811MYA L7C109YMB20L 5962-8959821M7A L7C108YMB25L 5962-8959812MYA L7C109YMB45L 5962-8959818MYA L7C108YMB20L 5962-8959840MYA L7C109YMB35L 5962-8959819MYA L7C108YMB15L 5962-8959848MYA L7C109YMB25L 5962-8959820MYA L7C109YMB20L 5962-8959821MYA L7C109KAMB45L 5962-8959818MMA L7C109KAMB35L 5962-8959819MMA L7C109KAMB25L 5962-8959820MMA L7C109KAMB20L 5962-8959821MMA L7C109KMB45L 5962-8959818MUA L7C109KMB35L 5962-8959819MUA L7C109KMB25L 5962-8959820MUA L7C109KMB20L 5962-8959821MUA L7C109FMB20L 5962-8959821MTA L7C108DMB45L 5962-8959810MZA L7C108DMB35L 5962-8959811MZA L7C108DMB25L 5962-8959812MZA L7C108DMB20L 5962-8959840MZA L7C108DMB15L 5962-8959848MZA

Indicates a LOGIC Devices product SRAM PART NUMBER: 108 = 1M SRAM with single chip enable (available in packages ‘D’ and ‘Y’) 109 = 1M SRAM with dual chip enables (available in ALL packages) PACKAGE CODE: D = 32 pin Sidebrazed DIP 400mil K = 32 pin Ceramic LCC KA = 32 pin Quad Ceramic LCC Y = 32 pin Ceramic SOJ SCREENING LEVEL: M = Military Temperature, -55ºC to +125ºC E = Extended Temperature, -40ºC to +105ºC I = Industrial Temperature, -40ºC to +85ºC COMPLIANCE: B = MIL-STD-883 Compliant SPEED GRADE: LOW POWER OPTION: L = Low Power No Mark Means Standard Power LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109

ORDERING INFORMATION

LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant informa- tion before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursu- ant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical compo- nents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. LOGIC Devices Incorporated www.logicdevices.com Aug 11, 2010 LDS-L7C108/9-F 1M Static RAMs 128K x 8 Static RAM L7C108 PRELIMINARY INFORMATION L7C109 Revision History L7C108/L7C109 Revision Engineer Issue Date Description Of Change A B C D E F COM DH/-M DH DH 10/8/2008 10/30/2008 07/02/2009 06/11/10 07/30/10 08/11/10 Initial Release Datasheet Format Revision Updated specs: 1. Added 10ns & 12 speed columns in ICC1 table 2. Added 10ns speed and AC specs in the AC table 3. Updated all DC power specs in DC table 4. Corrected symbol names in AC and Timing diagrams 5. Added speed bin to ordering info table 6. Removed commercial temp offering 7. Added an extended temp offering Revisions: 1. Removed 10 & 12ns bins 2. Removed 32LD FP to be re-introduced wiht our silicon, if market warrants 3. Removed SO - package variant v<Aw 4. Add notation for SMD 5962-89598 that Package t<u will be supplied as a v7w compatible package 5. Increased ICC1, ICC2, and ICC4@2V for standard power 6. Increased ICC2 and ICC4@2V for low power 7. Removed appropriate DSCC and LOGIC part numbers from ordering tables and PN generator 8. Modified LOGIC Devices v<Aw package reference to t<u 9. Corrections to package dimensions for MD-K11 and MD- <1 Updated mechanical drawings for all packages Revisions: 1. Removed all 108 KA quad LCC and K dual LCC package variants from SMD cross reference table. 2. Updated order information chart to reflect current package availabilities. 3. Changed ICC2 conditions to match ICC3 conditions. 4. Changed operating current to be calculated during the READ cycle.