L2340 LODEV | Alldatasheet

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Special Arithmetic Functions L2340 Digital Synthesizer 08/16/2000–LDS.2340-E ❑❑❑❑❑ Digital Waveform Synthesis at

50 MHz

❑❑❑❑❑ 24-Bit Polar Phase Angle Accuracy ❑❑❑❑❑ User-selectable Waveform Synthesis, Frequency Modulation, or Phase Modulation. ❑❑❑❑❑ Amplitude Input for Amplitude Modulation and Gain Adjustment. ❑❑❑❑❑ Replaces TRW/Raytheon/Fairchild TMC2340A FEATURES DESCRIPTION L2340 Digital SynthesizerDEVICES INCORPORATED L2340 BLOCK DIAGRAM The L2340 is a digital synthesizer that performs waveform synthesis, modu- lation, and demodulation. The L2340 automatically generates quadrature matched pairs of 16-bit sine and cosine waves in DAC- compatible 16-bit offset binary format with15-bit amplitude and 32-bit phase inputs. Output waveforms can be phase or frequency modulated. Digital output frequencies are restricted to the Nyquist limit. Functional Description The L2340 converts Polar (Phase and Magnitude) data into Rectangular (Cartesian) coordinates. The user selects the numeric format. A valid transformed result is seen at the output after 22 clock cycles and will continue upon every clock cycle thereafter. 15-bit amplitude and 32-bit phase data are input into the L2340 to produce an output of 16-bit rectangular data. The user may select the data format to either 16-bit offset binary or 15-bit unsigned magnitude format. High accuracy phase increment values with minimal accumulation error is accom- plished by use of a 32-bit phase accumulator. The phase accumulator structure supports frequency or phase modula- tion and is selected by ENP 1-0 and accumulator controls FM and PM. CLK OEI Q 15-0 ENA AM 14-0 ENP 1-0 PH 31-0 FM PM OBIQ I15-0 OEQ Digital Synthesizer

00 No accumulation (normal operation)

01 PM accumulator path enabled

10 FM accumulator path enabled

11 Logical OR of PM and FM (Nonsensical)

TABLE 2. ACCUMULATOR CONTROL is latched on the rising edge of CLK. latched on the rising edge of CLK.

  1. ‘M’ is the Modulation Register and

the Functional Block Diagram. TABLE 1. REGISTER OPERATION

TABLE 3. RESULTANT DATA VALUES OF CIRCLE TEST NEAR 45°

Special Arithmetic Functions 08/16/2000–LDS.2340-E M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 4.0 mA 0.4 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 95 mA ICC2 VCC Current, Quiescent (Note 7) 5m A C IN Input Capacitance TA = 25°C, f = 1 MHz 10 pF C OUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

Special Arithmetic Functions L2340 Digital Synthesizer 08/16/2000–LDS.2340-E 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 1234567890123456789012345678901 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1 23456789012345678901234567890 1 1234567890123456789012345678901 SWITCHING CHARACTERISTICS L2340– 50* 25* 20 Symbol Parameter Min Max Min Max Min Max tCYC Cycle Time 50 25 20 tPWL Clock Pulse Width Low 10 8 7 tPWH Clock Pulse Width High 8 7 6 tS Input Setup Time 12 7 6 tH Input Hold Time 1 0 1 tD Output Delay 22 18 16 tENA Three-State Output Enable Delay (Note 11) 13 13 13 tDIS Three-State Output Disable Delay (Note 11) 13 13 13 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) L2340– 50* 25* 20* Symbol Parameter Min Max Min Max Min Max tCYC Cycle Time 50 25 20 tPWL Clock Pulse Width Low 11 9 7 tPWH Clock Pulse Width High 8 7 6 tS Input Setup Time 13 7 6 tH Input Hold Time 2 2 1 tD Output Delay 25 20 18 tENA Three-State Output Enable Delay (Note 11) 15 14 13 tDIS Three-State Output Disable Delay (Note 11) 15 14 13 M ILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) 12345678901234567890123 1 234567890123456789012 3 1 234567890123456789012 3 12345678901234567890123 *DISCONTINUED SPEED G RADE

Special Arithmetic Functions 08/16/2000–LDS.2340-E SWITCHING WAVEFORMS :N O ACCUMULATION CLK PH 31-0 ENP 1-0 0123 2 2 2 3 EN EN EN A B C FM, PM I15-0 Q 15-0 f(A) f(B) tH tS 00 00 00 ENA AM 14-0 tD OBIQ tPWH tPWL tCYC SWITCHING WAVEFORMS :P HASE MODULATION CLK FM, PM PH 31-0 ENP 1-0 01234 2 2 00 01 OBIQ 01 01 C AM 14-0 R 01 01 01 I J K 24 25 ENA I15-0 Q 15-0 C + I 2C + J 3C + K 4C + L L

Special Arithmetic Functions L2340 Digital Synthesizer 08/16/2000–LDS.2340-E 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values be- yond those indicated in the Operating Conditions table is not implied. Expo- sure to maximum rating conditions for extended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Never- theless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. Input levels below ground or above V CC will be clamped beginning at – 0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with in- puts in the range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guaranteed as specified. 5. Supply current for a given application can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing ev- ery cycle and no load, at a 20 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

Special Arithmetic Functions 08/16/2000–LDS.2340-E

ORDERING INFORMATION

0°C to +70°C — COMMERCIAL SCREENING Speed 20 ns Plastic Quad Flatpack (Q1) L2340QC20 120-pin VCC Q 4 Q 3 GND Q 2 Q 1 Q 0 VCC OEQ GND GND CLK GND OBIQ ENP GND ENP 1 PM FM VCC PH 0 PH 1 PH 2 PH 3 PH 4 PH 5 PH 6 GND PH 7 PH 8 Q 5 Q 6 GND Q Q 8 Q 9 GND Q Q 11 Q 12 VCC Q 13 Q 14 Q 15 GND GND I VCC GND I GND I VCC I10 I11 GND I I13 I14 VCC I15 GND OEI V CC GND AM AM 13 GND AM AM 11 AM 10 AM 9 AM 8 AM 7 AM 6 GND AM AM 4 AM 3 GND AM AM 1 VCC GND PH 9 PH 10 VCC PH 11 PH 12 PH 13 PH 14 PH 15 PH 16 PH 17 VCC PH 18 PH 19 PH 20 GND PH 21 PH 22 PH 23 VCC PH 24 PH 25 PH 26 PH 27 PH 28 PH 29 PH 30 PH 31 ENR AM 0 Top View 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

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GND AM 9 GND GND V CC ENA PH 29 I11 I14 GND GND AM AM 10 AM 7 AM 5 AM 3 AM 1 PH 30 I10 I12 I13 I15 OEI AM 14 AM 13 AM 11 AM 8 AM 6 AM 4 AM 2 AM 0 KEY Speed Ceramic Pin Grid Array (G4) Discontinued Package