L10C11

L10C11 LODEV | Alldatasheet

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Technical content

4/8-bit Variable Length Shift Register Pipeline Registers 03/27/2000–LDS.11-L1 qqqqq Variable Length 4 or 8-bit Wide Shift Register qqqqq Selectable Delay Length from 3 to

18 Stages

qqqqq Low Power CMOS Technology qqqqq Replaces Fairchild TMC2011 qqqqq Load, Shift, and Hold Instructions qqqqq Separate Data In and Data Out Pins qqqqq Package Styles Available:

• 24-pin Plastic DIP
• 28-pin Plastic LCC, J-Lead FEATURES DESCRIPTION L10C11 4/8-bit Variable Length Shift RegisterDEVICES INCORPORATED The L10C11 is a high-speed, low power CMOS variable length shift register. The L10C11 consists of two 4-bit wide, adjustable length shift registers. These registers share control signals and a common clock. Both shift registers can be programmed together to any length from 3 to 18 stages inclusive, or one register can be fixed at 18 stages of delay while the other is variable. The configuration implemented is determined by the Length Code (L 3-0) and the MODE control line as shown in Table 1. Each input is applied to a chain of registers which are clocked on the rising edge of the common CLK input. These registers are numbered R1 through R17 and R1’ through R17’, corresponding to the D 3-0 and D7-4 data fields respectively. A multi- plexer serves to route the contents of any of registers R2 through R17 to the output register, denoted R18. A similar multiplexer operates on the contents of R2’ through R17’ to load R18’. Note that the minimum-length path from data inputs to outputs is R1 to R2 to R18, consisting of three stages of delay. The MODE input determines whether one or both of the internal shift registers have variable length. When MODE = 0, both D 3-0 and D7-4 are delayed by an amount which is controlled by L 3-0. When MODE = 1, the D7-4 field is delayed by 18 stages independent of L3-0. The Length Code (L3-0) controls the number of stages of delay applied to the D inputs as shown in Table 1. When the Length Code is 0, the inputs are delayed by 3 clock periods. When the Length Code is 1, the delay is 4 clock periods, and so forth. The Length Code and MODE inputs are latched on the rising edge of CLK. Both the Length Code and MODE values may be changed at any time without affecting the contents of registers R1 through R17 or R1’ through R17’. L10C11 BLOCK DIAGRAMREGISTER R1 REGISTER R2 REGISTER R3 REGISTER R15 REGISTER R16 REGISTER R17 L REGISTER D 3-0 REGISTER R1’ REGISTER R2’ REGISTER R3’ REGISTER R15’ REGISTER R16’ REGISTER R17’ D 7-4 L3-0 MODE CLK R17 R16 R15 MUX REGISTER R18 Y3-0 REGISTER R18’ Y7-4 R17’ R16’ R15’ R4’ R3’ R2’ MUX

TABLE 1. CONTROL ENCODING

4/8-bit Variable Length Shift Register Pipeline Registers 03/27/2000–LDS.11-L3 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 L10C11– 30* 25* 20* Symbol Parameter Min Max Min Max Min Max tPD Output Delay 30 25 20 tPW Clock Pulse Width 15 12 12 tSD Data Setup Time 25 10 10 tHD Data Hold Time 2 2 0 tSL L3-0, MODE Setup Time 25 10 10 tHL L3-0, MODE Hold Time 2 2 0 1234567890123456 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1234567890123456 L10C11– 25* 20 15 Symbol Parameter Min Max Min Max Min Max tPD Output Delay 25 20 15 tPW Clock Pulse Width 15 12 10 tSD Data Setup Time 20 10 8 tHD Data Hold Time 2 0 0 tSL L3-0, MODE Setup Time 20 10 8 tHL L3-0, MODE Hold Time 2 0 0 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS M ILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS tSL CLK tSD tHD tHL tPW tPW tPD D 7-0 L3-0 Y7-0 MODE 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *DISCONTINUED SPEED GRADE

4/8-bit Variable Length Shift Register Pipeline Registers 03/27/2000–LDS.11-L4 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values be- yond those indicated in the Operating Conditions table is not implied. Expo- sure to maximum rating conditions for extended periods may affect reliability. 2. The products described by this speci- fication include internal circuitry de- signed to protect the chip from damaging substrate injection currents and accumu- lations of static charge. Nevertheless, conventional precautions should be ob- served during storage, handling, and use of these circuits in order to avoid expo- sure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. In- put levels below ground or above V CC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given application can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing ev- ery cycle and no load, at a 5 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output volt age with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

4/8-bit Variable Length Shift Register Pipeline Registers 03/27/2000–LDS.11-L5 1234567890123456789012345678901212345678901234567 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1234567890123456789012345678901212345678901234567 Plastic DIP (P2) L10C11PC20 L10C11PC15 24-pin — 0.3" wide

ORDERING INFORMATION

24-pin — 0.6" wide 0°C to +70°C — COMMERCIAL SCREENING Speed 20 ns 15 ns –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING D 0 D 1 D 2 D 3 VCC CLK D 4 D 5 D 6 D 7 GND MODE Y D 0 D 1 D 2 D 3 VCC CLK D 4 D 5 D 6 D 7 GND MODE Y Plastic DIP (P1) Discontinued Package

4/8-bit Variable Length Shift Register Pipeline Registers 03/27/2000–LDS.11-L6 Plastic J-Lead Chip Carrier (J4) L10C11JC20 L10C11JC15 28-pin Speed 20 ns 15 ns 0°C to +70°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING Top View 12 17 18 4 2831 2 13 14 15 16 NC GND GND MODE NC D VCC CLK D 4 NC D 5 D 6 D 7 D 2 D 1 D 0