IH5141MFD

IH5021 INTERSIL | Alldatasheet

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Multiplexers Analog Switches : veto with Drivers 3 . oo Page - Lage : 1H5108 3-63 0G118/123/125 3-6 < 1H5208 3:79 DG139A Family 3-45. : 5 . 1H6108 3-93 DG180 Family 3-19 “ss rn (H6116 3-99 DGM181 Family 3.23 ee eae 16208 3-109 0G200 3:28 [oem i ’ 1H6246 3-115 DG201 3-32 i . IH5008-24 3.36 . 8 . 1H5025- 3-41 Analog Switch 1H5040-51 3-48 Drivers/Level 5052/3 356 Translators 1H5200 328 fee 123/125 3-9 1H5201 3:32 shee teens D129 3-13 : 31 . . IH6201 °° | Video!RF Switch on 7 1H5341 3-87 ae

. Low Leakage and ‘ . Low Quiescent Current High Speed ‘Low tps(on) a poo eat i meer ‘driver. gato ‘combination ‘combination Datao Farnily ‘ vette 3. speed witn 3. Loe teaage power consumption DSramatiah aloe 2 Draw nigredessont Eat ; wen ve sm vom vem we ° 5140 SPST GMIe4 — Dual DPST ‘3, DGIB!, 164, 187 182 pat SPOT Pettus Beeeret HSN ceuteor Sareror ee vo bow ee Spor testes Dua! SPOT adorn ee 188 joe Sopot 12, Bie ater - oateer Doveorbar, Dual SPOT i EE : 32

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ANALOG SWITCHES & MULTIPLEXERS Analog Switches with Driver Lil Tosiom —loxgn fon tayp, —______ al innat . Power Woof Device Switch i hake ~ ‘put Consumption Type Channels: La Technology max(h max max. ax ‘Logie Level Type(?) Lid 145021 P.JFET 100 02 05. @5 TTL High Level to

45022 PAUFET 1 02 05 0S TTL Low Level ~ lo

‘SPST 1 145023 PAJFET 100 02 05 05. TTL High Level lo

445024 PFET 190 02 05 05 TTL Low Level lo

15037 PFET 100 05 02 02 TTL High Level lo

18038 PASFET 150 0S 02 02 TTL High Level Jo

15040 cmos: 5 10 05 0.25 DIL. TTL, ATL. CMOS, PMOS hi 035 15140 ‘CMOS a 01 0.1- 0075 TTL. CMOS hi 035, es gio) NNFET 10 © 100 03 © 9.25 OTL, TIL, ATL fo 120 bGi81 NASFET » 10 0.15 0.13 OTL. TTL, RTL i 920 (0G182 | NASFET acy 10 0.25 013 OTL, TTL. RTL 0 120 3 ‘DGM182 cmos 15 01 025 0.13 OTL, TTL, ATL lo 035 06200 CMOS: 7 10 07 05 OTL, TTL. RTL. CMOS. TTL High Level lo 30 1HS017- PAJFET 100 02 05. 0.5 TTL. High Level lo 15018 PAJFET 150 02 05 05 TEL. Low Level . lo 15019 PFET 100 02 O05 OS TTL. High Leyet lo ‘SPST 2 145020 PASFET 150 02 O05 05 Tk. Low Level lo

15033 PASFET 100 05 02 02 TTk, High Level w

1HS034 PFET 130 05 02 02 TTL. High Level . fo 1HS035 PAJFET 100 oS 02 02 TTL. High Level to (45036 P.JFET 150 os 02 02 TTL, High Level lo H5048 CMOS sS 10 025 0.15 DTL. TTL, ATL, CMOS, PMOS LJ 035 1H5141 cmos cy a1 OF 0.075 TTL. CMOS hi 035 . IHS341 cmos % o1 03 0.15 TTL. CMOS hi 036 a

145013 PAJFET 100 02 05 OS TIL, High Level to

THSOT4 P-JFET 150 02 05 05 TTL, Low Level to iH5015 P-JFET 100 02 05 05 TTL. High Level lo 1HSO16 PAJFET 130 02 05 05 TTL, Low Level lo SPST 3 150290 PAJFET 100 05 02 02 TTL. High Level lo 145030 ‘PJFET 150 05 02 02 TTL, High Level lo 1H503+ ‘P-JFET 100 05 02 02 TIL, High Level to WH5032_ PeJFET 150, ps 02 02 TTL. High Level lo 06118 P-MOSFET 450 40 03 10. OTL, TTL, RTL lo 133 06201 cmos: 75 10 OS 025 OTL. TTL. RTL, CMOS lo 350 sest ‘ 15009 PAJFET 100 02 05 05 TTL, High Level to . 1HS010PAFET 19 «02«0S =~ «STIL. Low Level fo (H5011 PASFET 00 a2 05 05 TTL. High Level bo S011 PFET 1 02:05 ~=—«0S-_—“TTL. Low Level ‘0 S025, P-JFET 10 05 02 2 TTL High Level to ‘1H5026- P-IFET 190 05 02 02 TTL High Level to Hs027 P-JFET 100 0s 02 02 TTL High Levet to

15028 P-JFET 150 0§ 02 02 TT High Level lo

. 145052 cmos cd 10 05 0.25 DTL, TTL. RTL, CMOS. PMOS lo 350 0G123 P-MOSFET 40 40 03 1.0 OTL. TTL, ATL Li 133 0G125 P-MOSFET 450 +40 03 1.0 0 OTL, TTL. ATL lo 133 DG143A NAJFET 80 10° 04 08 = OTL, TTL, ATL 3 a4 ‘DG1444 NAJFET 0 10 04 08 = OTL. TTL, RTL. 13) 84 ‘SPST 5 ‘DG146A NAJFET 10 wo OS 125° OTL. TTL, RIL 3 84 0G161A NJFET 15 0 05 1,25 OTL, TTL, RTL (3) 90 ‘0G162A NJFET 50 20 04 08 OTL, TTL, ATL (3) 90 06186 NJFET 10 100 03 0.25 OTL, TIL, ATL 3} 73 06187 NJFET 30 10045 0.13 OTL, TTL, ATL (3) 73 06188 NAJFET cy 16 025 © 0.13) DTL, TTL. RTL 3) 73 OGM1gs = CMOS 6 01 025 «043. OTL. TTL. ATL 3 03s ‘SPOT 1 4H5042 cmos 78 1.0 0.05 0.025 OTL, TTL. RTL PMOS, CMOS ' 8) 035 15050 CMOS % 1.0 025 0.35. OTL: TTL, ATL PMOS. CMOS 8) 035 IH5142 CMOS. 0 01.175 0.125 TTL. CMOS 13) 035, 34 :

Analog Switches with Driver continued S00 eee Tosien | tok Loge input Prwer Neot ——bavien Switch ee er eed : ‘opt Consumption Type Channels, No. Technology: max(l) mak, max max Logie Level Type(2) nw 06189 NJFET 10 700 03028 OTL. TTL. ATL 3 120 ‘06190 NAFET 30 10 015 0.93 OTL, TTL. ATL . ro) 120 ‘DG19t NAJFET 15 10 0.25 0.93) OTL. TTL. RTL ry 120 ‘DGM1S1 MOS 15 01. 025 013 DTL. TTL. RTL (3) 035 ‘1H5051 ‘CMOS: B+ 10 025 O15 DTL. TTL. RTL. PMOS. CMOS 13) 038 1H5143 CMOS: 50 Os 0.175 0.125 TTL. CMOS 13) 035 DPsT 1 1H5044 Mos: 5 10 05° 0.25 TL. TFL. ATL. CMOS, PMOS hi 035, 1H 144 CMOS. 50 010.175 0.125 TTL. CMOS Li 035 06183 NJPET 10 wo 03 025 OTL. TTL, ATL Ly 84 . O61 = NUFET 3 10 015919 OTL! TTL, TL ai oe 06785, N-JFET ry 10 025 013° OTL, TTL RTL hh a DPsT 2 Oss = CMOS. % 01 028 © 013 OTL. TTL. ATL hie 05 1H5049 ‘CMOS kJ 10 025 015 OTL, TTL. RTL. PMOS, CMOS hi. 03S 15145, cmos 50 01 0.175 0.925 TTL. CMOS bi 035, SSeS DG139A, NFET 0 10 04 08 OTL, TTL, ATL a Be 3 (0G1424 NJFET 80 10 04 08 OTL, TTL. ATL @ co oPoT 1 GIA NUFET 10 00 5 125 OTL. TTL. ATL @ es OG163A AAJFET 1S 0 05 4.25 OTL. TTL. ATL @ 90 ‘DGI64A N-JFET 0 20 04 08 OTL, TTL, ATL 8) 90 IH5046° ‘MoS 75 10° 05 0.25 OTL. TTL, RTL CMOS. PMOS QD 035, PST 1 1H8047 CMOS: 7s 10 05 025 DTL. TTL. RTL CMOS, PMOS hi 035 eS Multiplexers: ao SSS Fosion tog ton tay tale inpat Per Meet Davies Switch en ed pvt Consumption Type Channets we Technology max(1) mx max mx Logie Level Type(2) nw cmos Tot 8 $H6108 cmos 300 Or 15 1.0 OTL, TTL, RTL. CMOS hi 45 CMOS Jot 6 NH6116- CMOS: 600 02 15 1.0 BTL. TTL. RTL, CMOS hi. 45 MOS 208 146208 CMOS 00 Uw 15 1.0 OTL. TTL, ATL. CMOS hi 4S CMOS: 2of 16 1H6216 CMOS. 0 O2 15 1.0 DTL. TTL, RTL. CMOS Li AS eee MOS GO 2 SOOT PL cMos CMOS Fault tof 8 1H5 108 CMOS 70 Or 45 1.0 OTL. TTL, ATL, CMOS: bi 45 Protected 2 of 8 15208 CMOS 70 O1 1S 10 DTL, TTL. ATL. CMOS La AS Serco Zot o ___Wea0e _CMoS 7} AS OOM TNL ATL CMOS Drivers tor FET Switches . Electrical Characteristics @ -25°C—Military Temperature Devices - —Eleirical Characteristics @ °25°G—-Military Temperature Devices 00 Your ton tar Power Device Positive: ‘Negative: LJ at te bint Logie Input ‘Consumation Mao Channels Mo. Volts Volts max max uA (many mA (max) Level (mW) CL, eC a ac 1, 2 ‘1H6201 +140 “40 200 0 10 10 TM cd) 4 129 Yupply “3300 0 1000 200 25,8 THOT 8 6 123 Veupply “19750 600 10 10nk TILL Ey D125 Veupol 2197 250 600 10 154A Ti EI oe SSSSSSSSSSSSSSSSSSssSsssSSSSssssSSSSSS RF/VIDEO SWITCH eS eeeeSSSSSSSSSSSSSSsSsss es 0S (ON) Power No. of Device a on Logie Consumption . Type Channels Na, Max Isalatlon {apt (nw) St] ‘CMOS: 2 1H5344 75. > 6008 @ 10 MHz TTL, CMOS 0.030 a oT 8H Notes: 1. Switen Resistance under worst case analog voltage 2, Positive logic LO ("0") or HI ("1") voltage al driver input necessary to turn switch on. 8. Logie "0" or" can be arbitrarily assigned for double-Ihrow switches. 4. Switch resistance under best case analog voltage. : . 35

4 and 5-Channel Driver-MOS-FET Switch Combinations FEATURES GENERAL DESCRIPTION @ Available With and Without Programmable Constant This series includes’ devices with four and five channel Current pull-up ‘switching capability. Each channel is composed of a driver © Zener Protection on All Gates é and a MOS-FET switch. Two driver versions are supplied @ P-Channel Enhancement-Type MOS-FET for inverting and noninverting applications. A MOS-FET, Switches ' used as a current source provides an active pull-up for faster ®@ Each Switch Summed to One Common Point switching. . . An external biasing connection is brought out for biasing the current source for optimization of speed and power. SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD) cn . | we a i > * : . * st =" “e Sante] Bes mt st ort Pry dt bo eel an "ED one wt _! | i ORDERING INFORMATION TRUTH TABLE P — 14-Pin Ceramic DIP {Special Order Only} L L L L | OFF A Miltary (258°C 10 7126°C) ty a ya | of ] ete B — Industrial (-20°C to +85°C) 4 rh hy tt OFF L=OV,H=+V¥ 3-6

Logic to Emitter (VL=Vo) oe oe eee 38V i . NOTE: Dissipstion ratirig sssumes.ceviée is mounted with all leads Reference to input (Va - Vin}... +--+ see eee ee BV temperature of 70°C. Derate 10mW/°C for higher ambient Logic to Input (VL = Vin) sees sere eee e eee 26V ‘temperature, Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device, These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied, Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Test conditions unless specified otherwise are as follows: Vi = 4.5V, Va = 0, V-'= -20V, and P=-20V. Input ON and OFF test conditions used for output and power supply specifications. : PARAMETER MAX LIMITS: (NOTE) = = 7 CONDITIONS s12s°e_| units | tors [1 [+ [too ea |v sv o [reco ff 3 fa . fa Lew Pg channel (ON) revi [ma | 3 ee ra [Ticcorss [| io Tea

3 Daa]

i wor [ [0 a All Channels (OFF) [Teer | [fd 26 ton 0.3 bs : zw All fc: " bs See Switching Times -_ EZ | circuits s 2 Ls . NOTE: {OFF} and {ON) subscript notation refers to the conduction state of the MOS-FET switch for the given test condition.

bin vs Vin SWITCHING TIMES ve abies TEMPERATURE tos Vp oF Vs 18 1100 ‘* == [cir - HH Vaso H-—- SSS=S San : a | Bo ayy es

2.4 TT goolvrw — TT == iow

Feaeaeee a OD = [cour=soer [TTT] Vera

5 Fo é pee TT BS fal

@ CUT ecen 7] = 700 al 7 NS CTT) £ 'Cereeeey a ee § mo Lee

3 Be 3 eo COLTS fg ==— ==

Sool LETT ae | ° ESS

2 TTT TTA TT Fm LLL LLL oe

• LLCO & COCCeeeorc Foz A CEST COOP) oS ptt 0 2 04 08 08 rr an vo 70 Vin = INPUT voLTAGeE «i TEMPERATURE vp ORV v1 APPLICATION TIPS ‘The recornmended resistor vaiues for interfacing RTL, DTL, and TL Logic are shown in Figures 1 and 2, 1} — GEREace ae (ae Je bios 7 = : pO ° TEESE guy an [> | ae | I™ | Figure 1.06328 ane 06128 Fiore 2, 06123 Enable Control The Va and V, terminals can be used as either a Strobe or an Enable control. The requirements for sinking current at Va . or sourcing current at V,_ are: | jon) x NO. of channels used, for 06118 and DG125, and !pon) x No. of channels used, for the DG123 devices. The voltage at V, must be greater than the voitage at Viy by at least +4V. SWITCHING TIMES ‘ . 96123 if soy

| D123/D125 < ). - Thee 6-Channel FET Switch Drivers FEATURES » GENERAL DESCRIPTION . ‘© Provides DC level shifting between low-level The D123 and D126 monolithic bi-polar drivers convert Logie and MOS:FET or J-FET switches low-level positive signals (0 & +8V)'to the high level positive © Externe Collector Pull-ups required and negative voltages necessary to drive FET switches. One Jead can be used to provide an enabling capability. © Direct int rface with G116, G117, G119, G115, and G123 \\10S-FET switches \\ SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD) D123 D125 2 | % | | ° Yates 2 an . 10 LL D> ben | ds ‘ 1 “ |

ORDERING INFORMATION

K = $4-Pin CERDIP L — 14-Pin Fiat Pack P— 14-Pin Hermetic DIP (Special Order Only) Temper Te Mery 285°C to 1258) B = Industrial (-20°C to +85°C) Deviee Chip Type ‘ 3.9

_. D128/125 EAINTERSIL ABSOLUTE MAXIMUM RATINGS . Input-to-Emitter Voltage (Viy - Vee) 33V Storage Temperature 65°C to +150°C Output-to-Emitter Voltage (Vo~ Vee) 33V Operating Temperature -B5°C to 125°C Logic Supply-to-Emitter Voltage (V_ - Vee) 27V Lead Temperature (Soldering, 10 sec) 300°C Input-to-Reference Voltage (Vin = Va) 2 Input-to-Logic Supply Voltage (Vin - Vi) +6V . vos i" NOTE: Dissipation rating assumes device is mounted with all leads Reference-to-Emitter Voltage (Vm - Vee) 31V welded or soldered to printed circuit board in ambient Maximum Dissipation (Note) 750 mW temperature of 70°C, Derate 10 mW/°C for higher ambient Current (any pin) 30 mA temperature. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those inidicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may'affect, device reliability. : : Test conditions unless otherwise specified are as follows: Vee = -20V, Vi = 4.5V, lour = 0, Vq = 0. Output and power supply measurements based on specified input conditions. MAX LIMIT PARAMETER = = = CONDITIONS 2 . x linvorey 100 BA Vin = 0.4V 5 o Vinsiont 0.8 v ly = 1mA 2/2 lintorey 1 1 20 HA *] Vin 84 1V. 6 linion? -0.7 ~07 0.7 mA Vin = 0.5V Sle louriorr) 0.1 0.1 10 BA Vour = +10V E Aas Voution) “19.7. | -19.7 -19.5 v lout: = 1 mA 6 jae Vourion) ~19.2 =19.2 ~19.0 Vv tour = 4 mA Trion 05 mat >| 8 lacorr)? 150 BA a/4 ) z legion" 1 mA lour <0 for a leeiore) 200 BA GN measurements. Fa Ton 2 2 19 ma | Vour = HOV for measurement rg g tuiorr)? 1 1 100 BA - ° tegen’? 2 2 19 mA : teevorr' 2 2 200 HA o 1/8 trom 250 lout = 1MA Court! = 10 pF g = glo Torn (4? 800 (See Switching Times) be] 2 Ton) 250 lout =4mA Cour = 10 pF Ee FA 5 torn 600 {See Switching Times) QOTES: 1) One channel ON, 8 channels OFF. i2) All channels OFF. . {3} Add 30 ns per pF for 1 mA and add & ns per pF for 4 mA for additional capacitive loading. (4) For Dual-In-Line package add 120 'ns t0 Toff}: (S) For Dual-in-Line package add 30 ns t0 t{off) 3-10 .

D129/125 . INTERSIL SWITCHING TIMES : pies « eS 10m: 1a ” nein 3 ver 0. . = = ww eo ou in 1 70 160%! a vcsem = Dm -v. res Lov ors . “ tans = Comiawaeh te FL ~T Cireuie Bdgroms TYPICAL CHARACTERISTICS SWITCHING TIMES vB sortiseay) VS tiniPeAK) ‘TEMPERATURE D123 AND Vinton V8 ois D125 (SEE NOTES 4 AND S) TEMPERATURE D120 ge 1100 1000 ey 2 FA REREESo =... 1 [1 ET | zat Lo <I Vee ==20v 6 z Let eal] beer) od a a | aan = eof tre, |. ce a Em Terra 2° {TT ANSTI Zul LAwe fof et CLL z Vege #200. 3 14 : Be set 5 on a ere “ST aA fT ocigr cama Perret M7 Take oo CEES wl LUT 3. 2 3 4 Ts 0 2 «78 (2S. “15 25~=~C«SC:CSSSCSC tae (nA | TEMPERATURE Co) TEMPERATURE Fe) loutiorr) VS Vear ve TEMPERATURE nerkt one Lin V8 Vin 0929 Dia ano przs D123 AND Diz 1s 0 pp Bu A : ——— ge HDT ag | OES Meet z 10 ee eg @ LUT fecha Eas et ee | = Fd HH ESSH 3 08 A ea = os 02 3 os coh cai st TT BESS o a2 a4 08 0B a Bas e808 oe INPUT VOLTAGE V1 “TEMPERATURE FC) TEMPERATURE Cot 3-11 .

D129/125 < . INTERSIL APPLICATION TIPS . Interfacing the D123 and D125, . In order to meet all the specifications on this data sheet, certain requirements must be met by the drive circuitry. ‘The D125 can be turned ON easily, but care must be exercised to insure turn-off. Keeping V,,~ Viy) < 0.4V is amust to insure turn-off, To accomplish this. shunt resistor must be added to supply the leakage current (Ices) for DTL devices. Since Ices = 60 uA, @ 0,4V/0.05 mA = Bk or less should be used. For T?L devices using a 2k resister will insure turn-off with up to 200 HA of leakage current. b> ree D> ip ee > . Using the ENABLE Control, - . Device pins V_ or Vi, can be used to enable the D123 or D125.drivers. For the D123 the enabling driver must sink taion) X no. of channels used, For the D125, , (on) X no. of channels used must be sourced with.avoltage'at least +4V greater than Vin. am APPLICATIONS . ‘Using INTERSIL’S MOS-FET SWITCH G117 with either the D123 or 0125 drivers provides a reliable means of providing up to 5 channels with a series block for multiplexing applications. .

7 T T 7 + 1 roy = resco :

ise ase er So : S:Channel Multiolexer, 312

h 4-Channel MOS FET Switch . . Driver with Decode FEATURES . GENERAL DESCRIPTION The D129 is a 4-channel driver with binary decode input. It © Quad Three-Input Gates Decode Binary Counter to Four has been designed to provide the DC level-shifting required Lines to interface low-level logic outputs (0.7 to 2.2V) to field- effect transistor inputs (up to 50 V peak-to-peak). For a 5V input logic supply, the V7 terminal can be set at any’ volt- © Inputs Compatible with Low Power TTL and DTL, age between -5V and -30V. The output transistor is capa- Ip= 200A Max ble of sinking 10mA and will starid-off up to 50V above V~ in the off-state. © Output Current Sinking Capability 10mA The ON state of the driver is controlled by a logic “1 {open} on all three input logic lines, while the OF F state of the driver is achieved by pulling any one of the three inputs © External Pull-Up Elements Required toa logie “0” (ground). © Compatible with G115 and G123 Series Multichannel The 4-channel driver is internally connected’such that each . MOS FET Switches which include Current-Limiter Pull- ‘one can be controlled independently or decoded from a Up-FETs binary counter. SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD) %, w sage? M24 out Ing of i foc outs : 0 wy 0 « t , ° (EACH DRIVER) > oo D129 AK : L— 14-pin Flat Pak. . , P — 14-pin Ceramic DIP (Special Order Only) A—-58°C to +125°C B—-20°C 10 +85°C 3413

ABSOLUTE MAXIMUM _ RATINGS Vo mV eee bev ceveeeeeeeeeseeveteve. BOV Note: Dissipation rating assumes device mounted with all feads welded GND = Vm eee cee ec eee cece neces 33V Of scldered to pe board in ambient temperature of 70°C. Derate 10mW/°C VIRGND 00... e eee eee ec eee cee e eee BV for nyner ambient termperatures. VIN“ GND... eee eee eect ee ee ee eee £6 Lead Temperature (Solderina, 10cee) 300°C _ Sections of the specifications is not implied. Exposure to abso- . pet net esses * lute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ‘Test conditions uniess otherwise specified V~ = ~20V, Vt = 5V PARAMETER CONDITIONS D129 [per] unit te if + Input Current Vin= ‘SV Input Under Test, TINH aput Voltage High V7 9 All Other Inputs NT input Current, Toure aa INL jnput Voltage Low Vin = 0, Vt = 5.8V -280. |-225 [| oas| [Teal jj fon Turn me See Switching Time Test Circuit bs [ee _Nesative Supply Current One Channel “ON (| [2] [ | mA Fi, eon] sa Peso * Per gate Input SWITCHING TIME AND TEST CIRCUIT + oo tye tte “1 2 iis wav Sanat ov . Ww ctr Po c0K He wen von sooe on 08 FT a THN oon sav eee 344

. . . r . ; Drivers with Differentially Driven FEATURES. GENERAL DESCRIPTION © Each channel complete interfaces with most integrated logic Each package contains a monolithic driver with differential . input and 2 or 4 discrete FET switches. The driver may be © Low OFF power dissipation, 1 mW treated as a special purpose differential amplifier which mw OFF ower cissipation, | m controls the conduction state of the FET switches, The . ; differential output of the driver sets the switches in opposi- ‘© Switches analog signals up to 20 volts peak-to-peak tion, one pair open and the other pair closed. All switches may be opened by applying @ positive control signal to the © Lowrosion), 10 ohms max on DG145 and DG146 Vp terminal. 3 SCHEMATIC AND LOGIC DIAGRAMS. (Outline Dwgs DD, FD-2, JD) * SPDT DPDT 2G143{rosion) = 802 my) . DG199(rHg{oN) = 302) Derastroeiony = 208 ¥ Dereatrosiony = BOM) BGi46(rosiON) = 102) 2 7 DG145(ros{ON} = 1022 BG181"psion! = 182) io ie Deresiroston?= 182 OG162(rps ion} = 502) wd ‘ puitcx STaTe5| DS(ON) . B Bae Son ans ¥ * iseech ve . veowmmy vi S, - 3s. oe wat : oe oe 2 oe 28, im Ms, wy Si " : “ ® oH a Os 2 ve | - pe s ve i ie x H eed " >, wm Feaioeara H : Va NHB) v t ne) = Vie ORDERING INFORMATION . DG139 A K . = 14-pin CERDIP L = 14-pin Fst Peck : P — t4-pin Ceramic DIP (Special Order Only) Temperature Range A Military ~55°C to +125°C B — Industrial -20°C to +85°C . Device Type 346

DG139, DG142 — DG146, DG161— DG164 INTERSIL i ABSOLUTE MAXIMUM RATINGS Vane aw EB BY : Dissipation rating assumes devie is mounted ith all eads aA «welded or soldered to printed circuit board in ambient Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress” ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational ; sections of the specifications is not implied, Exposure to absolute maximum rating conditions for extended periods may affect device reliability. . 3 Applied voltages for alt tests: DG139, DG142, DG143, DG144, DG145, DG146 (vt = 12V, Vo = ~-18V, Vp = 0, Vin2 = 2.5V) and DG161, DG162, DG163, DG164 (V* = 15V, V- = -15V, Va = 0, Vina = 2.5V). Input test condition y_ that guarantees FET switch ON or OFF as specified is used for output specifications. ore! |e [os [| [Tisnore, ] hn ore Ls A TE oa a ee ee a a s ; let +44] “oz t [Pores | Sstee Uenaan Cores | BTS a TAD a a " brn cure Ya 2 s Posie Powe apy ¢ Len eee a ee ee a ee ee ee [eT Ciscoe Gunen NOTE: (OFF} and (ON) subscript notation refers to the conduction state of the FET switch for the given test. : . 316

DG139, DG142 — DG146, DG161— DG164 : INTERSIL ELECTRICAL CHARACTERISTICS PER CHANNEL (cont,) [__assoxuremaxuime | we verconomons [eT fr | [eee [le fe | [see | [=| [= | ° ee ee ee es ee 3 NOTE [OFF sn ION) ssp toson eff te Conan ate af he FET stn forth von "NOTE: (OFF) and (ON absent notation testo she conduction sateafihe FET wen orthegiventes SWITCHING TIMES (25°C) OFF MODEL OFF MODEL . ON MODEL ON MODEL 317 : .

DG139,'DG142 — DG 146, DG161 — Da164 INTERSIL eRe Bea \\\\ a Bi \\\\\\\\ Ba Hi \\ . ree rr rr Vin (Pins 9 or 13) . Vin (Pin 13) ON and the V, side of the switch-is OF F-at 25°C, Conversely, when V, = 2V andV\\,"='2.5V, the V, side'of the switch is OFF and the V, 5 side of the switch is ON at 25°C. TYPICAL CHARACTERISTICS (per channel} “BPRS Of EERESRRS 6° ORES NEP Ee a SSS ° Cee LOTT oo EERE EREEEA ee a wo === ee = === == === Pm S18 ARE ON SS S| - CPs , ASS vo feet z ZZ 2 Seton ies “ S = =>—=—= = ~f ro a oe + ebebsetefocies vee | .| TERR EEE a =SEaSe====

5 Cee4 LETT TTT] eo PED

Sago 0S bo 75 100 ‘yeah a 0 wo PSO Sas OS aso as ‘TEMPERATURE (°C} ‘TEMPERATURE (°C). TEMPERATURE (°C) 3418

< LL High-Speed Driver With Junction FET Switches FEATURES - GENERAL DESCRIPTION © Constant ON-resistance for signals to +10V (DG182, The DG180 thru DG191 series of analog gates consists of 2 185, 188, 191), to +7.5V (all devices) or 4 N-channel junction-type field-effect transistors (J-FET) © +15V power supplies designed to function as electronic switches. Level-shifting © <2nA leakage from signal channel in both ON and _dTivers enable low-level inputs (0.8 to 2V) to control the ON- OFF states OFF state of each switch. The driver is designed to providea turn-off speed which is faster than turn-on speed, so that babe edie tsk which eaih raed break-before-make action is achieved when switching from on tot s, break-before-make action one channel to another. In the. ON state, each switch * Cross-talk and open switch isolation >50dB at conducts current equally well in both directions. In the OFF 1OMHz (750 load) condition, the switches will block voltages up to 20V peak-to- peak. Switch-OFF input-output feedthrough is >50dB down at 10MHz, because of the low output impedance of the FET- . gate driving circuit. SCHEMATIC DIAGRAM (Typical Channel) ° ONE AND TWO CHANNEL SPDT AND SPST CIRCUIT CONFIGURATION TWO CHANNEL DPST CIRCUIT CONFIGURATION Ww ve Mw ve ¥ ° % 5 iia | 12 wf Tl. = aL. 4 “ os — ail elie. | on; op aI = — oJ —_— ae iy (i e] [3 jig) 8 i - No v- DG186/187/168 SHOWN eno y- DG189/184/185 SHOWN PART TOS\\en) coo xX YX NUMBER TYPE (MAX) DG180 Dual SPST 70 DG181 Qual SPST 30 PACKAGE DG182 Dual SPST 75 Cogan mar rack, pais Dual DPST 10 PGERAMD DI ec Ore Oi oG184 Dual DPST 30 | Dat185 unt DPST 75 TEMPERATURE DG186 SPDT 10 A MILTARY -s8¢0 TO s425°0 palay SPDT 0 | B INDUSTRIAL -20°C TO +05" DG188 ‘spoT 75 DG189 Qual SPDT 10 DEVICE TYPE + DGi190 Dual SPDT 30 e191 Dual SPDT 75 DRIVER 319

MAXIMUM RATINGS ~ Current (S or D) See Note 3. sie. ce se Ses eee ee ves 2OOMA VOVDe ccc ooeccres, 88VVEGND oss osssssss BV. Operating Temperature «iss. cssees+, ~85°Ct0.4 125°C VoNG seveveceveree #22V0 GND V@ oe se sieves 27 825 (DIP) mW VINT cee eee BBV GNDViqe cic eeee Rov *Device mounted with all leads welded or soldered to PC board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device, These are stress ratings only, and tunctional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device retiabllity, ELECTRICAL CHARACTERISTICS (V+ = +15V, V- = -15V, V.=5V, Uniess Noted) [rmmueren| cence pare TSS rare tare ae ee ote SGT6T, 162, 184 105 p00 “09 Vea 100, Vp = =10V, VE TOV 187, 188, 190, 197 D165, 188. 186, 189 ‘10901 ir_|_coo, Vi = “OFF fee pe Pe = gee $ va a"oFF € gia eee 188 001 as _| oo v= =a. Vive “OFF eeecet Palel tele ieer {0G180, 18,186, 180) «10000 fa Vins "OFF peewee Tope pepe ls eee | Ve"OFF 16, 17,189, 180 [oater, 26,108,107 | | 2 | 200 | | wo | ao | na | Vosvs=-touww="on’ | tPA Cas -280 | -a60 | -a50 | -as0 | -es0 Taf v=ov |. BS a i [ran Switches [| 00 [aso ton [aonswitres | | wo [| Teo TT a S88 switching time test circuit [sonswitees | | aso | | | coo P| ("son and 750 Switches | [go [ts S233. —— ee [Goon] 187,168, +80. 191 pe [os=ev. Isao Pa Ie | ‘O61, 163, 188, 189 [Wes Ve=0T= Tre | [Type 50 at Tonite See Note S78 oar feo | Pett Ty 190,191 [ocres, vas | | on PT fo . Tootes.te7,108 | | oa [fos [| eeee=t tet | tet 180.161 [oores, rents [| | «0 | TT ao TO Vn = SV [octes. tere | | so | | | -eo ff Cte Pe s fu 18, 185,180, 190, 191

2 Ce au eo Peo ms

L 0G160, 181, 182, 189, ’ saree [ey tye [ootes ies [Tso [so . (cies se7taa | | os | | os [OT an a cl 100, 191 (Dots eas | | ss | fh ss fd Vn = Ov pee PE h 136,185, 168, 190. 191 [octes raves | | a2 | | fsa {| [eno fa | CY eo | Tt eo Note 1; See Switching State Diagrams for Vin “ON” and Vin “OFF” Test Conditions. Note 2: Off Isolation typically >55dB at 1MHz for DG180, 183, 186, 189. ‘Note 3: Saturation Drain Current for DG180, 183; 186, 189 only, typically 300mA (2msec Pulse Duration). Maximum.Current on all other devices {any terminal) 30mA. 3:20

ELECTRICAL CHARACTERISTICS (CONT'D) . MAXIMUM RESISTANCES (rps(on) MAX) : INDUSTRIAL DEVICE |__MILITARY TEMPERATURE TEMPERATURE UNITS CONDITIONS (Note 1) numeen [sc | sc | ste [-are | =e | ase | V+ =18V, V> = ~18V, Y= BV DG180 10 19 20 15 15 EY rn Vo=-7.5V DGi8t 30 30 60 50 Ey) 75 a Vo=-75V - DG182 75 75 100 100 100 150 a Vo =~10V" DG183 10 | 10 20 5 18 2 2 Vos-7.5V. © DG184 cu 30 60 50 50 75 2 Vo = ~-7.5V DG185 7S 75 150 100 100 1450 a Vo =-10V Is =-10mA DG186 10 10 20 6 al 2 a Vo =~7.5V DG187 oO 30 60 50. 50 5 a Vo =-7.5V Vin = "ON" bG188 5 75 150 100 100 160 a Vo = ~10V . 0G189 10 10 20 15 15 25 a Vp =~7.5V DG190 30 30 60 50 50 50 a Vp =-7.5V DG191 5 75 150. 100. 100. 150. 2 Vp ==10V_ APPLICATION HINT (for design only): Normally the minimum signal handling capability of the DG180 through DG191 family Is 20V peak-to- peak for the 752 switches and 15V peak-to-peak for the 10 and 302 switches (refer Ip and Is tests above). For other Analog Signals, the following guidelines can be used: proper switch turn-off requires that V~ = Vanatog(peak) —V, where V, =7.5V for the 109 and 302 switches and V,=5.0V for 752 switcties e.g. -10V minimum (~peak) analog signal and.a 750 switch (V,=5V), requires that V- s ~10V —§V= -15V. SWITCHING TIME TEST CIRCUIT switching time test circuit. Vo'is the steady state output with ‘Switch output waveform shown for Vs=constant with logic switch on. Feecthrough via gate capacitance may result in input waveform as shown. Note that Vs may be +or~as per _spikes at leading and trailing edge of output waveform. . Lote INPUT FOR “OFF” TO “ON” CONDITION (0G180/181/182 SHOWN) uw ve Louie ay. Vv 15v INPUT ‘switcn te<fons 18¥" SWITCH 5, i ‘OUTPUT ‘sins INPUT v0 ton, Ve = +8 RL. oa INPUT Logie "7 mG (REPEAT TEST FOR SwiTCH 9 2.1 Vo. a Gn 1S ALL CHANNELS) tn ‘er Vo- Vas rosa = ” v WO" VS RL roe DUAL SPST DUAL DPST SPDT DUAL SPDT G180/181/182 DG189/184/185 DG186/187/188 DG189/190/191 TEST CONDITIONS TEST CONDITIONS TEST CONDITIONS TEST CONDITIONS DG180/181/182 DG 189/1847185 bG186/187/168 1DG189/180/191 Vin "ON" = 0.8V | All Channels) [Vin “ON” = 2.0V | All Channels] {Vin "ON" = 2.0V_ | Channel 1 Vin “ON” = 2.0V [Channels 1 & 2 Vin “OFF” = 2.0V | All Channels) Min “OFF' = 0.8V | All Channels} |Viq "ON" =0.8V | Channel 2) } Vin “ON” = 0.8V [Channels 3 & 4 - Vin “OFF” = 2.0V | Channel2] | Vin “OFF” = 2.0V/Channels 3 & 4 Mw “OFF* = 0.8 | Channel] [Viv “OFF"= 0.8V|Channels 1&2 ‘SWITCH STATES ARE SWITCH STATES ARE SWITCH STATES ARE SWITCH STATES ARE . 321

PIN CONFIGURATIONS AND SWITCHING STATE DIAGRAM (See previous page for logic input) DUAL SPST (DG180, 181, 182) Metal Can Package Flat Package CERDIP* s : mi XM AQ aS i ° = hed oe “Be ON mm 2 Sf tye oft to CTE a Be ED eT] wot aA k fee «d A A Bee i @D> CPI) v- ne Cf] Aa P5 ne nc] () Q [rl] we v Ooo ~ , Tr ws EP Fa ms wet cH Sono uf fa]cno {OUTLINE DWG TO-100) (OUTLINE DWG FD-2) (OUTLINE DWG JD) DUAL DPST (DG183, 184, 185) Flat Package CERDIP* 4 14 ” ..~+d = 7 7 “ oe r EN 2 z mo BI ° vad at I s: . so, By moot! &ECHIES. : oie] A fy vicoy Ph y- we | Opti» woe Eh i aan ond {OUTLINE DWG FD-2) (OUTLINE DWG JE) ‘SPDT (DG186, 187, 188) Metal Can Package Flat Package CERDIP* we «ve Line

2 OP « noc] ts we ne Ey fay nc

so nc — = oc fe = | v+ QLD sno woog D—> — wEE)—>~ [anc % a hs v- wo EI v- we co “ex ra [=] ono (OUTLINE DWG TO-100) (OUTLINE DWG FD-2) (OUTLINE DWG JD) DUAL SPDT (DG189, 190, 191) Flat Package ‘CERDIP* orto — ne Te oua™ oy f= o: cory BY zi ° ra Etc fz] ano eo) epee “a le : rm IS ™m CTH) CHE: De fet © fs] v+ vcoo —_ ne Ef QO am z | | a o2 EY ° 3] se ieee ey ee “*Side braize ceramic package available (OUTLINE DWG FD-2) gs special order only. Consult factory. (OUTLINE DWG JE) ’ 3-22

Ge) DGM181-191 — High-S - gh-Speed CMOS Analog Switches FEATURES GENERAL DESCRIPTION ¢ Pin and Function Replacement for DG181 Family The DGM181 family of CMOS monolithic switches utilizes * Meets or exceeds all DG181 family specifications _Intersil’s latch-free junction isolated processing to combine with monolithic reliabiliity the speed of the hybrid DG181 family with the reliability and + Low power consumption low power consumption of a monolithic CMOS construc: * nA leakage from signal channel in both ON and __ tion. These devices, therefore, are an ideal replacement for OFF states the DG181 family. * TTL, DTL, RTL direct drive capability . The DGM161 family has a high state threshold of 2.4V; © tom tof <150n8, break-before-make action devices-which have a threshold of 2.0V (the DG181 speci- * Grosstalk and open load switch isolation >50dB at _‘“iation) can be selected and are available as the DGMS tOMMz (750 load) « Series — see ordering information. Both series meet or exceed all other specifications of the 3 . DG181 family. No’ quiescent power is dissipated in either the ON or OFF state of the switch.!Maximum power supply current is 10uA from any supply, and typical quiescent currents are in the 10nA range. OFF leakages are guaranteed to be less than 200pA at 25°C. * SCHEMATIC DIAGRAM (Typical Channel) ovt = ere E =e a 1000 = = vw W w So'S5 i vt U ov + ano % OF DGM182 ORDERING INFORMATION oom S 181 A A STANDARD] SELECTED | tosioq) PART PART MAX TyPE | NUMBER | NUMBER | AT 25°C Dual SPST | DGM181Bx| DGMS181BX 50 I Te METAL OAN DGMi82Ax| DGMS182ax | 50 Utepmn Flat Pack DGM182BXx|} DGMS182Bx | 75 | Sleroxr or Dual DPST | DGM184BX| DGMSt84Bx | 50 : DGM185AX] DGMS185Ax | 50 ‘TEMPERATURE RANGE DGM185BXx| DGMsi85Bx | 75, A. MILITARY 5570 T0 + 2570 spoT | DGM187Bx| Dams1s78x | 50 . on“ DGM188AX| Dams188ax | 50 DGM188BXx | DGMS188BX 75 7 DEMIGE TYPE Dual SPDT | DGM190BX| D@MS190BX | 50 | 2 ornon DGM191AX| DGMSi91AX | 50 bemi918x| pemsis1Bx |__75 - onoe image oevven . 3.23

Vo-Vo eee eeeeeees S8V0VINGVQND eee esses 20V 825 (DIP) mW Vo-Vs ceeeecseeee #2200 GND-V™ ee eee 27V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the: operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability, ELECTRICAL CHARACTERISTICS (v + = +15v, V> = -15V, V.=5V, unless noted) . TEST CONDITIONS [eauciea [once ESBS Teme wer ewe we fume] meen | pers TT fT Pee ieee Vin="OFF” paws ee ieee | Vin “OFF” Pence pete | pee Vins "OFF" Toe Tsien) | DGMTOY, a4 Tar OTT 80 too [na [Ves “78¥.vin="ON” | [ bers Pome eeeere tf oes ets =O] [i pa ee eee a TS CS OE OO EB OGM182, 185, 188, 191 300 ‘See suitching time test circuit ea 7 a a ‘DGMiBT, 162, 184, 165, SpF typical [p=W=0, f=iMee | “GEF Isolation [-———_ypealy > $008 at Tor a CO | . a C= OO vn=5V 3 a oo i a a a a LO ¥ fe} sr a CC OO a NOTE 1; See Switching State Diagrams for Vin “ON” and Vin “OFF” Test Conditions. ELECTRICAL CHARACTERISTICS . MAXIMUM RESISTANCES (rosion) MAX) epee |e Lo | DEVICE MILITARY TEMPERATURE TEMPERATURE UNITS CONDITIONS (Note 1) NumBer _[—s5-C [425°C | + 128°C | ~20°C [ +25C] vase | vt 215V, Vo = —15¥, VL=5V DGM181 50 50 7 Vp = =+7.5V DGM182 50 50 iy 75 75 100 Vp =-10V DGM184 50 60 75 Vo= -7.5V pem1es | 50 EY) 75 75 75 100 Vp= = 10V Ig = —10mA DaMt87 50 so |, 75 Vo= -7.5V Vin=“ON” DGM188 50 50 roy 75 1% 100 p= ~10V DGM190 50 50 75 Vo=-7.5V DGM191 50 50 75 75 75 100 Vo = —10V APPLICATION COMMENT: The charge injection in these switches is of opposite polarity to that ofthe standard DG180 family; but con- siderably smaller. 324° :

SWITCHING TIME TEST CIRCUIT ‘switching time test circuit. Vo is the steady state output with ‘Switch output waveform shown for Vs = constant with logic switch on. Feedthrough via gate capacitance may result in input waveform as shown. Note that Vs may be +or—as per’ _ spikes at leading and trailing edge of output waveform. . LOGIC INPUT FOR “OFF” TO “ON” CONDITION (0G180/181/182 SHOWN) Logic av . INPUT tr<tons- 1.5V t#<10ns ° . | SWITCH yg. : INPUT ~ 1 0:8Vo. . SWITCH 9 0.10 3 oureuT ton toff ve ve . Psy ? 18V SWITCH SWITCH 1 D1 OUTPUT INPUT 6 o o © Vo . R IN R CL Yo=Vs gt _ " 4 ) > IL L RL "ps(ony LoGic ° INPUT = = ® (REPEAT TEST FOR ) 6-15V ALL CHANNELS) : I v- SWITCH STATES DUAL SPST DUAL DPST SPDT DUAL SPDT Damisi/ie2 Dom1a4/185 Damiazi188 Dem190/191 TEST CONDITIONS TEST CONDITIONS TEST CONDITIONS TEST CONDITIONS [__pamseiez | [ bamieatas Vin“ON"=0.8V_ |All Channels | [Vin"ON" =2.4V> | Alt Channels: [Vin“ON” = 2.4V+ [Channel 1 Vin“ON" =2.4V+ [Channels 1&2 Nin“OFF" =2.4V+{Channel2 | | Vjy"OFF”=2.4V+IChannels 3 & 4 Vin"OFF” = 0:8V | Channel 1 Vin"OFF” =0.8V Channels 1 & 2 . + FOR SELECTED DEVICES, LOGIC "1" INPUT = 2.0V. 3-25

. PIN.CONFIGURATIONS & SWITCHING STATE DIAGRAM DUAL SPST (DGM181, 182) Metal Can Package Flat Package (FD-2) Dual-In-Line Package se 1 “ 8: ——F . Ly «: Ss A® o- 2 fi A on A a poof. ott vo: Ce eae [fa] oe o @ £3) ms a note ae | ; + ne Cf] A f eee seGl A A fainc mw Qo eo v nef] YO [5 ne ne} () () fre OGG ero woe TE ne mo Ta) me vw voto: — vi 2) v- u z =] | 2 ono vw [3] ano {OUTLINE DWG TO-100) SWITCH STATES ARE FOR LOGIC "1" INPUT {OUTLINE DWGS DD, PD) DUAL DPST (DGM184, 185)

3 Flat Package Dual-in-Line Package

ss 2 bs a as: oof Th ne oa oc bo oC vy BY 4 im s Gy} 3] cwo ese) ee ae Bo We CTE HOHE oGpstet BO fiw vcoy —! ne] O 4am . : =a: 1 7 2 s ns ee eT i a oa (OUTLINE DW FD-2) SWITCH STATES ARE FOR LOGIC““1" INPUT (OUTLINE DWGS DE, PE) SPDT (DGM187, 188) Metal Can Package Flat Package (FD:2). Dual-In-Line Package ma nee ve ne La nc

1 Oe « A ft Ai

° ne] HE xe ne [E] [3] we *Or—8 Ore oot ee ee x@Dor’ Or sof ges sf} ts . t = i KOO ow woot} Dp rae ED fine vw veo - ‘——h ve [3] v- we eno “Ey ono. (OUTLINE DWG TO-100) SWITCH STATES: ARE FOR LOGIC “1” INPUT {OUTLINE DWGS DD, PD) 7 . DUAL SPDT (DGM190, 191) Flat Package Dual-In-Line Package es ot ae z i wef} [i] mi oye ote c O or Bo : Bs [5] ho > fe carey r ri ae es Et Yon & ea eo se), . moot CHE: i fv a P* v- ne] § QO) qam eer i, A oe SWITCH STATES ARE FOR LOGIC “1” INPUT (OUTLINE DWG FD-2, 3-26 (OUTLINE DWGS DE, PE)

. is oy CONSULT 77 =a rel ml FACTORY . . baal ; ‘DGM188 “a AA a Ei

; Analog Switches FEATURES GENERAL DESCRIPTION . « Switches Greater Than 28Vpp Signals With + 15V ‘The DG200/IH5200 solid state analog gates are designed us- Supplies ing an improved, high voltage CMOS monolithic technology. ¢ Break-Before-Make Switching tof 250 nsec, ton They provide ease-of-use and performance advantages not 700nsec Typical previously available from solid state switches, Destructive » TL, DTL, CMOS, PMOS Compatible latch-up of solid state analog gates has been eliminated by © Non-Latching With Supply Turn-Off INTERSIL's CMOS technology. © Complete Monolithic Construction ‘The DG200 is completely spec and pin-out compatibte with * Industry Standard (DG200) the industry standard device, while. the 1H5200 offers ‘Improved Performance Version (1H5200) significantly enhanced specifications with respect to ON and OFF leakage currents, switching times, and supply cur- rent. . SCHEMATIC DIAGRAM (12 DG200/1H5200) PIN CONFIGURATIONS — CERDIP & EPOXY. 5 aq ‘5 | DUALAN-LINE PACKAGE METAL CAN'PACKAGE = | - | ar ou (outline dwgs JD, PD) {outline dwg TO-100) ay a al * perms Meas | ow sve Of bsg Byo-5 Ou oie ew | YY Fa fester ano) (D Voce 2 . ae eid Fa ne ROS MC fe we el = vq [5 vase ° ‘Top view" INDUSTRY | IMPROVED FLAT PACKAGE TEMPERATURE STANDARD| SPEC S09 FOZ part _|_DEVICE | mccce | RANGE (outa owa FO) Metal Can. ow VV emsrnare) [DG200AK — |THS200MJD |[14Pin CERDIP|-55 to +125°C | ne = we ; [DG200AL — [IH5200MFD 14-Pin Flat Pak|--55 to +125-C | so pe 10-Pin a To TH5200ND ror viEW THS2001FD_j1a-Pin Flat Paki=25 to + 85°C are pe20oc) | iHs200CPD |1+Pin y Eeay OP Oto +70°C . : 3-28 .

VIN“GND occ ccectteeee sees snteeeeeeees <20V {All Leads Soldered to a P.C. Board.) Derate émW/°C Above 75°C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those Indicated In the operational sections of the specifica- tlons is not implied. Exposure to absolute maximum rating conditions for extended pPerlods may affect device reliabillty. pa200 3 ELECTRICAL CHARACTERISTICS (@25°c, v+ =+15v, V— = -15v) [SYMBOL | CHARACTERISTIC | —55°C +125°C | ol—25°C] +25°C | +70°CI+85°C CONDITIONS {intone [input bogie Curent [x Ts PsP a a [ta [nav Input Logie Curent [TY [Pt aa [Winey Tosjen) | Drain-Source On 70 70 700 Ts=T0mA Resistance Vanatog = £10V_ ‘Channet-to-Channel 30 sion) Matoh (typ) Vanacoc | Min. Analog Signal 2 215 Vv . Handling Capability : loorF} ‘Switch OFF Leakage nA | Vanacoa = -14V to Current +14V, Is(oFR. ‘Switch OFF Leakage nA” | VanaLoe=—14V to Current +14V TON) ‘Switch ON Leakage nA | Vp=Vs=~14V to tlson__| Current +uV ton ‘Switch “ON” Time PL=TRO, Vanaloe | =~10V to +10V See Fig. A ‘Switch “OFF” Time RL=1kQ, Vanatoc = -10V to +10V See Fig. A Gharge injection fT a8 0a seer | Min. Off Isolation f=1MHz, Ru= 1009, Rejection Ratio C.s5pF See Fig. 6, (Note 1) . Wa + Power Supply. 1000 1000, 1000 A | Vin=0V.or Quiescent Current * Vin =5V We — Power ‘Supply. 1000 1000 1000 ry Quiescent Current : Min. Ghannet to ‘One Channel Off Channel Cross (Note 1) Coupling Rejection Ratio Note 1: These parameters are not tested in production. 1 3.29 :

. Figure A Figure B . Figure © avniog west ‘ANALOG INPUT anlornel y w + 10 bogie pur wt 1 J wt _ roa JyJtt eur meu = oF T a. 0.90098 T Lo, ‘oan 1H5200 ELECTRICAL CHARACTERISTICS (@25°6, v+ = +15V, V~ = -15V, Vrer open} 7 -, MINIMAX, LIMITS, PER CHANNEL MILITARY COMMERCIAL/INDUSTRIAL TEST [SYMBOL | CHARACTERISTIC | —55°C | +25°C | +125°C| o/—25°C | +25°C | +70°C/+85°C | UNITS] CONDITIONS [tayow | Input Logie Gurrent [1 [oy | a Ts a a [Veoav [more [Input Logic Gurent [1 Ta | a yt Tt Pv [av osjen) Drain-Source On 70 70 f=, ™ | Tg= Toma Resistance Vanauos = *10V Tosjen ‘Channel-to-Channel 28 30 a + __ | osieny Mateh (typ) typ) VanaLos | Min. Analog Signal #15 215 v =__| Handing Capability ‘Switch OFF Leakage 02 nA | VanaLog=—14V to Current +14V 1SOFF) ‘Switch OFF Leakage Pit | Vanauos = —14V to Current #14V Toon | Switch ON Leakage 1 1 700 Vo=V5=~14V to. +lgow | Current +4Vv 4 ‘Switch “ON” Time OT 4S | RL=1K®, Vanatoc 7 : = —10V to +10V See Fig. A ‘Switch “OFF” Time 04 RL=1k2, Vanatog = -10V to +10V See Fig. A ° [Qos | Chargeinjection [| 6 fT to mv seerig.e | Min. OFf Isolation T=1MHz, Ru= 1009, Rejection Ratio C.sSpF : See Fig. 6, (Note 1) Quiescent Current 4 Vin = SV. We = Power Supply [| 700 10 100 yA . Quiescent Current cCRR Min. Channel to One Gharinel Off Channel Cross (Note 1) Coupling Rejection Ratio . Note 1: These parameters are not tested in production. 3.30

DG200/IH5200 - 9) INTERSIL TYPICAL CHARACTERISTICS CHIP TOPOGRAPHY Thgion) vs Vo and Toston) VS Vp and Power | ‘Temperature Supply Voltage FPS es ooo Ly ‘ yp "HEEREER] yg eH Pee =o i Gee of oH > i Hime 7 eee SS See 6 Be oS = BEES GEESE? a — aL EE eC, 7 Io Injen) vs Temperature* Is(ott OF loot == | . vs Temperature ner = + | | 10 ee F :opeee ——— = SS 1 = Wwe 2S 2 == = #2 oo 2 cr | SSS Ft aaeseeanes § eee et aye : eS | Bay jsaumuenenal § oS NOTE: Backside of chip of common to V+. ‘T= TEMPERATURE (°C) . ‘7 — TEMPERATURE (°C) eee

APPLICATIONS

‘The DG200 has an internai voltage divider ‘setting the ve TTL - ‘CMOS TTL threshold on the input control lines for + 15V on Wl ‘Supply Resistor Resistor V*. The schematic is shown here, with nominal wy (ka) (kay . resistor values, giving approximately 2.4V on the Vage 78 — pin. As the TTL input signal goes from + 0.8V to. +2.4V, 12 400 Q1 and Q2 switch statés toturn the switch ON and OFF. ors 51 If the power supply voltage Is less than + 15V, then a 49 84) resistor needs to be added between V* and the Veer +8 en” pin, to restore + 2.4V at Vagr. The table shows the value 47 418 of this resistor for various supply voltages, to maintain TTL compatibility. if CMOS logic levels ona +5V ‘sup- . ply are being used, the threshold shifts are less critical, ve ceteMy but a separate column of suitable values is given inthe = table. For logic swings of —5V to +5V, no resistor is needed. Sad xt In general, the “low” logic level should be <0.8V'to pre- . . ar aid t vent Qi and Q2 from both being ON together (this will * cause incorrect switch function). With open collector eka logic, anda low value of pull-up resistor, the logic "iow" - level can be above 0.8V. In this case, INTERSIL can sup- = “ ply parts with thresholds > 1.5V, allowing the user to a2 “ define the “low” as <1.5V (consult factory). The Vaer photeenon point should be set at least 2:6V above this “low” state, INPUT RESISTOR ‘or to >4,1V. An external resistor of 27k2 between V+ and Vper is required, fora + 15V supply. - = 3.31

• Quad SPST CMOS Analog Switches FEATURES > GENERAL DESCRIPTION . © Switches Greater Than 28Vp-p Signals With + 15V- ‘The DG201/1H5201 solid-state analog gates are designed us- ‘Supplies: .°> : ing an improved, high-voltage CMOS monolithic technology. © Break-Before-Make Switching tox¢= 250nsec, ton= ‘They provide ease-of-use and performance advantages not Typically 500nsec. oe previously available from solid-state switches, Destructive - © TTL, DTL, CMOS, PMOS Compatible latch-up of solld-state analog gates has been eliminated by + Nor-Latching With Supply Turn-Off ____ INTERSIL's CMOS technology. : * Complete Monolithic Construction The DG201 is completely spac and pin-out compatible with © Industry Standard (DG201) the industry standard device, while the 1H5201 offers: © Itmproved Performance Version 1H5201 significantly enhanced specifications’ with respect to ON : and OFF leakage currents, switching times, and supply cur- 6 : rent: SCHEMATIC DIAGRAM (% DG201/1H5201) CHIP TOPOGRAPHY 2 aN Ds — - = 2 = er ou =" IIS = = Ad . aS a ri ow vrer i Sg) ono aie geo : ~— oly f we eicetry eee ee "ie eo ¢ TED pe * Cae a= 25" wrt + a bz Na INS D1 ove NOTE: Backside of chip common to V+. ORDERING INFORMATION PIN CONFIGURATION (outine awgs Jz, PE) DUAL-IN-LINE PACKAGE ~ INDUSTRY } IMPROVED: TEMPERATURE wore wem STANDARD| SPEC RANGE an za iad =i PART DEVICE & Gy {13} oa . |baao1aK [iHezo1MJe | 16-Pin CERDIP | 55°C to +125°C | x4 eon ~ Be Plastic DiI 7 mee “A we . ‘SWITCH OPEN FOR Logic "1" INPUT 3-32 :

VAEFAV~ eeeeeeeetsseeesessssssseeserseees <33V Derate 6mW/°C Above 70°C VREF-GND 2.0... eceeseeseceeueueeeeeseees S20V VINGND oo i.cececeeeveeeneeeeeeeeeeeererees 6 20V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, ‘and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica- tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device rellability. DG201 3 ELECTRICAL CHARACTERISTICS (@25°c, v+ = +15v, V— = -15V) Test |_symBoi] characteristic | ~s5°¢ | +26c [st25- [ore [+a5-c | +70°C | CONDITIONS | _tnwow [Input Logie Current [7 [a Vin=oav [ior [input Logic Current [FTP 2a a a Resistance Vanatoc = + 10V Pete et rar Tosiow, Match tye) (yp) [fine | | TPT Handling Capability [er [eee | ee ee ee Current +4 Current +14. eee ee To ee +lgon_| Current ee ee =~10V to +10V See Fig. A Switch “OFF” Time | 05 S| PL=Tk®, Vanatoa =-10V to +10V | Quay [Charge injection Pag a0 a a = Rejection Ratio Cus5pF See Fig. C, (Note 1) Quiescent Current |= | secede | [RE [ [ae ee fae | Quiescent Current ie Eee Channel Cross. (Note 1) Coupling Rejection Ratio Note 1: These parameters not tested in production. \\ 3-33

TEST CIRCUITS . : Figure A Figure B Figure C = x LoGic INPUT 1H5201 ELECTRICAL CHARACTERISTICS (@25°C, V+ =+15V, V~ = —15V) - [remenannes |} array — connie — TEST SvBOL | CHARACTERISTIC | ~ssre | +asre [vise | ore | vaste | +70°e | conomons [Choe [input tosis Gurent [1 1 Pt 7 ts [tA [neon input Logie Gurent [tpt ft Pt] ta nena Drain-Source On Fy 400 100 125 a Is=10mA Resistance . Vanaos = + 10V. ‘Channel to Channel Py ial foson) Match (typ) (typ) Vanaioc | Analog Signal Vv Handling Capability Toorh’ | Switch OFF Leakage 1 nA VanaLoe = —14V to Isorm | Current . +14V Toxon ‘Switch ON Leakage 400 Vo=Ve=214V + lsjony Current ‘Switch “ON" Time 0.75 “s RL =1k0, VanaLoc =-10V to +10V See Fig. A tort ‘Switch “OFF” Time “ws RL=1k9, VanaLoc =-10V to +10V . | See Fig. A Min. Off Isolation ‘f= 1MHz, Fi, = 1009, Rejection Ratlo C.s5pF See Fig. C, (Note 1) + Power Supply 1000, 75 1500 1000 1000 pA Vin =0V to 5V. Quiescent Current + — Power Supply 10 10 400 vA Quiescent Current. CCRR’ ‘Min. Channet to One Channel Off Channel Cross (Note 1) Coupling Rejection Note 1: These parameters not tested in production. - 3-34

DG201/1H5201 - ESIINTERSIL TYPICAL CHARACTERISTICS w. ooo coo 8@ otto 82 wot g2 oo 22 wre

38 Coco 38 Sooo

$e Coot 22 booed = cs > = ae PERSE see 55 ® Cpa coer Co '@ 0 [Cacveesienv= tev 3 arene hee . Be HEE] ear) WU kehees Abate “0-0-5 0 6 0 Ais =8 08 10 45 Vo — DRAIN VOLTAGE (VOLTS) Vp — DRAIN VOLTAGE (VOLTS) . ———— 0 Ss === ——— gt a ge | 3 #8 ooo ge CC

3 SS ==

| ig) eee eee eS : eS ig FRREREEEES pe w See § oie SS ee SS : a ee | a ee S ol LLP TT TTT BZ omnL LTT TTT TTT 4s 65 8S 7055 Zs Wes a5 105 Tas ‘T — TEMPERATURE (°C) ‘T — TEMPERATURE (°C) eee Using the Vac¢ Terminal "The DG201 has an internal voltage divider setting the VF TL Mos TTL threshold on the input controt lines for +15V on ‘Supply Resistor Resistor V*. The schematic is shown here, with nominal ” (ka) (ka) resistor values, giving approximately 2.4V on the Vacr 78 — — pin. As the TTL input signal goes from +0.8V to + 24V, 412 400 _ Q1 and Q2 switch states to turn the switch ON and OFF, +10 61 If the power supply voltage is less than +15V, then a +9 4) 4 resistor needs to be added between V* and the Vagr +8 en oa pin, torestore + 2.4V at Vage. The table shows the value 47 18 18 of this resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels ona +5V ‘sup. . ply are being used, the threshold shifts are less critical, ween but a separate column of suitable values is given in the — table. For logic swings of — 5V to +5V, no resistor is . needed. a Seva bie) In general, the “low” logic level should be <0.8V to pre- on Vag vent Q1 and Q2 from both being ON together (this will . cause incorrect switch function). With open collector ko Jogic, and a low value of pull-up resistor, the logic “low” level can be above 0.8V. In this case, INTERSIL can sup- ply parts with thresholds >1.5V, allowing the user to a define the “low” as <1.5V (consult factory). The Vacs orca son : point should be set atleast 2.6V above this “low” state, INPUT RESISTOR or to >4.1V. An external resistor of 27k2 between V* and Vper is required, for a + 15V supply. = 3:35

FEATURES GENERAL DESCRIPTION * Switches Analog Signals up to 20 Volts Peak-to- ‘The 1H5009 series of analog switches were designed to fill Peak the need for an easy-to-use, Inexpensive switch for both in- dustrial and military applications. Although low cost Is a * Each Channel Complete — Interfaces with Most primary design objective, performance and versatility have : Integrated Logic not been sacrificed. * Switching Speeds Less than 0.5ys Each package contains up to four channels of analog * Ip(orr) Less than 500pA Typleal at 70°C gating and is designed to eliminate the need for an exter- nal driver: The odd numbered devices are designed to be * Effective rasan) — 5¢ to 500 driven directly from T@L open collector logic (15 volts) © Commercial and Military Temperature Range while the-even numbered devices are driven directly from Operation low level T2L logic (5 volts). Each channel simulates a SPDT switch. SPST switch action is obtained by leaving the diode cathode unconnected; for SPDT action, the cathode should be grounded (OV). The parts are intended for high performance multiplexing and commutating usage. A logic “0” turns the: channel ON and a logic “1” tums the channel OFF. PIN CONNECTIONS ‘

15008 Moston s Top (EBS) sons {rosrons 1000) (38) 1H5013 (rpsioxy= 1000) (8)

1H! (rosiony = 1500) 1H5012 (rpsioxy $1509) 1H5014 (rosiony $1500)

14 PIN DIP PPP, A 16 BIN DIP PE PEE, 14 BIN DIP oe

te re ' - | ‘ so P ons Lo oe Lo te | : rt : rt | sched a ee 4 s Tr "y. mo “ — 6 Jt noel a me bla tre . , oe ae IHSD15 fosow = 1000 (82) 1H15017 (Fpajom $1002) (a3) 1H5019 (ose 1000) (a2) fosion) = 1H5018 (r¢ 31500) DWGS i (te = 1509) DWGS,

18 PIN DIP PE PEE, 8 FINDIP PO, PA BPINDIF PE, PAE,

‘te * a bets (e800 5 OOO (oS) (802s. oss Om ‘OUTLINE (osony = hy 1H5024 ("peony = 15 ( nes ) agRE (ese (annem (SER . ei \\ {(Note: Numbers In brackets refer to CEADIP packages.) . 3-36

IH5009 — 1H5024 (@INTERSIL ABSOLUTE MAXIMUM RATINGS Operating Temperature . _ - SOOGC Series... ee. eeeeeeseeeeeee OCHO + 70°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is nat implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ; ELECTRICAL CHARACTERISTICS (per channel) . yest Tare on 35°C 25-6 wl copimions [°c ) “70°C (0) on 2 sannuax |W wae | max [inion [Feurcurencon Tat va iiig=ana [ot] | or | we | Input Coren OFF SV Logie Cts! Vin= #454 vas erevy ea [oa [os | [na [sony —|enanoel contr vaiansGN_ | sV Laie Ox} See gu & Ned | | v [wore [chanel consi yoivaeOrF | 97 toi exts| Bee Figue snows [as | | ~as [as | [tower [testooe Curomorr "sv tase us| Wye +tvivasstov| oe | ae os |e _| [xox [tka Girearon “avrg a i | Seo Faure 344 [iso] se ‘| see Fgwes 344 jae xe NOTE 1: (OFF) and (ON) subscript notation refers to the conduction state ofthe FET awiteh forthe gven test. NOTE 2: Refer to.Figure 2 tor deflation of terms, NOTE 2: Vow and Viner are test conditions guaranteed by the teats of respectlvlyrosons ar! Iyoer NOTE 4: “SV Logic GKTS" applies to avon-numberad devices. : “BV Lople GKTS" applies to ode-numbeted devicea. eee Basic tosie ORDERING INFORMATION. LOSIC | packaces ce SD | a A SS cn ee a BS Ld sore = 5 | ve0erE soy oe PA — SPIN PLASTIOOP jHsoTS +18 | 0.000 PO — 1ePIv pLasriG OF cc Fe — TERI PLASTIC OD 014 a xckact—| Be een Gena or epoca Sow cums (ees Ys is | eee | 40 = erin conor fisois Ts | enema | YE — OPIN CERDIP (sow [18 [oop] TEMPERATURE RANGE ‘Ms MILITARY (~55°C to +126°C) pass | 2 +$ | s500Px © = COMMERCIAL (°C to 70°C) 18018 2 $18 _JEDEPA BASIC PART NUMBER a a TOY . fiasoas [18 T oovea_| [tasoze Ts Tore a Se a Se . NOTE: Mil-Temperature range (~86°C to +125°C) available caramle peckages ony 337

• JH5009 — 1H5024 : INTERSIL i TYPICAL ELECTRICAL CHARACTERISTICS (per channel) 7_========| 2 a Re -peeee | RE 3 === = a § vo ==-=c=== bee Se (SSS a= SSS f===-==—— : Sees 3 naan SESS eee Be LEVI TI g eth A wt ZiT TTT) 3“), -sobnes cunaent tna) s Fewpenarune ce) 2°. rewenntune ca)" veces ve vewenarone CROSSTALK MEASUREMENT CIRCUIT ca cibmnnuitzo reas evaLveD mor meaueneys TO toxe FY ef 3 2 — St. RON fom + -FETQN Bas | a g > eNO PO ae es 7 Zo - LTT 3 + Nr = ‘our pre Ty got A woo = MIL Poo fe = io a i Vin ©) 20v oko FETOF 00 5 pe a “Y t a a ae Ro t = Teweenatune aESuENeT yee, DEVICE SCHEMATICS AND PIN CONNECTIONS FOUR CHANNEL THREE CHANNEL. 1H5009 (rogionj $1009) IH5011 {rpgion) $1000) 1H5013 (rosion) #1009) 1H5015.(rpgion)s 1000) 1H5010 (rps;on) $1502) IHS012 (fosjon) S 1509) 1H5014 (rps(oy) = 1500) 15016 (rpsion) 1502)

14 PIN DIP 16 PIN DIP 14 PIN DIP 16 PIN DIP

a oe be ; dt bre & 8 re be se be 4 brs TWO CHANNEL SINGLE CHANNEL 1H5017 trpsion)s 1009) 1H5019 (rog;0) = 1009) 1H5021 (fpsion) = 1000) 115023 (ros;ow)s 100) 1H5018 (rosion $1502) 1H5020 (rogion = 1502) 1H5022 (roson) $ 1809) 1HE024 (Fo¢0n) $1802) SPIN DIP 8 PIN DIP 8 PIN DIP 8 PIN DIP. ” a 1 a 6 * 2 . 3 wos 4 2 ¢ ¢ . t L . 338

1H5009 — IH5024 INTERSIL LOGIC INTERFACE CIRCUITS sunioo union ceeeececeeen ow aM perenne oe t ] r you i : T woe ' H wut ' bn woe . H Las | ioe . ' <3 bone ! t H \\ an i : “|e be eee ° eer Se ° 1 ieee . a 1 OSM , MW ' i ! tema 125 . bernttese 775 Figure §. Interfacing with +5V Logic Figure 6. Interfacing with +15V Open Collector Logic APPLICATIONS (Note) . tn oye Me sone oO bl O vou [> ~isonmiaoio™ ~ 7 Pn cock H H FTO “cease” 2 19K i i : ht ; ee tS i i wet ! \\ Tours Hi i H ' ' : H wre 1 bonn-14 ae 1 bd ° a ma ° . i 1s He 2 i eee ' : Fadi 87 bs Gia GianacTenwnics ryncat ovr ' { ven L ocr 1 6700 dx santo. Woe maeee Saw ecueer NOTE: Additional applications information is given in Application Bulletins A003 “Understanding and Applying the Analog Switch” and A004 “The 6009 Series of Low Cost Analog Switches”. See also September '79.issue of Product Engineering “Analog Switching” by Paresh Maniar. 3-40 :

! LL Positive Signal Analog Switches FEATURES GENERAL DESCRIPTION * Switches up'to +20V inte High Impedance The 1H5025 series of analog switches was designed to fill Loads (i.e. Non-Inverting Input of Operational the need for an easy-to-use, inexpensive switch for both in- Amp.) dustrial and military applications, Although low cost Is a rimary design objective, performance and versatility have * Driven from TTL Open Collector Logic pany deaton oleate. © Iporr)<50pA © Tpsiony< 1500 . Each package contains up to four channels of analog * rosin) Mateh <509 ‘Channel to Channel Gating and is designed to eliminate the need for an exter- * Switching Speeds <100ns 3 . The entire family is designed to be driven from TTL open collector logic (15V), but can be driven from 5V logic if signal input is less than 1V. Aiternatively, 20V switching is readily obtainable if TTL supply voltage is + 25V. Normally, only positive signals can be switched; however, up to +10V can be handled by the addition of a PNP stage (Figure 11) or by capacitor isolation (Figure 10). Each chan- nel is a SPST switch. A logic “0” turns the channel ON and a logic “1" turns the channel OFF. PIN CONNECTIONS 1H5025 (rpgion) = 1009) 1145027 (rpsiony $1000) 1H5029 (rps;ow) = 1000) 15031 (tog(on) = 1000) 1H5026 (rps;on) $1509) 15026 (ros;on = 1509) 1H5030 (rosiony = 1509) 1H5032 {fos;on) 1502) . 14 PIN DIP 16 PIN DIP 14 PIN DIP 16 PIN DIP 92 95 gw Oo 92 97 Go gts 93 9s ow 92 qr ie ¢ ag Fs ; at tT “tg 3 3 2 He 2 3 cont Lidsta be _ br bbe bebe ba 1H5033 (rosin) < 1009) 1H5035 (rpsjon) = 1000) 1H5037 (roscon = 1009) 1H5034 (Foion) = 1509) 1H5036 (tpsionj< 1809) 1H8038 (rps¢ony $1500) 8 PIN DIP 8 PIN DIP 8 PIN DIP. 8 ea ae 718 ee on Fe) me “oy sop ft B04 ae : “ woh wind dae wad bea: bron NUMBERS IN PARENTHESES INDICATE CERAMIC PACKAGE PINOUT : 341

IH5025 — IH5038 - INTERSIL ABSOLUTE MAXIMUM RATINGS Operating Temperature BO25C Series... eee eeeeeeeeeees OCHO 70°C Drain Current «soso: sessessiscessecsesssssstize 25MA ——WoTE: Dissipation rating assumes device is mounted with al leads welded Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the ‘operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (per channel) : SPEEIFICATION LMT svMBoL ae) TC ‘ot 1 conomons [oct ass) a COC Channel contol vatageoN = | a__ [Soe Flgue 1 ws [is Ps . [¥inoen [Grannel Gonvel vouasearr | “A [See Flawe 3 a ; togiow [o‘amsouce nrensanep | sian non, ig=25% (9 ma [sem | so | | aimn | [orp [Famore ng Tak fase gue oso [oe oa | Suny [Charge nection | an [sew Fou s [reo | aa | Tape rae | ¥arorm) _[Sre8s Counting Reiection [a See Fours CT a [srosiong_[Cnanne!o Channel mpsiong Naien] All Vin=05V, gu mA 00 [m0 [| nina [NOTE 1 (OFF) ane (ON subsert notation refers to the conduetion eat ofthe FET sith fr tho gion test CC Peerwmeen | oumwes| She | moxaoe [isigoas eT 18 [0,000 | a Pa — spn ptastic Die [Hso2e a4 PD — 14IN PLASTIC DIE PES IPINPLASTODIP ao [inser Te | ogre pACKAGE —| DD — 14PIN CERAM dor On i ST ” BE — 4ePIN CERAM BIP (Special Oey On| 8028 4 30 — isin CeRDIP 32 — torn CERO basoea 3 [#2000 3 Tt 3 [sis sen re _| La TEMPERATURE RANGE +1082 j 2 IM=UILITARY (=55°C to +125°0) CI COMMERCIAL Octo 470°O 16034 [25 [spore | saci Pon WuWBER [iss [2 is [secera 16006 [2 | +8 | sepe ra 15057 ee T5098 1 NOTE: Mi-Temperatura range (~85°C to +125°O) avallable In coramle packages oniy. 3-42 :

IH5025 — IH5038 ESINTERSIL TYPICAL ELECTRICAL CHARACTERISTICS (per channel) : Ipjorr) VS. TEMPERATURE Ipton) VS. TEMPERATURE at ea CO toma Tt ty = matt LL i [7 FA

3 LI bad Bzan 5 100pa TA = loion,

100 pA Bee anee 10 pa 248 \\ CELL “TT LTT TTT TI ERE; 25. +25 +75 +125 -25 425 +75 4125 TEMPERATURE (°C) TEMPERATURE (°C) REJECTION V8 FR QUENCY Rosion} VS. vn TTT LIT TTA 12 175 36 ) é 78 * Leva ab A BCC ati os LTT LEE TTY | | Co) ° 1KC 10KC 100 KC 1Mc ov O.5V 1.0V 1.5V ca . FREQUENCY Vin TEST CIRCUITS : / . ve our aw “pro sooe one oe Vow = ul ra Figure 1 ” Figure 2 = 10,000 000 sev fy E 1-4 veo: wil bux t Figure 3 ~ Figure 4 3-43 .

1H5025 — 1H5038 Il fi DEVICE SCHEMATICS . FOUR CHANNEL THREE CHANNEL 1H5025 (Fpsjon = 1009) 1H5027 (Fosiéuys 1000) + 18029 (rosionys 1009) 1115031 (Fosion $100) TH5028 (tosiony 1509) 115028 {Tpejony = 1800) 1H5030 (togjony = 1509) 1115022 (rpe;ony = 1500) 14. PIN DIP 16 PIN DIP 14 PIN DIP 16 PIN DIP . ‘ 2 6 . TWO CHANNEL ~ SINGLE CHANNEL . 15033 (rpsion) = 1009) H5035 (rpgion) 1900) 115097 (rosjor = 1000) 1H15034 {reson 1500) 1H5036 (rpsjon) = 1500) 1H5038 rosiony = 1809) 8 PIN DIP 8 PIN DIP. 8 PIN DIP (ae yor 3) 4(a) . “ oe (11) as . “a «aro 1920 “Po a -s & bo wn be sso 3-44

‘they may be driven by floating outputs. This family is used with SV TTL logic, a maximum of + 1V can be switched. of an opérational amplifier, while the IH5009 series is used “referral resistor” can be placed between gate and source. adequate safety margins to insure proper switching action. thus with + 18V at the logical input, and a +10V signal in. _be gated. necessary positive voltages for proper gating action. . Figure 5. Interfacing with +5V Logic Figure 6. interfacing with +15V

1H5025 — IH5038 BINTERSIL , prota anno Few sen sume i St werosan Vavascay_S0ieh \\ evra soy _voye F—Yov = one = I 1 nck ; wy Le Sxocie x Tan Tass p hr + * ° H v7 ow 1 \\ moc Has? smiron 1 H = : - wma = sav : hoon wt Lb . 3 Figure 7. Multiplexer from Figure 8. Sample. and Hold Switch Figure’. Switching upto +20V0 0” Positive Output Signals with T2L Logic Transducers +. S10Ks . edo Posie ‘ouTeUT - ee PO TDT Tea G Su 1 | ped ame 1 et $e S10 i ay { {ike te = | i a \\ sine, 19 sone 1 \\ sagy Sone bRS Hoos ww OT " i ! | 1 | ' \\ =F! busnese 7 4 Ea aw oy ely toate wv ca outa wv . Bo naw, tt A — 3 Note 10 STEW 10 VAC 20m: 0 INCREASE SV SUPPLY TO sI0V, AP GREASE TW Shen eae civ SO, Figure 10. Switching Bipolar Signals with TAL Logic

1 U Sthpur ss

1. Sete anent aerone axe IBerOne m Hauneo. ao een 3

Figure 11. Switching Bipolar Signals with TL Logic (Alternate Method) Eitan ToFlounge 9. on 1s NOULD BE URED. Figure 13. Gain Control with High Input Impedance

@ 1H5040-1IH5051 Family FEATURES. GENERAL DESCRIPTION © Switches Greater Than 20Vpp Signals With +18V Supplies The IH5040 family of solid state analog gates are designed © Quiescent Current Less Than 1A using an improved, high voltage CMOS monolithic tech- © Overvoltage Protection to #25V nology. These devices provide ease-of-use and perform. © Break-Before-Make Switching torr 200 nsec, to, 300 ance advantages not previously available from solid state Typed a ae NE Kon SOMES. switches. This improved CMOS technology provides input © TZL, DTL, CMOS, PMOS Compatible overvoltage capability to +25 volts without damage to the " tefeee Wi device, and destructive latch-up of solid state analog gates © Non-Latching With Supply Turn-Off Geni © Low rasion) — 352 has been eliminated, Early CMOS gates were destroyed when - power supplies were removed with an input signal present. © New.DPDT & 4PST Configurations . ‘The IH5040 CMOS technology has eliminated this serious © Complete Monolithic Construction systems problem. 15040 through 1H5047 Key performance advantages of the 5040 series are TTL compatibility and ultra low-power operation. The quies- FUNCTIONAL DIAGRAM cent current requirement is less. than 1A, Also designed ¥ ' into the 5040 is guaranteed Break-Before-Make switching, which is accomplished by extending the to, time (300 nsec [| TYP.) so that it exceeds tof time (200 nsec TYP.). This . insures that an ON channel will be turned OFF before an Py OFF channel can turn ON. This eliminates the need for ex- ternal logic required to avoid channel to channel shorting a Lc ] during switching. . JJ io Many of the 5040 series improve upon and are pin-for-pin and electrical replacements for other solid state switches, e oe nh} Boe FUNCTIONAL DESCRIPTION . Jpp& = . INTERSIL EQUIVALENT $ 5 PART NO. TYPE DS(on) (Note 1) 7 ~j] TH5040 SST 75x rf oe 1H5O41 Dual SPST 752 les 15042 SPOT 758 DG 188AA/BA Fy] Oe 1H5043° Dual SPOT 752 DG 191AP/aP 1HS044 ‘PST 762 . Fi oon} 15045, Dual DPST 792 OG 185AP/8P : 1H5046 DoT 750 — 1H5047 4PsT 752 had 1115048 Dus! sPsT 352 1H5051 Qual + SPDT 359 DG 190AP/BP NOTE 1. See Switching State diagrams for applicable package tHs040 JE equivalency. T— serie cenmic Di sul oder ny) Pin and functional equivalent monolithie versions of the DG181, FD2— 14-Pin Fiatork DG182, 0G187 and DG182 are available. Soe data sheet for Je = iePin GeRDIP this and also 1H181 to 1H191, Pe = tein Prete DIP TW T0-100 Meta Can {1H6081/2, 15044, 185948, 1HSOBO Only] ‘Temparaturo Range Mi altry =E5%C wo +128°6 C= Commercial °C 470°C {Basle Part Number . 3-48 ;

1H5040-1H5051 Family all OL, ABSOLUTE MAXIMUM RATINGS + 7 vive <33v (All Leads Soldered to @ P.C. Board) VieVin <30V Derate 6mW/"C Above 70°C . VL-GND <20V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to.absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (0 28°c, vt = +15 V, V~ = -15V, VL=+5V) Pyo | eurent ‘soe§ theo 180511 sina | Shoe nor 00 THHS08 hvu EOS) Va + Power Susply 1 1 10 10 10 100 “a ‘ono Quiescent Currant TEST CIRCUITS. FIG, A FIG. B ‘ FIG. C . onc hai . wag inet NOTE 1: Some channels are turned on by high “1” logic inputs and other channels ere turned on by low “0 inputs; however O.BV to 2.4V “ON” or “OFF” state. 3-49 ’ ‘

1H5040-1H5051 Family INTERSIL TYPICAL ELECTRICAL CHARACTERISTICS (Per Channel) rDston) ¥8 CHARGE INJECTION vs VanatoG "DS{on) ¥§ VANALOG SIGNAL POWER SUPPLY VOLTAGE (SEE FIG. B) Cy = 10,000pF ; « EET “et 7S | _| a co Pere Cory | ee tee te

3 Oper ete

» “SE eC CCC CEPR (EERE (=== sao

3 CROSS COUPLING r

NET ~— “y PREDaS SCGEahd | $0 i ATTERANCUET id ol ee NN | 7 Fa TTT rm D-> 1 [ave H it L | ‘SWITCHED i” ! om conn -amioe Hones game LOO ay sa a OFF ISOLATION vs FREQUENCY , Saohioti dt Poor ia [ Al | Your 20 t.. wt «gL Temes Spee |] = ‘THe 10M: 100H: tk 10k. TOOk IM = ee POWER SUPPLY QUIESCENT CURRENT i ; Pen FY 3 LZ LOGIC FREQUENCY @10% DUTY CYCLE tHe FIGURE G 3-50

1H5040-IH5051 Family . INTERSIL SWITCHING STATE DIAGRAMS. SWITCH STATES. (OUTLINE DWG (OUTLINE DWGS ARE FOR LOGIC “1” INPUT. FO-2) DE, JE, PE) {OUTLINE DWG TO-100) ‘SPST Ld 7 shoe | : Jor | a eye DUAL SPST . i uy oe wow 145041 (rps{on) <752) * a Dn 4, 1) b> mo “BF. ) mote . mod . eer) eD- > Loo . notte tyom aot e 4 SPDT “Moy (DG188 EQUIVALENT) | ¥ Fi Pn wow 1H5042 (rS(on) < 75%) Oe . $F ot orton not of et 200, sot ° Boop wo woth neh p> OT <T5G191 EQUIVALENT) OOS DUAL SPDT ve v y 1H5043 (rpston) < 752) Go fe cam ne tin Ee pre tie Ds D> ms E> OPST Ms fe Pu S . 115044 (rpg{on} < 759) he a a DUAL DPST wooo s, %, 1H5045 (rpg{on) < 752) i 2, f o> mobo "sot > * lS oes ERNE Bade bel meee a roa 3-51

1H5040-1H5051 Family _. -BBINTERSIL SWITCHING STATE DIAGRAMS (Cont.) . SWITCH STATES . . ARE FOR. LOGIC 1" INPUT. FLAT PACKAGE [FD-2) DIP (DE) PACKAGE ‘TO-100 a a 4 f2_fu H5046 (rpg {ON} <752) sof ——erthon = 1S ET cl ee oa noe] _oteleoe, toe oft toe. hot foo 1H5047 (rpg (ON) <750) > Sy eye ott ore] 00, . sot] erthago, nye sot} orale os ot ° Body DUAL SPST 4 v fe is $0 1H5048 (rpg (ON) <352) foe jum mob -> m >> ny fe > cs ig > N27 - 7 (DG184 EQUIVALENT) DUAL DPsT wy 3, 1H5049 (rpg (ON) <352) Pio fe mel D> mt "ot -> fom wo |. Moot (DG187 EQUIVALENT) spoT wow Safe “ ¥ 1H5050 {rpg (ON) <35Q) fee Jefe wot o oop not 0. Ao oe 204 © too {DG190 EQUIVALENT) DUAL SPDT ?, 1H8051 (rpg (ON) <352) ao af Pe BE | eine ° nop een Set Ration 382

1H5040-1H5051 Family BINTERSIL PROVED saueLe & HOLD USING 5H5043 sage Ll-> = 4 1 ed SR By . DP! fs 3 Bre ue. = D> - mn Using TAE cos swiTcH To DIVE AN ISS ESSER NETO ETS LO af “D> 12 stReoe EXAMPLE: If —Vanatog = ~10VDC and Vanatog = *10VOE «| D> 1 ey ioe vote ‘| : to re. n N ie ere, DIGITALLY TUNED . Low POWER ACTIVE FILTER “ ad ‘ee wer ‘ome rice! | Ges FG sense ; ase oo BT fee . ole ee oo Constant gain, constant Q, variable frequency filter which a =A provides Simultaneous Lovipess, Bandpass, and Highoass | _ a. . ‘outputs. With the component values shown, canter frequency TEs ome TE 3-53

i INTERS| IH5040-IH5051 Family all IL FOR INTERFACING WITH T2L OPEN COLLECTOR LOGIC. pronase | Fear, it I mio ntl oe j tose | yy . Losi 6 H ; i +15V Usvmgere Sima a FOR USE WITH CMOS LOGIC. . potter ™ \\ ot if 1 i | | ! exo | 1m GND t i y q | I 1 I I ! iF ‘Von | ews GATE v | v (eel 2k LOGIC INTERFACING a . , in 7 i | i | | i ! | | 1 1 ‘OND | Jw wtb | y Losic| 1 ‘ 1 i 1 ! we | iol \\ ‘18 Of gg IY, TERMINAL (enor) vox 3-55

1H5052/1H5053 ; INTERSIL MAXIMUM RATINGS VIVE ic ccecceeeerttterrtrreeeteeeees €33V Storage Temperature --ueeseseseceseies BB®CLOF1EO°C VIM ceeeeeeccecetsseerrsneetseerserees €90V (All Leads Soldered to a P.C. Board) . VUVIN cer ee tee eee rete ee tree eereeeeeeerees <30V Derate 6 mW/*C Above 70°C VIEGND occ eee icteeeeeeeeeeeeeeeeeerees <20V Stresses above those listed under Absolute Maximum Ratings may cause permanent dariage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (@25°G, V+ = +18V, V- = -18V, VL= +5V, GND=0v) [remem |] rae ce — Test conpmons |__svmpou[cuanacrenisric| “se [ +zse [asc | 0 [sare [roc | " [tony [put copie curent| 1] [tp a+ | +) ok] Wn VOCE OSD] [Finer | input conic Gurent| [ft Pn va ED | : Tosiony [Drain-Source On | 75 8 705 Tg= 107A, Vanalog = 10V 10 pesca pe fe |e [ee [ere teves =e fet | fat PT Riosiony Match (y9) [ne [enamel | | | OP PT fT Handting Capability Eee ee +siom_| Current : Switch “ON” Time Fi = Tk, Vapaiog= = TOVTO pe pees | ee Oe eee a i a +10V See Fig. | Qty" TCharge tajection [| as ao [See Fig 8 ‘Min, Off Isolation [= | f= 1 MHz, RL = 100, C. = SpF Rejection Ratio See Fig. G Note 1) + Power Supply 700 oA |" lamoedem | |? Pe pepe pets yl Power Supply =} = 10 BA Vioei5V,V~=-15V, Wa 45V ‘Quiescont Gurrent with GND. a er a Quiescant Current “Gnd Supply 700 [i [ecient | |? Pe |e Pe pepe Min, Channel to One Channel Off, Any Other ‘Channet Cross Channel Switches as per Fig. E }Coupling Rejection (Note) Ratio Note 1: Not tested in production. TEST CIRCUITS FIG. A. FIG. B FiG.¢ snog eur puacoa mur Tinea ote Lp ota > tL)>-/ = = woate Loeie = soe Be Sn sep006F T 1000 387 :

A. Floating Body CMOS Structure In a conventional C-MOS structure, the body of the "n” - channel device is tied to the negative supply, thus forming a ° reverse biased diode between the drain/source and the body MATERA (Fig. H), Under certain conditions this diode can become Bora our forward biased; for example, if the supplies are off (at eur ots ground) and a negative input is applied to the drain, Thiscan . ie have serious consequences for two reasons, Firstly, the Tt Ls diode has no current limiting and if excessive current flows, the circuit may be permanently damaged. Secondly, this ac diode forms part of a parasitic SCR in the conventional ~ C-MOS structure. Forward biasing the diode causes the SCR to turn on, giving rise to a “latch-up" condition. . FIGURE H Intersit’s improved C-MOS process incorporates an addi- 3 tional diode in series with the body (Fig. 1). The cathode of this diode is then tied to V+, thus effectively floating the body. The inclusion of this diode not only blocks the exces- sive current path, but also prevents the SCR from turning on. +400 oH B. Overvoltage Protection Floarwig noDy The floating body construction inherently provides over- anavoa . voltage protection. In the conventional C-MOS process, the anal | tor body of all N-channel FETs's tied to the most negative power supply and the body of all P-channel devices to the most Tt fe Positive supply (i.e., +15V). Thus, for an overvoitage spike of > £15V, a forward bias condition exists between drain and . body of the MOSFET, For example, in Fig. H if the analog . = signal input is more negative than -15V, the drain to body of the N-channel FET is forward biased and destruction of the device can result. Now by floating the body, using diode D1, FIGURE! the drain to body of the MOSFET is still forward'biased, but D1 is reversed biased so no current flows (up to the breakdown of D1 which is = 40V). Thus, negative excursions of the analog signal can go up to a maximum of-~ 25V. When the signal goes positive (= + 15V, D1 is forward bi- ased, but now the drain to body junction is reversed for the : N-channel FET; this altows the signal to go to a maximum. ot of +25V with no appreciable current flow. While the ex- planation above has been restricted to N-channel devices, anatoe ot the same applies to P-channel FETs and the construction ‘SIGNAL ° Your is as shown in Fig. J. Fig. J describes an output stage ils showing the paralleling of an N and P-channel to linearize om the rpsion) with signal input. The presence of diodes D1 and DRIVER ™ D2 effectively floats the bodies and provides overvoltage JL protection to a maximum of + 25V. y £ . qT o ve FIGURE J 359

• > 1H5052/1H5053 BSINTERSIL LOGIC INTERFACING [en 9 * | | I 1 i | . ! ono it | i + : i mn ‘ = +! [wrmeate ran FOR INTERFACING WITH T2L OPEN COLLECTOR LOGIC. pocsos ow ! Cu 70. . 4 ™ - MA | H “15v i oii LvTmgare ou TYP. EXAMPLE FOR +15V CASE SHOWN 3-60

1H5052/1H5053 ' @INTERSIL FOR USE WITH CMOS LOGIC. wanna m r vt t 1 | i i \\ t ano : ve 1 v- | | 1 ye | ; “ . | i x | | v lemoscate tomoscate " _ m 18V>V* >sv ee APPLICATIONS : PROGRAMMABLE GAIN NON-INVERTING AMPLIFIER WITH SELECTABLE INPUTS fs [> sex . a te | fs ve oa] ° aL SF onont-{ > vw aH ¢ fa. s= ose +p 1 TOT Te enor > 1 2. al 000! . owed Fp = Sea av co ACTIVE LOW PASS FILTER WITH DIGITALLY SELECTED BREAK FREQUENCY 3-61

APPLICATIONS (Continued) 4-CHANNEL SEQUENCING MUX ‘sequencer otconen anatoa swrren (earr BINARY COUNTER) * SEQUENCE 0 4 For i nese IF a= it I >-p sero D D>--7/ |» a Ta Pst spp--7] o | DUAL SR FUP FLOP TPT wan posses, rosomuires "Mu: onsera rhea snseto Truth Table (IH5052) SEQUENCER] SWITCH STATES OUTPUT |; (- DENOTES OFF) [P20 [21 | swi/swe[sws[swa] ° 0 ofo . 1 ° o}o 1 ypuse | 1] 0 4 2 pulses ol} 4 1 3 pulses 1,4 . 1 4 pulses alo A Latching DPDT . The latch feature insures positive switching action in response to non-repetitive or erratic commands. The Ai and Az inputsare normally low. A HIGH input to Az turns S and S2 ON, a HIGH to Ar turns Sg and S4 ON. Desirable for use with limit detectors, peak detectors, or mechanical contact closures. : ogy ov a fe ms ib 5, Dr-/ f ‘Truth Table (145052) aa) cours wan P| | commano | STATE OF SWITCHES rs AFTER COMMAND TD D> " ae 3 & Se $18 Se J . 0 ° same same unp amour sh Joo 4 on off wa J Tree owrace L> cure 1 0 off on cwos cow ey" 11 INDETERMINATE, ‘or ouracoo a : t—L)> os i g . 3-62

2) l IL IH5108 8-Channel Fault Protected CMOS Analog Multiplexer FEATURES GENERAL DESCRIPTION * Ultra low leakage— I pjo11;<100pA ‘The 1H5108-is a dlelectrically isolated CMOS monolithic * Power supply quiescent current less than 1mA analog muttiplexer, designed asal plugin replacement forthe log signal and similar devices, but adding fault protection to the : NoSCR ise range standard performance, A unique serial MOSFET switch en- 8 . sures that an OFF channel will remain OFF when the input + Break-before-make switching i Fi ible with DGS08, HI508 and AD7508 exceeds the supply rails by up to = 25V, even with the supply * Pin compatible wi , HIBOS ai voltage at'zero. Further, an ON channel will be limited to a * All channels OFF (I. «=< 100nA) when power OFF, for throughput of about 7.5V less than the supply rails, thus analog signals up to + 25V affording protection to any following circuitry such as op ° Any channel turns OFF (Ii.x=100nA)itinputexceeds amps, DIA converters, etc: Gross talk onto “good” channels . supply rails by up to +25V. Throughput, always is also prevented, 3 < +14V (+ 15V supplies) Abinar r i . ry Sbit address. code together with the ENable input * TTL and CMOS compatible binary Address and sows'selection of any one channel or none at all, These 4 ENable inputs inputs are all TTL.compatible for easy logic interface; the ENable input also facilitates MUX expansion and cascading. FUNCTIONAL DIAGRAM DECODE TRUTH TABLE . [ a]as [ao] en] onswircw] - XTX/]X] Oo NONE soo % O;o}o}4 1 O1o};i)4 2 S20—o-—% ofilol4 3 —, Ol1; ata 4 Ss 4Potol st 5 -%, vfo}a}a 8 “ our © afato}a z s%s0-——_0-—% afafe]a 8 Aay Ar, Az, EN Ses Logic 1" = Van=24V s _, Logic “0” = Vai $0.8V S10—o-—"o PIN CONFIGURATION (outtine dwg JE, PE) 1086. en [2] HS] Ae . ss 44 aa [ono Ao A ENGNABLEINPUD, | [z] v> LINE BINARY ADDRESS INPUTS : =: Bf Fa] ss G0 )ANDEN HI ABOVE EXAMPLE SHOWS CHANNEL § TURNED ON s [e Ss s [i sr o [aj fa]s - . oP VIEW [tnstescre [ote roe] “ean este , 3-63

@INTERSIL 1H5108 J ABSOLUTE MAXIMUM RATINGS a . Vin(AJEN)tOGrOUN oe. eeeeeeesseeeeeese+TISVUO15V Operating Temperature ..----- esse eeeee+++ 8510 125°C V4 tOGIOUN Looe cece eee e ee eeeenen eer ee seer ee BV VO tOGIOUNd ..ssseereesseesteeesscsseeeeceess =16V “All leads soldered or welded to PC board. Derate 10mWi"C above ‘Stresses above those listed under Absolute Maximum Ratings may cause permanent damage tothe device. These are stress ratings only, and functional opera: ‘lonof ie dovice at these or any other conditions above thosa indicated nthe operational sections of the specifications isnot Implied. Exposure toabeolute max- imum rating conditions for extended periods may affect devicarellabilty. ELECTRICAL CHARACTERISTICS v + =15v, v~ = -15V, Ven=2.4V, unless otherwise specified. NO maxims ["_wsurrx TT _icsurrix | . 3 msasuneD|rests| 11 M SUFFIX UGSUFFIX ‘TEST CONDITIONS ep] |e eee [ ae “ele lle [= [| fe. [eae . Ig=—10mA, switch on 6 1200 B00 Vp==10V Vai = 08, ig= —1.0mA Vann =24V : Brose 10 10 TostonjmaxfDSton)in g|feeen ‘rpsfony = eorex “PSionhrin Wn Yg= 2 10V 1 ‘os(onjavg. t Se ee eee Hq [a Joo [aos [50 [Por] 50] a a na Ven=0 a ad = switeh on [ope ee |e ee | . F [Is with Power OFF 1000 5000 Vt =V7 =0V, V5 = £25V, . 4 oA Ven =Vo=0V, Ap, Ay, Ap = OV or 5V £ Jisiorp with 72000 Vg = = 25V, Vp = = 10V|Sequence each T Jovervoltage (Note 1 switch Pe re ee | tn [lat fel=[ [el =| jfenen eee O Renton Breake 70 Ven= + 8V, Ap; Ay, Ag Strobed N [Betore-Make Vjy= #10, Figure 4 A [Delay Settling Ml rime C-OFF" Isolation Ven=0, RL = 2008, C, =3pF, Vg=3 VRMS,

12500 KH2

feu ts | [sf ot [oy ot yy Ven =0v, [Coom +} > |_|] fy fa140 KH2 [Cosen fp Ses fT | so, MHz, sweety + | v= | 1 {sooo | 70 [soo | [ooo [OY | Alive, ven=0orsv Ec aR RO cl Note 1. Readings taken 400ms after the overvaltage occurs. : 3-64

2 Feet

Figuré2. tipea (Break-Bofore-Make) Switching Test .

3 MT oVour x 10%

Figure 3. to, and toy Switching Test .

systems (see applications section). . Another, and more important, difference lies in the switching . Figure 5. Serles Connection of Channel Switches .

IH5108 APPLICATIONS INFORMATION (continued) , —Po— Ms hy sv TTUCMOS INVERTER 9 9 ‘TTUCUOSNOR GATE re a tHs108 hoett_] rouTors aso ra] 1 anatogineurs ® ts {> Tad’ na [| [ras] store ° aan in . i ovo ¥ 3 wisca ass OUT OFS D an 25 anacoa inputs * £ 4 ev DECODE TRUTH TABLE DECODE TRUTH TABLE [Aa] As [Ae [As [Ao [ON SWITCH * [Aa[As[ Aa] Ar [Ao] ON SWITCH Oj;O}O}O]0 st 1}/o};o}ojo si7 ol}ojoloj4 $2 t}o}ojal}4 S18 ofofolijo} sa 1fofol1jo] sie . O;o;ofri1 S4 a] O;oji}4 $20 O;O;1]0;0 $5 1/a;1]o]o s2t O;ojyrlofta 86 afo}1{oy4 $22 O;o;1}140 s7 qjojijiajo $23 O;oyr fits $8 apopryass7 ‘$24 O;1jojol+ $10 a{1}o;o}4 ‘$26 : O}1}o}1/0 si af1]o]a]o]. saz O;1so;isa $12 apa} o;1}7 $28 O;1}1/ojo $13 api} 1po}o $29 O;1 si joys si4 apap apoudr ‘$30 ol}t)t[rfo S15 tpaprprypo 831 Opt jr fria S16 tpaprpryd $32 . Figure 14, 1 of 32 multiptexer using 4 1H5108s and an JH5053 as a . ‘submuttiplexer. Note that the IH5053 Is protected agalnst overvoltages by the IH5108s. Submultiplexing reduces output leakage and capacitance. 369

• @UNTERS! IH5108 al Ik. APPLICATION NOTES : Further information may be found in: A003 “Understanding and Applying the Analog Switch,” by A020 “A Cookbook Approach to High Speed Data Acquisi- Dave Fullagar tion and Microprocessor interfacing,” by Ed Slieger - A006 “A New CMOS Analog Gate Technology,” by Dave ROO9 “Reduce CMOS Multiplexer Troubles Through Proper Fullagar Device Selection,” by Dick Wilenken . CHIP TOPOGRAPHY Si Ss S281 vo (eet) = : SSS a EN aM Se. wel i a : aul eo a Ao D pe 0.408 in Se) __ (2.74) mm Ss Se|m@ dul oc a] = er = TAC ped pee =—— ‘ ‘ ea . S; Ss Ss - vt GND . | oxttin | (2.82) mm_ : 3-70

FEATURES GENERAL DESCRIPTION . © Super fast break before make switching The 1H5140 Family of CMOS monolithic switches util- ton 80ns typ, toy 50ns typ (SPST switches) izes Intersil's latch-free junction isolated processing to Power supply currents fess than 1A build the fastest switches now available. These switches °- Ply en can be toggled at a rate of greater than 1 MHz with super ¢ OFF leakages less than 100pA @ 25°C fast ton times (80ns typical) and faster toy times (50ns guaranteed typical); guaranteeing break before’ make switching. ¢ Non-latching with supply turn-off This family of switches therefore combines the speed © Single monolithic CMOS chip of the hybrid FET DG 180 Family with the reliabitity and i" . low power consumption. of a monolithic CMOS con- * Plug-in replacements for 1H5040 family and part of struction. the DG180 family to upgrade-speed and leakage : ¥y to upgrade sp st OFF leakages are guaranteed to be less than 100pA at * Greater than 1MHz toggle rate . 25°C. No quiescent power is dissipated in either the ON * -Switches greater than 20Vp-p signals with or the OFF state of the switch. Maximum power supply £15V supplies current is 1uA from any supply and typical quiescent 2 currents are in the 10nA range which makes these * TL, CMOS direct compatibility devices ideat for portable equipment and military applications. ; The IH5140 Family is completely compatible with TTL {5W) logic, TTL open collector logic and CMOS logic . gates. itis pin compatible with Intersil's ]H5040 Family and part of the DG180/190 Famuy as snown im the switching state diagrams. ORDERING INFORMATION FUNCTIONAL DIAGRAM Order ‘Temperature ' Part Number Function Package Range iHSt40 NUE SPST TPN CERDIP SSC to asc in Pastc 3 70 a - IKSMOMFD «SPST 14 Pin Fiat Pack 55°C to 125°C cg =a ove INSt41 NUE Dual SPST 16 Pin CERDIP = -S5PC tw 125°C al : (HST CIE Dual SPST 16 Pin CERDIP. PC to 70°C 1oKEr [re JHS141 CPE ‘Dual SPST 16 Pin.Plastic DIP O°C to 70°C 1H5141 MFD Qual SPST. 14 Pin Flat Pack 55°C to 125°C ‘1H5141 CTW Dual SPST TO-100 O°C to 70°C $ ‘1H5141 MTW Dual SPST 70-700 BEPC to 125°C | a7 1H5142 MJE ‘SPOT 16 Pin CERDIP 55°C to 125°C IH5142 CPE it ( e( Mew ueD SBT 14 Pin Flat Pack 55°C to-125°C mi oe et p 15142 CTW ‘SPOT ‘70-100 OC to 70°C neu! Fe] (r

15142 MTW ‘SPOT 70-100 “BSPC to 125°C

1H5143 MJE- Dual SPOT 16 Pin CERDIP 55°C to 125°C 1H5143 CJE ‘Qual SPOT 16 Pin CERDIP OC to 70°C . => [sxe Laie

15143 CPE * Dual SPOT 16 Pin Plastic DIP = OC to 70°C ~

|H5143 MED. Dual SPOT = 14 Pin Flat Pack = -55°C to 125°C. r les \\HS144 MJE DPST 16 Pin CERDIP <65°C to 125°C . | 1H5144 CJE ‘DPST 16 Pin CERDIP O°C to 70°C | J A] ingiad CTY PST 0-100 OC to 70°C Le. dy *

15144 MTW ‘OPST 0-100 ~SS°C 10 125°C [ fan

15145 ME Dual DPST = 16 Pin CERDIP- 55°C to 125°C -

1H5145 CLE Dual OPST =—-16 Pin CERDIP_ OPC to 70°C , va 1H6145 CPE Dual DPST —16 Pin Plastic DIP Cte 70°C 115145 MFO. ‘Qual DPST =—-14 Pin Flat Pack 65°C to 125°C Note: FIGURE 1. Typical Driver/Gate — 1H5142 1. Ceramic (side braze) devices also avaitabl: consult factory. 2. MIL tomp range part also available with MIL-STD-663- processing, 371

1H5140-IH5145 Family INTERSIL ABSOLUTE MAXIMUM RATINGS viv <aav NOTE: Stresses above those listed under : . Absolute Maximum Rai “ese . o~ < ‘These ae stress ratings only, enc tune- Operating Temperature .... -85°C to+125°C 9 Vo—Vs_<t 2r any other conditions above tnose

9 Vy inlcated nthe operationalzectionsot

(All Leads Soldered toa P.C. Board) Vi-Vin <30V Sure to sbtolute maximum ating cor . 2 fons forexten iect Derate 6 mW/°C Above 70°C VL <20V device reliability. Lead Temperature (Soldering 10 sec.) .. 300°C VIN <20V . ELECTRICAL CHARACTERISTICS (@ 25°C, V* = +15V, V- = -15V, V = +5V) ‘ MIN/MAX, LIMITS PER CHANNEL MILITARY COMMERCIAL |_sympot | characteristic | ssc [sarc |irse [0 | sarc [+70 | TEST CONDITIONS Drain—Source On 75 75 ry Is=-10 mA Resistance VANALOG * -10 V to +10 V Atosien | Channet to Channel 25 30 Toston) Match (typ) (typ) Vanatos | Min. Analog Signal an +10 v | Handling Capability Iogt* — | Switch OFF Leakage nA |Vo=+10V, Vs=-10V Isjott Current Vp =-10V, Vs= +10 V toon Switch On Leakage 1 Vb = Vs = -10 V to +10 V Ion | Current ton ‘Switch “ON" Time See switching time specifications and timing diagrams. tot ‘Switch “OFF” Time OIRR: Min. Off Isolation f=1 MHz, Ry = 1000, CL <5.pF Rejection Ratio See Fig. 5, Note 2 vr + Power Supply 10.0 100 BA ° Quiescent Current = Power Supply 10 | 100 10 | 100 | wa |vrestsv.ve-tsy, * Quiescent-Current VL= +5 V +5 V Supply 1.0 10.0 10 100 pA Quiescent Current See Fig. 6 . Gnd Supply 10. A 1 Quiescent Current CCRR | Min, Chanfiél to One Channel Off; Any Other ChannelCross Channel Switches Coupling Rejection See Fig. 7, Note 2 Ratio Note: 1. Some channels are turned on by high (1) logic inputs and other channels are turned on by low (0) inputs; however 0.8V to 2.4V describes the, min. range for switching properly. Refer to logic diagrams to find logical value of logic input required to produce ON or OFF state. 2. Charge injection, OFF isolation, and Channe! to Channel isolation are only sample tested in production. . 3-721

SINTERS! 1H5140-1H5145 Family » Bl I TYPICAL SWITCHING WAVEFORMS SCALE: VERT. = SV/DIV. TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 8) CCoCTeeoTy avonomee im bo He ot . I | ct ! Coie Arey meme pay Cf i A TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 9) i iN ae yi ooo erry f 1 ai jal " am i owe TT] [ve Lil et aa Lor ToL) °C ++25°C +125°C TTL OPEN COLLECTOR LOGIC DRIVE TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 10) (Corresponds to Figure 1+) CTT TT ETT Ty ee | CSA Ea Cory fo eee foe Oe Lf fl ft AT SSaAeeae acer] rest 425°C 425°C ‘ 3-75

1H5140-1H5145 Family . IL SWITCHING STATE DIAGRAMS | switch sTATEs ARE FOR LOGIC "1" INPUT FLATPACK (FD-2) DIP (JE, PE) FLATPACK (FD-2) « Orr (e PE) TO-100 1 a x] mod > »| >! | ore Opes moto |, BoD o SPST - DUAL SPST 1H5140-(rpgion) < 762) 15147 (rpgion) < 752) FLATPACK (FD-2) DIP (JE, PE) TO-100 FLATPACK (FD-2) DIP WE, PE) wor {DG188 EQUIVALENT) {06191 EQUIVALENT) we y Poe Suv ae u v uo . . SPOT DUAL SPDT — dio 1H5142 (rBSton) < 782) 15143 (tpsion) < 752) . FLATPACK (FD-2) ‘DIP (WE, PE} TO-100 FLATPACK (FD-2) ‘DIP (JE, PE) uo {DG185 EQUIVALENT) a g Bop ef epe DPsT DUAL DPST = aw 1H5144 (rpsion)< 752) 15145 {rps(on) < 752) 3-78 ‘

Ball y l lel S IL 4-Channel Differential Fault Protected CMOS Analog Multiplexer FEATURES GENERAL DESCRIPTION «Ultra low leakage Ipyoyn < 100pA The: 1H5208 is a dislectrically Isolated CMOS monolithic ® Power supply quiescent current less than 1A analog multiplexer designed asa plugin replacement for the < # 48V analog signal range DG509 and similar devices, but adding fault protection tothe ® NOSCR latoh standard performance. A unique serial MOSFET switch en- 2 peeicbetore Me ke ewitching sures that an OFF channel will remain OFF when the Input ‘ 4 swite exceeds the supply rails by up to + 25V, even with the supply’ * TTL and CMOS compatible strobe control voltage at zero. Further, an ON channel will be limited to a © Pin compatible with 11509, DG509 and AD7509 throughput of about’/.5V less than the supply rails, thus * All channels OFF (Iy,x=100nA) when power OFF, for —_ affording protection to any following circultry such as op analog signals upto + 25V ‘amps, DIA converters, etc. Cross talk onto “good” channels * Any channel tums OFF (I,x<100nA)if inputexceeds _is also’prevented. 3 supply rails by up to +25V. Throughput always a binary 2-bit address code together with the ENable input . <#14V(215V supplies) allows selection of any channel.pair or none at all. These 3 * TTL and CMOS compatible binary Address and inputs are all TTL compatible for easy logic interface; the ENable inputs ENable input also tacilitates MUX expansion and cascading. FUNCTIONAL DIAGRAM DECODE TRUTH TABLE ON Su SWITCH . ; : PAIR Sm oo x | x foo NONE 0 oO 1 ta, ib suo" ofa] a 2a, 2b su o% os +]o] 4] 3aab de . Si oe Dy Ap An EN . Logic "1" = Vay 24V sao Logie "0" = Var 0.8 $5 07% sao PIN CONFIGURATION (outline dwg ve, P=) ist a GT eno 6 ¢ $ vi fig v+ a su EF] [3] Sw . [ Sam [5 Des . Sua may aboness eure Sum [&| fa] Sau ABOVE EXAMPLE SHOWS CHANNELS 1a AND 1bON ' Sua fi0] Sao [a [2] ‘TOP VIEW . 3.79

IH5208 ~~ INTERSIL ABSOLUTE MAXIMUM RATINGS V4 toGroUnd 6.00. e cece ete cece eee ener eects BV VO tOGTOUNG «00. seseeeeeeeeeeeseesteeeeseees—16V “All leads soldered or welded to PG board. Derate 1omWi°C above ‘Stresses above those listed under Absolute Maximum Ratings may cause permanent damage tothe device, These are stress ratings only, and functional opera- tlonot the device a these or any other conditions abovethose indicated in the operational sectione ofthe specifications isnt implied. Exposure to absolutemax: imum rating conditions for ‘extended perlods may affect device reliability. ELECTRICAL CHARACTERISTICS v + = 15v, v> = ~15Y, Vey =24V, unless otherwise specified. No [waxing IMeasuneojrests| rye ["—wsuFex | vesuFAx 1... TERMINAL | PER 2s = 20°C): asec | 85°C!) TEMP oe me L fel [= p= (tia | Sr ly=—1.0mA, switoh’on, V5o=10V Val =08V, ig=—1.0mA Vani=24V s : ‘toston) * ‘sien)maxfOS%on)min Ww . Atogon = PIE OBCN y asay t « Fosion)ave, R ce ee Vg= 10V, Vp= =10¥ [8 joo0z| [0.05 [so [ot 80 | Ng =10V, Vp =i10V, en a, eS ee ee Vp =0V, Ve= —10V | Ven=0 | XT Vp= =10V, Vg= 10 dO cc sutton on I a F [Ig with Power OFF 400 Vt SV" = QV, Vex 2 25V, a Ven=Vo0V, Ap, Ay, Ag=0V oF SV £ Jisforn with Vg = = 25V,Vp = = 10V] Sequence each T Overvoltage (Note 1} switch fewey on [Rota | 4 [or] [=o [ow [le | Vanavoroy or o 1A fivnsten [fe aera a pfu oa ¥ FRon=tore Beak 0 Ven= +8V, Ap, Ay, Ay Strobed N | Before mae Vin= # 10v, Figures & | Delay Setting 1 [Time "OFF teolation Vew=0, Ay = 2000, C, =39F, Ve= VRMS, 1=500KHE y ea A A Vena ov, [Foon es 1140 KHa oO A fot Mie Pe [ve [a Tso 800 [760 [coo | s000 [7 Patrva, ven sory a Note 1. Readings taken 400ms after the overvoltage occurs. *3-80

Figure 5. Series Connection of Channel Switches Under some circumstances, if the logic inputs are present sale] Fi}sa. logic inputs as a sort of phantom supply; this could result in .

Figure 14. Submultiplexed 2 of 32 system. The two1H5043s are

Further information may be found in: A003 “Understanding and Applying the Analog Switch,” by ‘A020 “A Cookbook Approach to High Speed Data Acquisi- Dave Fullagar tion and Microprocessor Interfacing,” by Ed Slieger A006 “A New CMOS Analog Gate Technology,” by Dave R009 “Reduce CMOS Multiplexer Troubles Through Proper Fullagar Device Selection,” by Dick Wilenken . CHIP TOPOGRAPHY Saa_. Ssa Sia vo 2) 2) ee A sen 3 oom” Dealt a 008 in a = 7 a : Sa SS Se == a =| Dr la \\ wx] aN a N ° Full Facil foc cla, 82 Sa Sap Sa Sth vt GND _ 0.111 in . (2.82) mm 3-86 .

: SE CMOS Monolithic RF/Video Switch FEATURES . . GENERAL DESCRIPTION * Tas(on)<750, flat from DC to 100MHz(< 3dB) The IH5941 is a dual SPST, CMOS monolithic switch which * “OFF” isolation>60dB @ 10MHz uses a “‘Serles/Shunt” ("T" switch) configuration to obtain * Cross coupling isolation>60dB @ 10MHz high “OFF” isolation while maintaining good frequency * Directly compatible with TTL, CMOS response in the “ON” condition. * Wide operating power supply range Construction of remote and portable video equipment with 3 * Power supply current< 1A extended battery life is facilitated by the extremely low * “Break-before-Make” switching current requirements. Switching speéds are typical * Fast switching (80ns/150ns typ) . ton = 160ns and toy=80ns, and guaranteed “Break-before- Make" switching. Switch “ON” resistance is typically 409-502 with +15V ° power supplies, incteasing to typically 175@ for +5V sup- ORDERING INFORMATION plies. The devices are available in TO-100 and 14-pin epoxy DIP packages. PART TEMPERATURE NUMBER RANGE Oto +706 14Pin DiP_| TO-100) =55°Cto +1250 FUNCTIONAL DIAGRAM PIN CONFIGURATIONS Circuit of Switch Channel ¥ nw SWITCH ao pls Mr, switcH ” sounceo——oT o—o bean ne By fa] ne o2N aN) | J oun poT qt of] fm /@ o\\* . ono [4] fay contact oT +p o- "a ETO Of, DRIVER ° ®@ [9) . TRANSLATOR ae “oe Tas. NO _ a Note: Only one side shown, seE] fee Tor vew Tor view * 387

145341 INTERSIL

ABSOLUTE MAXIMUM RATINGS . (CVEFSION) «oe eee ee cece ee reese ees eee OO +70°C Stresses above those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica- tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS v* = + 15v, v, = +5V, V~ = - 15V, Ts = 25°C unless otherwise specified, PARAMETER [Smet conorons Ege ee aoe 3 ‘Supply Voltage : Ranges . Positive Supply | V+ 45>16 5015 51015 Logic Supply VM (Note 3) 45>V* Stove Btov* v Negative Supply} V~ —4>-16 —5to -15 ~5to -15 ‘ Resistance agen |g = 10mA, Viv =2.4V (Note 4) Vo-18V to +18V ves | 15 15 175 Switch "ON" V+=V_=SV, Vin =3V} Resistance V-=5V, Vo= #5V [on Resistance Ig= 10MA, Vo= =8V Match ‘Switch “OFF” loot [Vero = +5V to - BV 20 05 Leakage or |vy=0sv (Notes 2and4) | Ison |Ven=+14Vto ~14V 50 10 n a Switch “ON” loon {Vo = +5V or -8V 03 03 50 Leakage + WMy=2dv lyn [Vo= +14V to ~14V 0s 08 100 . Input Logic Vin>24V or<0 1 1 10 1 Current ° Positive Supply ha Vin = OV or +5V_ 1 10 1 Quiescent Current WA Negative Supply Vw=ovor ev | 1 1 10 Quiescent Current | Logic Supply h Vin = OV of +5V | vo 1 1 10 Quiescent Current . Note 1: Typical values are not tested in production. They are given as a design aid only, Note 2: Positive and negative voltages applied to opposite sides of switch, in both directions successively. . Note 3: These are the operating voltages at which the other parameters are tested, and are not directly tested. Note 4: The logic inputs are either greater than or equal to 2.4V or less than or equal to 0.BV, as required, for this test. 3-88

AC ELECTRICAL CHARACTERISTICS v- = + 15v, v= +5V, V~ =0V, T,=25°C unless otherwise specified (Note 5). Note 6: Test circuit should.be built on copper clad ground plane board, with correctly terminated coax leads, eto. Note: Only one side shown. Other acts identically. Figure 2. OFF Isolation Test Circuit Figure 3, Cross-Coupling Rejection Test Circuit

2 A 10 Vour

Your, ¢—- Il Fasjonisee frequency. Note: Only one side shown. Other acts identically.

. 1H5344 @INTERSIL TYPICAL CHARACTERISTICS, . a "aoeg vo Analog Input Voltage Faafon) ¥8 Analog Input Level with * ”_OIRR (OFF Isolation Rejection) +16V Power Supplies ‘+ 5V Power Supplies vs Frequency (See Figure 2)

70 Fpin's= +16 PINTS 1 180 PrN S=PIN T= FOV] Ty FU T= 22s] ‘

tea tare / ° CSN TT err rrry nya » rh e He ecw / Peg 0 RT pe Ly eT CN PAH , § CNT eo A) cg Ceee a annnadaell a . atl Lt Td a LL ° CO ET CN CORR cross Coupling edi tenon Rejection) vs Frequency Voltage Divider Terms with a 750 {See Figure 3) Load (See Figure 4) 0 was C=] ROY 30 ot 4 H SHS Tht eet ma a 2 lh ONT en | ee CCITT seem a my BM NU raped ML rq 3-34) : @ COME TH eee AA ° CLONIT CIN SC FREQUENCY (MHz) FREQUENCY (MHz) DETAILED DESCRIPTION . APPLICATIONS. ec eee I edt" contigurstion, where aunt Charge Compensation Techniques switch is closed when the switch is open. This provides much Charge injection results from the signals out of the level better isolation between the input and the output than does. translation circuit being coupled through the gate-channel the single series switch, especially at high frequencies, and and gate-source/drain capacitances to the switch inputs and the result is excellent performance in the Video and RF outputs. This feedthrough. is particularly troublesome in region compared to conventional Analog Switches. Sample-and- Hold (re eee Creek Tea eeer a as it 1, a +) tn ain ise! ample (Track) to Hold of levices guaranteed “'Breakcbefore Make” action, with negligible © S0™V-S0mV in a 1000pF capacitor, at Vero of about OV static power consumption and TTL compatibility. 1 3-90

1H5341 ‘ SSINTERSIL EQUIVALENT SCHEMATIC DIAGRAM (1/2 of actual circuit on chip'shown) va at | oy L | i Pad | mot | oe aT . | Peet Ly isa an co So swnrcn CHIP TOPOGRAPHY | , 3:92

• Analog Multiplexer FEATURES GENERAL DESCRIPTION © Ultra Low Leakage — Ipjot) < 100pA te The IH6108 is a GMOS monolithic, one of 8 multiplexer, The * Fos(on) < 400 ohms over full signal and temperature part is @ plugin replacement for the DG508. Three line binary range decoding is used so that the 8 channels can be controlled by * Power supply quiescent current less than 100,A 3 Address Inputs; additionally a fourth input is provided to © £14V analog signal range . use as a system enable. When the ENable input is high (SV) * No SCR latchup : the channels are sequenced by the 3 line Address inputs, and * Bréak-before-make switching when low (OV) all channels.are off. The 3 Address inputs are © Binary Address control (3 Address inputs control 8 controlled: by TTL logic or CMOS logic elements, a “0” cor. channels) responding to any voltage greater than 2.4V. Note that the © TTL and CMOS compatible strobe control + ENable input (EN) must be taken to SV-to enable the system © Pin compatible with DG508, His0B & AD7508 and léss than 0.8V to disable the system. 3 FUNCTIONAL DIAGRAM DECODE TRUTH TABLE : [a2 [as To [en T on swircn | . . x|x|xlo NONE - o|o} ofa 1 bal oO 0. 1 1 2 o{+]o]3 3 oy ofafada 4 & r]ofo}: 5 I ; . 1 o 1 1 6 1 1 0 1 7 Ao, Ar, Aa S40——_o-—% Logic “1” =VaH>2.4V Venn = 4.5V Your Logic “0” = Vat $ 0.8V D s0——_o-% swircn . PIN CONFIGURATION * ° ao] Fra: Eves Fal Ae Se vy GND sy fil vt Pvca| Fra ss , & [Til Se . 6 4 8 sc fas, hh Bvenaste pur oa aa LINE siNanY ADDRESS INPUTS (o'janden@ sv ABOVE EXAMPLE SHOWS CHANNEL 6TURNEDON ORDERING INFORMATION - [—saerqumsea | TEMPERATURE RANGE | PRGA] Ceramic package available as = Special order only (IN610BMDE/CDE) 16 pin CERDIP TH6108CPE. 0°C to 70°C. 3.93

Current (Any Terminal) ....0cccesssseeeseeeeere SOMA 70°C, Stresses above hoo sted under Abgalute Maximum Ratings may cause permanent damageto te dovico, These aresres ratings ony sndfuncionl oneaton of the aoviee at these or any clfer Conaltions above those indteated inthe operational sections of te specifications is not implied. Exposure to absolute maximum faling conditions for extended periods mav affect device releblty. ELECTRICAL CHARACTERISTICS V* =15v, V~ = -15V, Vey = +5V (Note 2), Ground = OV, unless otherwise specified. Tests TEMP | see] asrc [reece | orc | asc [ror | [2 | 80 [s00 | s00_[ 400 [sso [sso [40 [ [vo = tv, ig = 1.0mA [8 _| 150 [300 | s00 [00 [350 | "350 [ 450 | 0 [Vo==10v. ig ="10mA|VaL = O8V. Van = 2aV) S|arpsion, ~ FOSionjmax= TBsfenyrin Sana a v [8 _onoe| ons [eon so [is 10V. Vo = =10V - T hscorey CN he ee nA [Wo= 10V, Vs =-10V_]Ven = 0 4) [fos [ [70x {1090 fT 02 [100] ee ee [Sequence each switch on 0 [efor [| 02 [oo [a4 [100 | [say = Vo ==10v [vat = 08, Vans = 2.4 Thaniow 67 Iaom) [oe Ar orAef__3—} or | 1 -t0-[-20 [5 | 50 [Was za ory Nilaxcorey twcn | inputs [~3 [oi [To fa [To [30 | ee nf er ul = = ea LS VR CY A | seerig Ofte | of feat ff yy [SeeFig.2 Vhowemy | | dos as Ps Nhowew | Oo | foe ft M += 500 xz fGen Se a Yue lcosen | ows | fat Ty yyy : Sfsvony Te[ ves Pao ao TT tooo TT levee | pjouret [=P ve fa [ao [Po J] ue sv Plsorey [et ve [+ fs [fie [Pico [ow All Va=0.07 8V yfeurent_ [=P v= a eo PT cco Puen NOTE 1: See Enable Input Strobing Levels, Section 1. ve wv = - Ue t00ns . {= toons 08V- 50% ve Fro tana EI = ov bo I Your po a: VereHov Ves=— fs a + 33 = 10 ie s Eo] wWQ — 3s00 5 ial ane) id 16108 ——V aon = = ESTONSY | E-SBON Yb STON}) | HSB ON EN tv : [] Jono _v>_ of °%——+-—~Eroag] rane Re tice + Sa Your * vst==10¥ Vee = HOV | PROBE IMPEDANCE |-10v mid Re 2 10. tes . Bee 0-5 . Figure 1. tiansiion Switching Test 3.04

1H6108 : INTERSIL JH6108 APPLICATION INFORMATION (Continued) When the EN input is driven from CMOS logic, no puliup is necessary, see Fig. 5. : ” le [sl : w [i] cD4003 : id fis] BI ' 3 iG aol] Hila: : fit ENT] fla: ral i] ~sv[ ffajano . = . sf fg}s15v sf] Fass sof] Fils: sf] lds, ofl [ls Figure 5, ENable Input Driven trom CMOS Logic ‘The supply voltage of the CD4009 affects the switching speed of the IH6108; the same is true for TTL supply voltage levels. The chart below shows the effect, on trans for a supply varying from +4.5V to +5.5V. (MOS OR TTL SUPPLY VOLTAGE TYPICAL trans @ 25°C +4.5V 400ns +4.75V 300ns +5.00V 250ns 45.250 . 200ns +5.50V 175ns ‘The throughput rate can therefore be maximized by using a +5V to +5.5V supply for the ENable Strobe Logic. The examples shown in Figures'4 and deal with ENable strobing when expansion to more than eight channels.is required; in these cases the EN terminal acts as a fourth address input. If eight channels or less are being multiplexed, the EN terminal can be directly connected to +5V logic supply to enable the IH6108 at all times. 3:96

1H6108 APPLICATION INFORMATION (Continued) ll. Using the 1H6108 with supplies other than A15V : The IH6108 can be used with power supplies ranging from voltage in order to define a binary “1” state. For the case 6V to 276V. The switch rosion) will increase as the supply _ shown in Figure 6 the EN voltage is 11.3V which means that voltages decrease, however the multiplexer error term (the —_logic high at AQand A1is=-+8.8V (logic low continues to be= Product of leakage times sion)) will remain approximately —_0,8V). In this configuration the [H6108 cannot be driven by constant since leakage decreases as the Supply voltages are = TTL (+5V) or CMOS (+5) logic. It can be driven by TTL open reduced, - collector logic or CMOS logic with +12V supplies. Caution must be taken to ensure that the enable(EN) voltage “the logicandthe 1H6108 have common supplies, the EN pin is at least 0.7V below V~ at all times. If this is not done the —_ should again be connected to the supply through a silicon Address input strobing levels will not function properly. This . diode. In this case, tying EN to the logic supply directly wilt may be achieved quite simply by connecting EN (pin2)toV+ not work since it violates the 0.7V differential voltage. (pin 18) via a silicon diode as shown in Figure 6. When using _required between V+ and EN. (See Figure 7) A 1uF capacitor this typeof configuration, a furtherrequirementmustbemet- can be placed across the diode to minimize switching the strobe levels at AO and Ai must berwithin 2.5V of theEN glitches. wwo1e . ali] fis}a: Sal Fa: EL fa of wets Fe sof5l frzjss INPUTS: sf] []s6 INPUTS sz] fils: Wour) of] 19}s2 Figure 6, IH6108 Connection Diagram for less than #18V Supply Operation. 3-97

146108 APPLICATION INFORMATION (Continued)

| IN914 OR ANY SILICON DIODE. Figure 7. 146108 Connection Diagram with ENable Input Strobing for less than =15V Supply Operation. . using ::18V supplies. lower sps(on) and slightly higher leakages.

FEATURES GENERAL DESCRIPTION ° © Pir il |-! . Ore epatiae weth D506, Hl on + AD7506 The IH6116 is a CMOS monolithic, one of 16 multiplexer. The - ott analog si i ott) = 100p/ part is a plug-in replacement for the DG506. Four line binary ony analog Sigal range decoding is used sothat the 16 channels can be controlled by © FOS(on) <700 ohms over full signal and temperature 4 Address inputs; additionally a fifth input is provided to use range . as system enable. When the ENable input is high (5V) the * Break-before-make switching channels are sequenced by the 4 line,Address inputs, and * TTL and CMOS compatible Address control when low (OV),all channels are off. The 4 Address inputs are * Binary Address control (4 Address inputsicontrol 16 controlled by TTL logic or CMOS logic elements with a “0” channels) corresponding to any voltage less than 0.8V and a “1” cor- © Two tier submultiplexing to facilitate-expandability responding to any voltage greater than 3.0V. Note that the © Power supply quiescent current less than 100A ENable input must be taken to 5V ‘to enable the system and © No SCR latchup Jess than 0:8V todisable the system. FUNCTIONAL DIAGRAM DECODE TRUTH TABLE som no . [as [a2 Ta: [ao Ten Ton swircH | x x x x 0 NONE so . o}o}]ojfo|1 1 : ofololi1]a 2 so ofofifol}4 3 ' ofofifa fa 4 on o}+]ojfoj4 5 so . 0. 1 0 1 1 6 it 0 1 1 o 1 7 so Lo ofajafa]a 8 * 1Jo}ol}ol|t 9 so wouter a1folo}ita 10 » r]o};1]o fa 1" 1 0 1 1 1 12 soo 1 } oO oO 1 13 i 1 oO 1 1 14 so afr}fafola 15 so tia ja ja [as 16. suo Logic "1" = Va 23.0V Venn = 4.5V suo. Logic "o"=VaL S0.8V

35 OM ° -

SennOLLING Sor “a Exar ‘Fens or auxin ta ES . so [zisr Br false auf] fBlss Bio pst $43 4 S03 Fa st Bo Ay Aa As eN [ca en ono Fr AS , {UNE sinany anofess nPUTS net ony (Oo NANDEN GeV . ‘ABOVE EXAMPLE SHOWS CHANNEL 9 TURNED ON Tor view vécoMMON TO SUBSTRATE . ORDERING INFORMATION [pant NUMBER | TEMPERATURE RANGE | PACKAGE | Ceramic package available as THeT16MJT 55°C to +125°C 28 pin CERDIP™ ‘special order only (IH611GMDI/CDI) JH6116CUL O°C to 70°C 28 pin CERDIP. THET16CPI OC to 70°C 28 pin Plastic DIP - 309.

Vo tO GFOUNG vo. s ees eec eee eee eee eee eeeeee eens IBV “All leads soldered or welded to PC board. Derate 10 mW/*C above Stresses above those listad under Absolute Maximum Ratings may cause permanent damage tothe device. These are stress ratings only, and tunctional operation of the device at these or any other conditions abave those indicated inthe operational sections of fe specifications fs not implied, exposure to absoluse maximum rating conditions for extended periods may affect device reliably. ELECTRICAL CHARACTERISTICS v* =15v, V~ = -15V, Veu= +5V (Note 1), Ground =0V, unless otherwise specified. CHARACTERISTIC | MEASURED| TESTS | TYP . TEMP [-ss°c | aso [rasec | ore [asco Trove | [16 [480 | 600 | 600 [700 | sso [eso [ 7s0_| rosions [46 7 [300 "{ "200 [600 [700 | eso | os0 | 750 iS = PBSionyman— FDSICAIMI Ye rem [| [et | cE cE | Isl feo elena eam ! [ae "foot | tos" (so 2 Ts | iH [16 foo [| os [sof [02 sa) ce [ » Re eee See A [Vp = 10V, Vs =“10V_|Ven = 0 | tlororr a A A YT a A [Sequence each switch on oxo [ie fos [ 02 [100 [| 7100| VAL = 08V, Van= 5Y r LO IN | taiot) a P AoA: BA fen a to s0 020 ftrore os a p [epee oe See Fig 2 jy eon oss See Fig. 3 emo os ll A Gl GG Gl + = 500 KHz M i SCT A ES | a OG

1 Mle

Ioogiore {pies fs ee lena _| [Current [2[ vee 00 1000 [Ven = SV. E|Standoy [eve 00 000 a AIVA=00r 3 |Current fap 00 F000 NOTE 1: See Section V. Enable Input Strobing Levels. ve wv . Ve scone | Sitoe oav ox ——| rm L sav _ vst . 3 : Fo a vou co Vows : Ao s7}— am Ve sof = sk = fee tease) : ud az sol “av sy "QD Ss0—7* Ho ' sek SON | SONY pst Hest ON = = suf Hw ae stsp—) ew S15 [0] wnat) [=] [ewe y-_ of; <r] mo * cher Your Lauy-3 Wee stv = E prone mrcomice 8 = * | pest C2 5 30pF now mad asin Figure 1 ‘ 3-100

s5v - av : 2 2 ; ty ove: cal SRY ~ fal S—omase Tl so ae or He © Your — > © Your “® in) eae é Sao To [eno -3v eno ftv x " CS te www oav von West vo to on ee ww SION S18 OK te som on : Es “ee - Yoyo 5¥ ‘wey Figure 2 Figure 3 a 1H6116 APPLICATIONS ; , . +5 sv 1. 1 out of 32 channel multiplexer using 2 IH6116s 9 9 EN ho rt a “ f= 2 Vour u—De Tron , : cMios mnvenTeR ‘1H6116~ aa TTL foverter must have resistor r : pulp to dive EN Input. ste sn DECODE TRUTH TABLE DECODE TRUTH TABLE * [as TAs [Ae Tas [Ao TON switcn 7 [TAs Tas T Ae Tar J Ao TON Switch O oO oO Oo oO si 1 oO 0 0 0 S17 o oO i) oO 1] $2 1 iJ oO i) q S18 0 0 oO 1 oO $3 + oO o 1 ° “$19 oO i) oO 1 1 $4 1 ° o 1 1 ‘S20 0 oO 1 i] o ss 1 i} 1 o ° ‘S2t . o}o]/1folf4 $6 afoftr}o]a $22 0 oO 1 1 0 s7 1 oO 1 1 O $23 0 tC) 1 1 1 SB 1 oO 1 1 1 ‘$24 0 1 0 0 0 so 1 1 ° ° oO $25 . of1]/ojyo]1 S10 sha4}af]ofo]4 $268 O 7 oO q O si 1 1 o 1 oO $27, , o 1 o 1 1 S12 1 1 oO 1 1 $28 0 1 1 i} P) $13 1 1 1 i oO $29 0 1 1 0 1 Sid 1 1 1 i} 1 ‘$30 Oo 1 1 7 oO S15 1 1 1 1 oO $31 oO 1 1 i 1 Sié Figure 4 4 1 1 al i S32 - : 3-101

IH6116 APPLICATIONS (continuec) Il. 1 out of 32 channel multiplexer using 2 1H6116s; using an IH5041 for submultiptexing . | ° we vs + atv soa Ae Ht Sie . Ss: 1b [| 9D) A wb 4 * Le Lb ° Vout 3 te Neg {> sw © erat ie . rm.on 1 hos =| ; INVERTER 4 : Syren. " vi =A he . “Tri gate musthve + pulp resiter fo + 6V to ive EN inpuls DECODE TRUTH TABLE DECODE TRUTH TABLE [ArT As] Ae T Ar | Ao | ONSWITCH [Ac T ae [ae Tar [Ao | onswitcH 0 [} 0 [ oO st 1 0 oO 1-6 Oo |. S17 o i} 0 oO 1 $2 . 1 O o o 1 $18 o ° oO 1 oO $3 7 oO o 1 ) s19 0 ° O 1 1 84 4 iJ oO 1 1 $20 ojolrfolo} 5 r}o]1fol]o $21 o i} 1 Oo 1 sé 1 i) 1 oO 1 $22 oO 0 1 1 o S7 1 oO 1 1 o $23 oO oO 1 1 1 ‘$8 q 4 oO 1 q 1 $24 oj}ifofajo so 1} 1]}ofo]}o 52s ofifojo fa S10 +} afofo |i 526 ° 1 oO 1 i) Sit 1 1 9 1 0 S27 ofirjo}ifa 812 afatola|a $23 0 1 1 9 oO » “S13 t 1 a oO o $29 o}rlafo]s sid t}afafolr S30 i 1 1 1 i) ‘S15 1 1 1 1 i) $31 oj 1 1 1 S16 1 1 1 1 1 $32 Figure § ‘ 3102

1H6116 . BINTERSIL 1H6116 APPLICATIONS {continues} Ill. 1 out of 64 multiplexer using 4 1/16s and 1H5053.as submultiplexer o—fpe— “THLcMOS" INVERTER =pD— : “ ir Trews Non Gare +i 3v eo : Avo — 1H6116 att 1 OUT oF 16 . a a 5 on an 1 | SRB ° 3 7 re ANALOG INPUTS: mt > L)—-p> = | tet16 { [I sour OF 16 - ° tra] ty aan ee Vour y y a Tal tott6 Cat 4 0UT OF 16 ri asl Mux i | . ES 7 vaio INPUTS ool tS {)->

1 OUT OF 16 °

| | a jate must have 4a) joa Ve Ve puluposiotor to arvo EN Inputs ANALOG INPUTS = “18 Figure 6 ; IV. General note on expandability of IH6116 ‘ The IH6116 is a two tier multiplexer, where sixteen input the 16 channels of information. The advantage of this is channels are routed to a common output in blocks of 4. Each lower output capacity and leakage that would be possible block of 4 input channels is routed to one common output using a system with all 16 channels tied to one common channel, and thus the submultiplexed system looks like 4 output. Aiso the expandability into 32, 64, 128, etc. is blocks of 4 inputs routed to 4 different outputs with the 4 facilitated. Figures 4, 5, and 6 show how the IH6116 is outputs tied together. Thus 20 switches are needed to handle expanded. 3-103

Dual CMOS Driver/ . : Voltage Translator FEATURES When used in conjunction with the Intersil IH401 family © Driven direct from TTL or CMOS logic Varatets, the combination makes a complete solid state © Translates logic levels up to 30V levels switch capable of switching signals up to 22Vpp and.up to © Switches 20VAcpP signals when used in conjunction 20MHz in frequency. This switch is a “break-before-make” with Intersil [H401A Varafet (as an analog gate) type (i.e. tott time < ton timé).. The combination has typical-tost © ton <300nS & torr < 200nS for 30V level shifts Srentradat WP: fot = 200n8-for signale-up to 20Vpp in = amplitude. ° < . Seieeen REpPlY curvent 10pa for sy State (2c) A,TTL “1” input strobe will force the 6 driver output up to Pp V* level; the 9 output will be driveri down to the V~ level. : When the TTL input goes to 0", the 6 output goes to V- and 8 goes to V*; thus @ and @ are 180° out of phase with each : other. These complementary outputs can be used tocreatea 3 wide variety of functions such as SPDT and DPDT switches, GENERAL DESCRIPTION . etc.; alternatively the complementary outputs can’beused to ‘The IH6201 is a CMOS, Monolithic, Dual Voltage Translator; Grive an N and P-channel Mosfet, to make.a complete Mosfet it takes the low level TTL or CMOS logic level and converts analog gate. them to higher levels (i.e. to +15V swings). This translator is The driver typically uses +5V and +15V power supplies; typically used in making solid state switches, or analog however a wide range of V+ and V" is possible, however gates. . VT > 8V is necessary for the driver to work properly. BLOCK DIAGRAM “| SCHEMATIC DIAGRAM {ONE CHANNEL) s5v_ HSV RIVER ov iV DRIVER : oureur * ourPur ioaie % ia 2 STROBE [2 STROBE L2 wweur; LV, 7 iweuTz LI ie, i : EI PIN CONFIGURATION : * Np riven agfe OT fa 1k ae oureur . fz} FS rm input 1 a * safe] 06201 FS Su STmobe abe vt ate fa +5 2 (ey Fj ve — +15v tk,

7 Ee Fru pur 2

__ OUTPUT ‘OUTLINE DWwGs ™ oa a , DE, JE,PE Ly - * \\ oa = PART NUMBER | TEMPERATURE RANGE *IH6201CDE 0°C to 70°C. | *iHé201mDe [55°C = +125°C . : 1H6201CJE 0° to 70°C : TH6201MJE =S5°C to 125°C IH6201CPE *Special Order Oni 3-105 * .

1H6201 © - “INTERSIL ABSOLUTE MAXIMUM RATINGS VOLO VIN cevdecseressersesestectseerseeerseeeeeees 40V . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; and furictional operation of the device at these or any other conditlons above those indicated in the operational sections of the specifications is not implied. Exposure to'absolute maximum rating conditions for.extended periods may affect device reliability. : ELECTRICAL ‘SPECIFICATIONS V* = +15v, V7 =-15V, Vi = +5. [em | ——connmions (pare tomret mel are tiers] [125°C wus [aorFanverouputewing | wen 28 | 26 [ 26 [ ae | 28 [28 [25 | Vor | Vin strobe level ("1") for o2 14v 30 24 Voc. proper translation §2-14V 3 Vin strobe {evel ("0") for 62=-14V 04 Vo. proper translation 2 14V tin input strobe current draw Vin =.0V or +5V 1 1 1 1 nA {for OV — 5V range) ton time vaso, CL = 30pf switching turn-on time fig. 2B vweovdeeL CL = S0pf) 300, switching turn-off time fig. 2B I+ (V*) power supply Vin = OV or +5V 100 700 | too | 100 uA quiescent current (WV) power supply Vin = OV or +5V 00 | 100 100 | 100 | pA quiescent current I (VL) power supply ‘Vin = OV or +5V. 100 100 100 100 BA quiescent current

1. INPUT DRIVE CAPABILITY SIGNAL NUT The strobe input lines are designed to be driven from TTL aw REFERRAL logic fevels; this means 0.8V ~ 2.4V levels max. and min. Lk AESISTOR respectively. For those users who require 0.8V to 2.0V 4 DRNER aps. operation, a pull-up resistor is recommended from the TTL TL INPUT output to +SV tine. This resistor is not critical and can be in wsotaion °°} — Sirpur the 1k0 to 10k range. "7 When using 4000 series CMOS logic, the input strobe is connected direct to the 4000 series gate output and no pull = up resistors, or any other interface, is necessary. Figure 1 When the input strobe voltage level goes below Gndiie.to You will notice in Figure 1 that a “referral” resistor has been -15V) circuit is unaffected as long as V" to Vin does not —_ added from 2N4391 gate to its source, This resistoris needed exceed absolute. maximum rating. to compensate for inadequate charge area curve for isolation diode (i.e. if Cvs. V plot for diode<2 [Cvs. V plot for outputJ- FET] switch won't: function; then adding this. resistor Leebehteht bah FE CAP ape to drive the ters nagar o¥e"Omes this condition. The “referra'resstor is normally family of Varafets; these are N-channel J-FETS with built-in ("the YOOk®) to 1M range and is not oo critical. driver diodes. Driver diodes are necessary to isolate the Ill, MAKING A COMPLETE SOLID STATE SWITCH signal source from the driver/translator output; this prevents THAT CAN HANDLE 20Vpp SIGNALS forward biasing. between the signal input and the +Vcc _—_The limitation on sighal handling capability comes from the supply. The IH6201 will drive any J-FET provided some sort output gating device. When a J-FET is used, it's the pinch-off of isolation is added’i.e.” of the J-FET acting with the V" supply that does the 3-106

1H6201 @l IL APPLICATIONS, CONTINUED limiting. In fact max. signal handling capability ~ 2 (Vp + advantage of using the Vp = 7V pinch-off (along with (V7) Vpp where Vp = pinch-off voltage of J-FET chosen. unsymmetrical supplies) over the Vp = 8V pinch-off (and Le. Vp = 7V, V" = ~18V «. max. signal handling = 2(7V + — 18V supplies) is that you will have a much lower Ros(on) (15V)) Vpp = 2(7V-15)pp=2-8Vppi=16Vpp. Obviously to resistance for the Vp=7V fet i.e. for the 2N4391 fet "get 2 20Vpp, Vp = 5V with V-=-15V. Another siriple way to TDS(ON) = 222, ros(on) 352) get 20Vpp with Vp = 7V, is to increase V-to-17V, infact © Vp=7V— Vp= SV using V" "= +12V or +15V and setting V- = ~18V allows one to switch 20Vpp with any member of |H401 family. The , The 1H6201 is a dual translator, each containing 4 CMOS FETs, The schematic of one-half 1H6201, driving one-fourth of an IH401, is shown-in Figure 2A. w wv ove po~+-4 aus — sxe axa, \\ oy | as wor 7 32 | - 3 tNpuT [ I / stnoBe | 86 | vgeay “se ! Pa a “ry r “Ev . 2m, axa 3 f w * jm A j av Ov —8v ton ad torr TRANSLATOR Figure 24 Figure 28 NOTE: Each translator output has a 0 and 9 output. 6 is just the inverse of 0. . . SSS Avery useful feature of this system is that one-half of an IH6201 and one-half of an IH401 can combine to make aSPDF switch, or an IH6201 plus an IH401 can make a dual SPDT analog switch. (See II!) 1. Dual SPST Analog Switch WN. DPOT Analog Switch Gy fo FS oy cl fs) —“n] fa overs wm al EB | Est ah ps | fs Gy i By fig] ~1sv is} id) _& fia] ~15v ey 2 E E | a] RE; (} 2 & fa-sv = Ey jit gy fev = @ {7 =a i] q i; ay FE Ae a fro) o es ) a fy ee io By) y 5] NOTE: Either switch is turned on when strobe input goes high, 3407

"APPLICATIONS, CONTINUED : ; Il. Dual SPDT . IV. Dual DPST im Fa E A “ ° iz} 115 iH fia i fig) a fs} tt a — ah php d pr. a | a bs ow 3 =a Fasr {SI fiz; {a} fia act & By Ey Lal was i] figitsy = {5} fi a fg-sv = ad Ek “| [ia +1sv od ws q fr +sv a ba — ie er. 3-108

$ IH6208 4 . 4-Channel Differential ‘ CMOS Analog Multiplexer FEATURES GENERAL DESCRIPTION © Ultra low leakage — Ipjort) < 100pA ‘The 1H6208 is a monolithic 2 of 8 CMOS multiplexer. The part * ros(on) < 400 ohms over full signal and temperature _ sa plug-inreplacement forthe DGS09, Two line binary decod- range ing |s used so that the 8 channels can be controlled ih pairs by the binary inputs; additionally a third input is provided to : Powe pon sot Plane current less than 100A use as a system enable. When the ENable input is:high (6V) © No SCR latch ae the channels are sequenced by the 2 line binary inputs, and : ie up . when low (OV) allchannels are off. The 2 Addiess inputs are Break-before-make switching == controlled by TTL logic or CMOS logic elements with a “0 ¢ Binary Address control (2 Address inputs contro! 2 corresponding to any voltage less than 0.8V and a “1” corre- out of 8 channels) sponding to any voltage greater than 2.4V. Note that the * TTL and CMOS compatible Address control ENable input must be taken to 5V to enable the system, and 3 * Pin compatible with HI509, DG509 & AD7509 less than.0.8V to disable the system. FUNCTIONAL DIAGRAM DECODE TRUTH TABLE sta . x 0 | NONE smo 0 1 | ta, 16 oO 1 24, 2b 1 1 | 32,36 sao merce 1 1_| 4a, 40 Db + be Aoy At sie { : i . LOGIC “t"= Van =2.4V Venn > 4.5V LOGIC “O" = VaL < 0.8V ‘2b: oe seo PIN CONFIGURATION smo ao $76) A: en] Ha] No vg fia] v+ tore soa [5] fra sap . q sia fra sop Ce su Fi sab : > [5] 02 LINE BINARY ADDRESS INpUTS (0 0) AND EN=5V N=" FOR +5, “0" FOR Ov) ABOVE EXAMPLE SHOWS CHANNELS fa &1BON. ~ | ORDERING INFORMATION Ceramic package aveilsble as [PART NUMBER | TEMPERATURE RANGE [PACKAGE | i . Specistonder only (HBZOEMDEICOE) 3-109

Voto Ground oo. ce eev ees eeceeee eee eeeteeeee neers “IBV “All leads soldered or welded to PC board. Derate 10 mW/*C above. rating conditions for extonced periods may affect devies reliabihy. ELECTRICAL CHARACTERISTICS v* =15v, V~ = -18V, Van = +5V (Note 1}, Ground=0V, unless othenwise specified. cuanacTenistic] MEAsuAED| TESTS | TYP Max cimirs. T [7s [oof [ons J so [ot | so] [Vs = “T0V. Vo = TOV. NOTE 1: See Section | Enable Input Strobing Levels. Figure 1. trrans Switehing Test

IH6208. INTERSIL 1H6208 APPLICATION INFORMATION (continued) When the EN input is driven from CMOS logic, no pullup is necessary. (See Fig. 5) j i List a cp4009 Hs) a] cmostoce FF a g ‘ . wy Fl 3 iG Aoi] fi] a: GI fo} a Fa [3] asv BY Fi]+ssv. sia] fi3} 10 saa [5] fi2] sap “ . saa [6] fit] $3» saa{7] {10} sap ‘ oy [3]p2 ‘ . Figure 5. CMOS Logic Driving ENable Pin. . ‘The supply voltage of the CD4009 affects the switching speed of the 1H6208; the'same is true for TTL supply voltage levels. The chart below shows.the effect on trrans for a supply varying from +4.5V to +5.5V. CMOS OR TTL SUPPLY TYPICAL trans @ 25°C +4.5V 400ns +4.75V 300ns +5.0V 250ns +5.25V 200ns. . +5.50V . - 175ns ‘The throughput rate can therefore be maximized by using a + 5V to +5.5V supply for the ENable Strobe Logic. The examples shown in Figures.4 and 5 deal with ENable strobing when expansion to more than four differential channels i: required; in these cases the EN terminal acts as a third address input. If four channel pairs or less are being multiplexed, thc . EN terminal can be directly connected to + 5V to enable the IH6208 at all times, 3-112

The 1H6208 can be used with power supplies ranging from _2.5V of the EN voltage in order to define a binary “1” state. configuration; the strobe levels at AO and Ai must be within glitches. . ‘ACHANNEL SOURCE INPUTS 8 CHANNEL SOURCE INPUTS. Figure 6. |H6208 Connection Diagram for less than +15V Supply Operation.

**Figure 7. |H6208 Connection Diagram with ENabie Input Strobing for less than * 15V Supply Operation.** using =15V supplies. lower ros(on) and slightly higher leakages.

cS . . 8-Channel Differential CMOS Analog Multiplexer FEATURES GENERAL DESCRIPTION gin compatnie with His07, DGSO7 & AD7507 The 1H6216 is a CMOS monolithic 2 of 16 multiplexer. The part = TT ansiog signal range is a plugin replacement for the DG507. Three line binary * FDS(on) < 700 ohms over full signal and temperature ——_gecoding is used so that the 16:channels can be controlled in range pairs by the binary inputs; additionally a fourth input is pro- © Break-before-make switching vided to use as a system enable. When the ENable input is * TTL and CMOS compatible Address control high (V) the channels are sequenced by the 3'tine binary in- © Binary Address control (3 Address inputs control 2. -_puts, and when low (OV)all channels are off. The 3 Address in- out of 16 channels) puts are controlled by TTL logic or CMOS logic elements with * Two tier submultiplexing to facilitate expandability a “0" corresponding to any voltage less than 0.8V and a “1” © Power supply quiescent current less than 100uA corresponding to any voltage greater than3.0V. Note that the © No SCR latch up ENable input must be taken to SV to enable the system and 3 © Very low leakage Iniott) < 100pA less than 0.8V to disable the system. FUNCTIONAL DIAGRAM DECODE TRUTH TABLE . ~ ON — sgece= sono PAIR. x x x oO NONE two ofoto}ia 1 ‘Sta0—*e oO 0 1 1 2 sao o}1+folft 3 oO 1 1 1 4 sono 1 i) ° 1 5 sm" o 1 0 1 q 6° 1 1 0 1 7 sta ‘oo . 1 1 i 1 8 om sino oe LOGIC" =Van > 3V_VeNH> 4.5V smo LOGIC™“0" = VaL < 0.8V sab oe ssp PIN CONFIGURATION smo . ‘smo ~ suo oy v Pin soe ontmottinc oot ono] Bo “TIERS OF MUKING. 2 Eiece soo a co] aes soa] | en fia: BR Seenasuenoun re fax TOR new ume onary aopness nPurs vtcomuon ro SUSSTRATE . ‘ABOVE EXAMPLE SHOWS CHANNELS ta & 1b ON PARTNUMBER | TEMPERATURE RANGE | PACKAGE | Ceramic package available as THE2TEMUi 28 pin CERDIP special order only (|H6216MDI/CDI) THE216CU OOo 70°C 28 pin CERDIP THE216CPI °C to 70°C 28 pin Plastic DIP 3-118

1H6216 . ~ INTERSIL ABSOLUTE MAXIMUM RATINGS Vo tO GrOUNG seep ceeseseeeeeeeeenseesesseeens “IBV Current (Analog Source or Drain) w..e.esceseeeeeeee 20MA 70°C Simglse above nose listed under Absolute Maximum Fatings may cause paraont amagetothe vice, These are stress ratings only, tnd functional operation of the device at these or any other conditions above those Indicated inthe operational sections of the specifications fe not impliso. Exposure to absolute maximum |» rating conditions for extonded periods may affect device reliably. ELECTRICAL CHARACTERISTICS v* =15v, v~ =—15V, Ven = +5V{Note 1), Ground = 0V, unless otherwise specified. (CHARACTERISTIC ‘MEASURED | TESTS ‘TEST CONDITIONS TERMINAL | PER [| msurex [sure | TEMP | ssc [asrc [asc] orc [256] vo°c | [18 {eo | "s00_| “600 [700 [50 | eso [70 | [Sequence each switch on Stoo {16 [300 | "eo | 600 | 700 [eso [eso | 750_| Van =0.8V, Van =3V = $0SIonjmax— FDS{onan ye ! | . Wee ee eS IT s [is Poort or 1 so [0.250] ic eA | Ven = IH [2 [os [02 Too [0.4 [00] A OA [Sequence each switch on A Mat =0.8V. Val =SV_ FT Fiaenor ee IN aio a lp om lu Ae Aa Ven = 6v Allva=0 ir a DA OT a SS A pfeeo oe yy fone on es os yfenew os a fa iG OG ad hn += 500 Kt ba a A pF Vo=0 Ven = 0,1 = 140 kHz to ie 1 MHz aS CE | iS or leans | p [Surrent SS a SO E | Stanby pe 00 000 AlLVa=0 or V Pefeureont [Pe 909 006] ven NOTE 1: See Section V. Enable input Strobing Levels. SWITCHING INFORMATION . ao : = Fe ma ‘ ° i : az sop 7 A Co. sot > == f Sa- “4 ja BE Fal f Vv : [=] Loo __v- ef: ——<rronr] ase Te thee Vim aoe] fee 8 ‘eee = = (08 2 prose mpepance es a0pF 3-116

SWITCHING INFORMATION (continued) +00 sia teow pen # 2 . we “ fa] ‘SWITCH OUTPUT [al Wee ne. 2) one 7 : rs & OQ“ Toxo q 90 = a9 . a” : : - = igure 2 = av , fot teren ow eave hs ogo“ grrotoumt Fr] 1 {see na. 3) = Ly} S 3 Es over a8vo Qe T a i Kn Op vo “8 Figure 3 1H6216 APPLICATIONS {. 2 out of 32 channel multiplexer using 2 IH6216s . +15v -18v re me T ore a wa216 Trl ; re en a Sie Sea Sib sab ° 2 Youre rrurewos A sv “sv INVERTER So ”(Stea So St “TTL gate must have pul to dive EN input : Figure 4 DECODE TRUTH TABLE DECODE TRUTH TABLE [As [Az TAs | Ao TON switch [| [As | Ao TA: [Ao | ONswitch [|_| 7 oO oro oO Sta [J oO 0 o Sib 0 0 0 1 ‘Sa 0 oO ° 1 ‘S2b ololi}o Soa ofofs]o ‘sab of ofa] Sia ofofils S4b o 1 i i‘) ‘SSa oO 1 o oO ‘SSb oO 1 oO 1 ‘S6a o 1 i) tT ‘S6b . oO 1 1 oO Sta oO 1 1 0 $7b ofatala Sea Vours ola}afa 585 Voure q1 ° oO i) ‘$9a 1 oO oO 0 ‘S8b

1 O oO 1 ‘S10a, a 1 oO oO 1 ‘$10b

1 oO 1 oO Siia 1 ° 7 oO S11b 1 o 1 1 Sida 1 oO 1 4 ‘$12b 1 1 oO 0 S13a 1 1 i) 0 ‘$136 r{afota Sida s]afo]a S145 1 1 1 oO $154 1 1 1 Oo ‘$15b . 1 1 i 1 Si6a. 1 al Bl 4 S16b 3-117

IH6216 APPLICATIONS (continued) Il, 2 out of 32 channel multiplexer USirig 21H6216s; with an 1H5043 for submuttiplexing av ov ov , hs raion” a i ] . x TT] at * a | 1 m5043 | ee ee = { sta sea Stb sont Op TIJcMos 5 I INVERTER a os a al he 590 $16a_ Sb si “TTL tortor must have resistor pulup to drive EN Input - iad . Figure DECODE TRUTH TABLE . DECODE TRUTH TABLE [as | Ae | Ar] Ao T onswitcn TT] (TAs J Az TA: [Ao | on-switch [] ‘oy; opo|o ‘Sia ofolo fo Sib o}of}o|a Sea o}o}oala S20 o}o}]1]o Soa o}o}1jo s3b ofo}s]4 Séa o}o}ia}4 Séb of 1]o]o. ‘Soa . o}+}folo ssp ojifo]s 36a : o}afo fa seb ofifijfo Sva o}i}a1 fo ‘stb ofaya] a s8a Vours ofrta da sab Voure r}ofo]a Soa 1{o]o]o $96 r}ojo]a 10a r}Jolo|a S10b t]o]1]o Sita 1}o}1]o Sitb r}o]iia St2a y}o}1]4 S12 1} 1]ofo $134 an 1} 1fo}o $13b af a}ojr Si4a ra }o jr St4b a] 1] 1]o S15a 1} a]1 fo $180 s}iti fs Siéa bata ta ja $160 3118

1H6216 APPLICATIONS ° : Ml. 2 out of 64 multiplexer using 4 1H6216s and 2 1H5043s.as ‘submultiplexers Mined aad VL = +5V9 Voc = 15V 9 . a i en Be we | pare a Roe wl os +H {Op — ~ | ri b [js . 3 ——— a t S98 ~ ‘S16a_S9b S165 ~ Y Mad ad Was8ve Voc = +18ve o Ce we CDA Sita ‘$24a S17b ‘S24b ~ ‘1 Op F a Db pm . ° on Taree Figure 6 General note on expandability of 16216 .@ 1H6216 is a two tier multiplexer where. 8 pairs of input the 16 channels of information, The advantages of this are annels are routed to a pair of outputs in blocks of 4. Each lower output capacity and leakage than would be possible ock of 4 input channels is routed to one common output using a system with all 8 channels tied to one common aannel, and thus the submultiplexed system looks like 4 output. Also the expandability into 2 out of 32, 64, 128, etc. is slocks of 4 inputs routed to 4 different outputs with the 4 facilitated. Figures 4, 5, and 6 show how the !H6216 is utputs tied in pairs. Thus 20 switches are needed to handle expanded. . 3-119

1H6216. . INTERSIL Figure 4 shows a 2 of 32 multiplexer Using 2 IH6216s. Since _that no excessive system power is generated. Note that the the 6216 is itself a 2 tier MUX, the system as shown is logic of the 6043 is such that it can be tied directly to the basically a 2 tier system. Corresponding output points of —_ENable input (as shown in the figures) with no extra jogic each of the 6216 are connected together, and the ENable in- being required. Put strobe is used as the As input. Since each output (pins 2 . . and 28) corresponds to an “ON” FET and an “OFF” FET, the _V- Enable input strobing levels overall system looks like 1 “ON” FET and 3 “OFF” FETs for The ENable input acts as an enabling or disabling pin for each of the Voutt and Voue2 outputs. Thus the outputleakage the IH6216 when used as a2 out of 16 channel MUX, however will be 1 In(on) plus 3 Ip(o%S or about 0.4 nA at room —_when expanding the MUX to more than 16 channels, the EN temperature. Thruput speed willbe typically 0.8usfortonand —_pin acts as another address input. Figures 4 and 5 show the 0.3us for tort, with thruput channel resistance in the 5002 EN pin used as the As input. area. For the system to function properly the EN input (pin 18) Figure 5 shows the 2 of 32 MUX of Figure4, withathirdtierof must go to5V 5% for the high state andless than 0.8V for the. ‘submuttiplexing added to further reduce leakage and output __low state, When using TTL logic, a pull-up of 1k® or less capacity. The 1H5043 has typical ON resistance of S00 (max. _resistor should be used to pull the output voltage up to 5V. is 750) so it only increases thruput channel resistance from When using CMOS logic, the high state goes up to the power the 500 ohms of Figure 4 to about 550 ohms for Figure 5. supply so no pulll-up is required. Thruput channel speed is a little slower by about 0.5us for If used on high voltage logic supplies, EN should be at least both ON and OFF time; and output leakage is about 0.21nA. 0:7V below V * at all times. See 1H6208 data sheet for details. Figure 6 shows a 2 of 64 MUX using 3 tier MUXing (similar to

3 Figure 5), The Intersil IH5043 is used for the third tier ot APPLICATION NOTES

MUXing, Each Vout point will sea 3 OFF channels and1ON Further information may be found in: channel at any time, so that the typical leakages will beabout —_ag03 “Understanding and Applying the Analog Switch,” by 0.4.nA. Thruput channel resistance will be in the 5500 area Dave Fullagar and thruput switching speeds willbe about 1.3usforONtime gos “A New CMOS Analog Gate Technology,” by Dave and 0.88 for OFF time. . Fullagar > ‘The 1H6043 was chosen as the third tier of the MUX because A020 “A Cookbook Approach to High Speed Data Acquisi- it will switch the same AC signals as the IH6216 (typically tion and Microprocessor Interfacing,” by Ed Slieger Plus and minus 1SV) and uses break before make switching. R009 "Reduce CMOS Multiplexer Troubles Through Proper Also power supply quiescent currents are typically 1-2uA so Device Selection,” by Dick Wilenken NOTE: This multiplexer does not require external resistors and/or diodes to eliminate what is commonly known as a latch up or SCR action. Because of this fact, the ros(oxy of the switch Is maintained at specified values. 3-120