GPLD1080A | DigiCamel IC Datasheet

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GPLD1080A GENERALPLUS | Alldatasheet

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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GG MAY 23, 2007 Version 1.3 PPLLDD11008800AA

800 CCHHAANNNNEELL SSEEGG//CCOOMM SSTTNN LLCCDD

In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

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Version: 1.3 Table of Contents PAGE

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Version: 1.3

80 Channel SEG/COM STN LCD Driver

GENERAL DESCRIPTION The GPLD1080A is a 80-channel segment/common driver IC which is suitable for driving small/medium scale dot matrix LCD panels, and is used in hand-hold game or electronic dictionary. The GPLD1080A has seven modes that can be selected to set common and segment numbers by select pin. The GPLD1080A also has built-in DC/DC converter, voltage regulation and voltage follower to generate LCD driver voltage. 2. FEATURES Number of LCD drive outputs : 80 Supply voltage for LCD drive: 12V (max.) Supply voltage for logic system: 2.4V to 5.5V 3-types LCD combination selectable by input pins CS1 CS0 Configuration Bias 0 0 48 COM * 32 SEG 1/8 0 1 64 COM * 16 SEG 1/9 1 1 80 COM 1/10 Built-in DC-DC, Voltage Regulator and Voltage Follower Abundant command functions LCD bias set, electronic volume Shift data clock frequency − 6 MHz (max.) : V DD = 2.4 V ~ 5.5 V 4 bit parallel / serial modes are selectable by PS pin. 3. PIN DESCRIPTIONS Mnemonic Type Description Y80 – 1 O LCD driver output pins. V0 ~ V4 P The bias voltages for LCD driving. Where V OUT >V0>V1>V2>V3>V4>VSS. FB I Gain adjustment input of V0. By adjusting the RA, RB ratio between VB 0, FB and VSS, the LCD driving voltage, V0 is equal to VREF (1+ RB B/RA). Where the V REF is the internal reference voltage. VDD P Power supply for logic circuit. (+ 2.4V to + 5.5V) EI I AT com/seg mix mode, when EI=’H’ the bus data DI3 ~ DI0 be accessed. EO O Enable GPLD2080A signal DI3 ~ DI0 I Display data input at com/segment mode. 1). In 1-bit parallel input mode (PS=”L”), input data into the 1 pins DI0. Connect DI3- 1 to VSS or VDD. 2). In 4-bit parallel input mode (PS=”H”), input data into the 4 pins, DI3 - DI0. DISOFFB I Display Off control input pin. Control input pin for output non-select level. When set to V SS, the LCD drive output pins (Y0 – 79) are set to level VSS. CP I Clock input for taking display data at com/seg mix mode. 1). Data is read at the falling edge of the clock pulse. LP I Latch pulse input for display data at segment mode. Shift clock input for shift register at common mode. 1). Data is latched at the rising edge of the clock pulse. M I AC converting signal input for LCD drive waveform. FP I COMMOM data input PS I Data input mode select pin. 1). When set to VSS, 1-bit parallel input mode is set. 2). When set to VDD, 4-bit parallel input mode is set. VSS I Ground (0V). VDDA P Power supply for analog circuit. (+ 2.4V to + 5.5V)

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Version: 1.3 Type Description Mnemonic VSSA P Ground (0V) for analog circuit VSSH P Ground (0V) for driver circuit CAP1 O DC-DC voltage converter, capacitor for charge pump. CAN1 O DC-DC voltage converter, capacitor for charge pump. CAP2 O DC-DC voltage converter, capacitor for charge pump. CAN2 O DC-DC voltage converter, capacitor for charge pump. CAP3 O DC-DC voltage converter, capacitor for charge pump. CAP4 O DC-DC voltage converter, capacitor for charge pump. CAP5 O DC-DC voltage converter, capacitor for charge pump. VOUT O DC-DC voltage converter. SCL I Serial clock input pin for command decoder. Built-in pull high resister 100Kohm to VDD. SDI I Serial data input pin for command decoder. Built-in pull high resister 100Kohm to VDD. CS1 ~CS0 I 3-types LCD combination selectable by CS1 ~ CS0. CS1 CS0 Configuration Bias 0 0 48 COM * 32 SEG 1/8 0 1 64 COM * 16 SEG 1/9 1 1 80 COM 1/10

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Version: 1.3 4. FUNCTIONAL DESCRIPTIONS 4.1. Segment outputs M Latch data DISOFFB Driver Output Voltage Level L L H V2 L H H V0 H L H V3 H H H VSS X X L VSS 4.2. Common outputs M Latch data DISOFFB Driver Output Voltage Level L L H V1 L H H VSS H L H V4 H H H V0 X X L VSS Note1: VSS < V4 < V3 < V2 <V1 < V0, L: VSS (0V), H: VDD (+2.4V to +5.5V), X: Don't care. Note2: "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage which is assigned by specification for each power pin. 4.3. Mix mode (common/segment mode) When (CS1, CS0) = (0, 0) Æ Select 48 com/32 seg mode 4.4. Segment side of mix mode (48COMX32SEG) (A) 4-bit parallel mode Figure of Clock Input Data

8 Clock 7 Clock 6 Clock ․․․ ․․․ ․․․ 3 Clock 2 Clock 1 Clock

(B) 1-bit serial mode Figure of Clock Input Data

32 Clock 31 Clock 30 Clock ․․․ ․․․ ․․․ 3 Clock 2 Clock 1 Clock

DI0 Y48 Y49 Y50 × × × Y77 Y78 Y79

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Version: 1.3 4.5. Booster Circuit Using the booster voltage circuits equipped within the GPLD1080A chips, it is possible to product 2X/3X/4X/5X/6X step-up of the (VDD - VSS) voltage levels. Note: all the capacitors value is 1uF Please keep this relation: VOUT – V0 > 2V VOUT will be clamped about 15.6V

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Version: 1.3 4.6. Regulator Circuits The booster voltage generated at V OUT outputs, the liquid crystal driver voltage V 0 through the voltage regulator circuit. Because the GPLD1080A chips have an internal high-accuracy fixed voltage power supplies with a 32-level electronic volume function for the V0 voltage regulator. 4.7. When the V 0 voltage regulator with external resistors are used Through the use of the V 0 voltage regulator, external resistors and the electronic volume function, the liquid crystal power supply voltage, V 0, can be controlled by command alone, making it possible to adjust the liquid crystal display brightness. The V 0 voltage can be calculated by using equation E-1 over the range where | V0 | < | VOUT | - 2V The Rb and Ra are external resisters. V0 = (1 + Rb/Ra) • VREF VREF is the IC-internal fixed voltage supply and its voltage at TA = 25°C is 2.04V. When use default value S4~S0. For power saving please selection Rb > 1000Kohm (saving DC current from V0 through Rb, Ra to ground) α is set to 0 level of 31 possible levels by the electronic volume function depending on the data set in the 5-bit electronic volume register. The following table shows the value for depending on the electronic volume register settings. S4 S3 S2 S1 S0 α 0 0 0 0 0 31 0 0 0 0 1 30 0 0 0 1 0 29 : : : : : : 0 1 1 1 1 16(default) 1 1 1 0 1 2 1 1 1 1 0 1 1 1 1 1 1 0

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Version: 1.3 5. COMMAND DESCRIPTION By setting SDI to “Low” and SCL to “High”, GPLD1080A is able to receive serial input data. Serial data is input in the order of “S4, S3, S2, S1, S0” from the serial data input pin (SDI) at the rising edge of serial clock (SCL). After the 5-bit data have been read into the shift register, the shift register will automatically convert serial data to change V0 voltage. SCL 2 4 SDI START CONDITION SCL 1 3 4 5 S4SDI START CONDITION S3 S2 S1 S0 STOP CONDITION Timing Diagram of Serial Data Transfer 5.1.1. Timing characteristic of command interface: Parameter Symbol Min. Typ. Max. Unit The Hold Time of SDI Falling to SCL Falling Tstart 100 - - ns SCL Period Tcyc 200 - - ns SCL High Width Tw 50 - - ns SCL Setup Time in Order to Latch SDI Data Ts 50 - - ns SDI Hold Time That Is from SCL Falling to SDI Change Th 50 - - ns SCL Rising to SDI Rising in Order to Load Data to Register Tstop 50 - - ns

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Version: 1.3 6. ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Parameter Symbol Conditions Applicable Pins Ratings Unit Supply Voltage (1) VDD VDD -0.3 to +6.5 V V0 V0 -0.3 to +16 V V1 V1 -0.3 to V0 + 0.3 V V2 V2 -0.3 to V0 + 0.3 V V3 V3 -0.3 to V0 + 0.3 V Supply Voltage (2) V4 V4 -0.3 to V0 + 0.3 V Input Voltage VI TA = +25℃ Referenced to VSS (0V) DI3 - 0, CP, LP,M, PS, CS1,CS0, FP,SCL,SDI,EI, DISOFFB -0.3 to VDD + 0.3 V Storage Temperature TSTG - - -45 to + 125 ℃ Note1: TA = +25℃ Note2: The maximum applicable voltage on any pin with respect to VSS (0V). Note3: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For no rmal operational conditions see AC/DC Electrical Characteristics. 6.2. Recommended Operating Conditions Parameter Symbol Conditions Applicable Pins Min. Typ. Max. Unit Supply Voltage (1) VDD VDD +2.4 - +5.5 V Supply Voltage (2) V0 Referenced to VSS (0V) V0 +8 - +12 V Operating Temperature TOPR - - -20 - +75 ℃ Note1: The applicable voltage on any pin with respect to VSS (0V). Note2: Ensure that voltage are set such that VSS＜V4＜V3＜V2＜V1＜V0 6.3. DC Characteristics Parameter Symbol Conditions Applicable Pins Min. Typ. Max. Unit VIH - 0.8VDD - - V Input Voltage VIL - DI3 - 0, CP, LP, M, PS, FP CS1,CS0, SCL, SDI, DISOFFB,EI - - 0.2VDD V VOH IOH = -0.4mA VDD - 0.4 - - V Output Voltage VOL IOL = +0.4mA EO - - +0.4 V ILIH VI = VDD - - +1.0 μA Input Leakage Current ILIL VI = VSS DI3 - 0, CP, LP, M, PS,FP,CS1,CS0, SCL, SDI,EI DISOFFB - - -1.0 μA Output Resistance RON |△VON| = 0.5V V0 = +12V Y79- 0 - 1.0 2.0 KΩ Stand-by Current ISTB B DISOFFB=VSS VDD - - 1.0 μA Operation Current Consumption IDD *1 VDD - 100 - μA Note1: 48COM X 32SEG, VDD = 3.0V, V0 = 8V(Rb=1000Kohm, Ra=342Kohm), V OUT=9V, fCP = 1MHz, No-load, E I = VDD. The input data is turned over by data taking clock (4-bit parallel input mode).

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Version: 1.3 Parameter Symbol Conditions Applicable Pins Min. Typ. Max. Unit VIH - 0.8VDD - - VInput Voltage VIL - LP, M, FP,PS,CS1,CS0, SCL, SDI, DISOFFB - - 0.2VDD V VOH IOH = -0.4mA VDD - 0.4 - - V Output Voltage VOL IOL = +0.4mA EO - - +0.4 V ILIH VI = VDD - - +1.0 μA Input Leakage Current ILIL VI = VSS DI3 - 0, CP, LP, M, PS, CS1,CS0, SCL, SDI, DISOFFB - - -1.0 μA Output Resistance RON |△VON| = 0.5V V0 = +12V Y79- 0 - 1.0 2.0 KΩ VLCD Accuracy V0 Rb=1000k, Ra=240k V0 -1 - +1 % Stand-by Current ISTB B DISOFFB=VSS VDD - - 1 μA Operation Current Consumption IDD *1 VDD - 200 - μA Note1: VDD = +3.0V, V0 = +10.5V(Rb=1000Kohm, Ra=240Kohm), VOUT=12V, fLP =6.0 KHz, fM = 35Hz in case of 1/80 duty operation, no-load. 6.4. AC Characteristics: EX. 64 Common 96 Segment 1 bit data mode use GPLD1080A + GPLD2080A. 6.4.1. LCD control signal timing characteristic: Parameter Symbol Min. Typ. Max. Unit CP Rising Time Tr1 - - 5 ns CP Falling Time Tf1 - - 5 ns CP Clock High Plus Width Tw1 80 - - Ns CP Clock Period Tcyc1 160 - - Ns The Setup Time That CP Clock Latch Data Ts1 50 - - Ns

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Version: 1.3 Symbol Min. Typ. Max. Unit Parameter The Hold Time That CP Clock Latch Data Th1 50 - - ns The Delay Time from CP Falling to LP Rising Td1 30 - - ns The Timing from LP Falling to CP Falling Td2 10 - - ns LP Clock High Plus Width Tw3 80 - - ns Parameter Symbol Min. Typ. Max. Unit LP Signal Rising Time Tr2 - - 5 ns LP Signal Falling Time Tf2 - - 5 ns LP Falling to FP Rising Td3 0 - - ns The Setup Time for LP to Latch FP Ts2 200 - - ns LP Pulse Width Tw2 100 - - ns LP Falling to FP Falling Th2 0 - - ns

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Version: 1.3 7. LCD DISPLAY DESIGN GUIDE The data transferred from MCU to GPLD1080/GPLD2080 module will pass to last point. Let’s see the example. If we have an “E” word (Fig) in computer, and we want to show it from computer to LCD panel. We are going to get the four events below the section 7.1～7.4. Fig. “E” word in computer 7.1. The 80COM x 160SEG (1) The SEG signal connected to O1 Æ S1, O2Æ S2……O159 Æ S159, O160 Æ S160, in PCB layout which it w ill mirror display on LCD. An 80COMx160SEG diagram is below: GPLD2080A(2) Y[79:0] LCD PANEL 80COMX160SEG O80 O79O2 O1 EIEO GPLD2080A(1) O160O159O82 O81 EIEO VDD EO EI DISOFFB CS1 CS0VDD VDD GPLD1080 S1 S2 S159 S160 C79 C80

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Version: 1.3 7.2. The 80COM x 160SEG (2) The SEG signal connected to O1 Æ S160, O2Æ S159……O159 Æ S2, O160 Æ S1, in PCB layout which it will mirror display on LCD. An 80COMx160SEG diagram is below: GPLD2080A(2) Y[79:0] LCD PANEL 80COMX160SEG O80 O79O2 O1 EIEO DISOFFB GPLD2080A(1) O160O159O82 O81 EIEO DISOFFB VDD EO EI DISOFFB CS1 CS0VDD VDD GPLD1080 O80 O79 O2 O1O160 O159 O82 O81 C79 C80 S1 S2 S159 S160

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Version: 1.3 7.3. The 64COM x 96SEG (1) The SEG signal connected to O1 Æ S1, O2 Æ S2……O95 Æ S95, O96 Æ S96, in PCB layout which it will mirror display on LCD. A 64COMx96SEG diagram is below: GPLD2080A Y[63:0] O96 O95O18O17 EIEO VDD EO EI DISOFFB CS1 CS0VDD VSS GPLD1080A O16 O15O2 O1 Y[64] Y[65] Y[78] Y[79] LCD PANEL 64COMX96SEG S1 S2 S95 S96 C63 C64

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Version: 1.3 7.4. The 64COM x 96SEG (2) The SEG signal connected to O1 Æ S96, O2 Æ S95……O95 Æ S2, O96 Æ S1, in PCB layout which it will mirror display on LCD. A 64COMx96SEG diagram is below: GPLD2080A Y[63:0] LCD PANEL 64COMX96SEG O96 O95O18O17 EIEO DISOFFB VDD EO EI DISOFFB CS1 CS0VDD VSS GPLD1080A O16 O15O2 O1 Y[64] Y[65] Y[78] Y[79] O80 O79 O2 O1O96 O95 O82 O81 S1 S2 S95 S96 C63 C64

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Version: 1.3 8. APPLICATION CIRCUIT 8.1. 64 Common 96 Segment 1 Bit Data Mode Note1: All capacitors value is 1uF. Note2: If this panel >4 inch, then V0~V4 capacitors need to use 2.2uF. Note3: GPLD2080A is the segment driver and Y[79] is first data in.

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Version: 1.3 8.2. 80 Common 160 Segment 1 Bit Data Mode Note1: All capacitors value is 1uF. Note2: If this panel >4 inch, then V0~V4 capacitors need to use 2.2uF. Note3: GPLD2080A(1&2) are the segment drivers and Y[79] of GPLD2080A(1) is first data in.

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Version: 1.3 9. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment This IC substrate should be connected to VSS Note1: To ensure that the IC functions properly, bond all VDD and VSS pins. Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type GPLD1080A-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).

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Version: 1.3 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.

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Version: 1.3 11. REVISION HISTORY Date Revision # Description Page MAY 23, 2007 1.3 1. Modify the diagram in section 5. 2. Add the “Timing characteristic of command interface” in section 5.1.1. 3. Add the “LCD control signal timing characteristic” in section 6.4.1. 4. Add the “LCD DISPLAY DESIGN GUIDE” in section 7. 10, 11 APR. 11, 2007 1.2 Modify the “DC Characteristics” in section 6.3. 9, 10 FEB. 12, 2007 1.1 1. Modify the “FEATURES” in section 2. 2. Modify the “PIN DESCRIPTIONS” in section 3. 3. Modify the “Application circuit: 64 common 96 segment 1 bit data mode” in section 7. 4. Add the note2 and note3 to section 7.1. A pplication circuit: 80 common 160 segment 1 bit data mode. JAN. 05, 2007 1.0 Original 15

Product Information

GPLD1080A specifications and overview.

Summary

80 CHANNEL SEG/COM STN LCD DRIVER

Description

80 CHANNEL SEG/COM STN LCD DRIVER

Source title GPLD1080A Datasheet(PDF) - Generalplus Technology Inc.

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