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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus. DATA SHEET Aug 03, 2016 Version 1.3 GGPPLL008811AA11 LLooww PPoowweerr 160 Dots LLCCDD CCoonnttrroolllleerr wwiitthh 77KKBB RRoomm
© Generalplus Technology Inc. Proprietary & Confidential
2 Aug 03, 2016
Version: 1.3 Table of Contents PAGE
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3 Aug 03, 2016
Version: 1.3 LOW POWER 160 DOTS LCD CONTROLLER WITH 7KB ROM 1. GENERAL DESCRIPTION GPL081A1, a special designed CMOS 8 -bit microprocessor by Generalplus, offers the best cost/performance ratio in the industry. It combines RAM, ROM, I/Os, an interrupt controller, and an automatic display controller/driver in a small package. One of its extraordinary features is the capability of operating in low voltage range, from 1.2V ~ 1.7V. The Power Down Mode keeps LCD being displayed when CPU is in standby mode, but consumes only less than 3.5 A. Not only GPL081A1 is capable of displaying LCD, but it also can process complex instructions and functions as well. The development team has designed GPL081A1 to cover many application fields such as calculator, watch and other LCD related products required only one battery supply. 2. FEATURES Built-in 8-bit RISC processor 128-byte SRAM 7.5K-byte ROM CPU frequency: 300KHz or 600KHz (mask option) @ 1.5V (dependent VDD) Built-in RC oscillator Built-in 32.768KHz oscillator circuit for real clock function Watch dog mode (1Hz or 0.5Hz) Low operating voltage: 1.2V - 1.7V Low standby current, ISTBY < 1A LCD matrix: 28 - 32 segments, 4 (or 5) commons 12 general I/O pins (segment 29, 30, 31, 32 can be defined as I/O; ABB1 can be optioned to 5 th common) LCD 1/2, 1/3 bias, 1/2, 1/3, 1/4, 1/5 (mask option) duty One 8-bit timer 6 interrupt sources (Timer, T16Hz, T2Hz, 128Hz, 2KHz, external interrupt) Power down mode (wake-up source: key input, T2Hz, T16Hz, timer) Note1: T16Hz: 32Hz, 16Hz, 8Hz or 4Hz Note2: T2Hz: 2Hz or 1Hz 3. BLOCK DIAGRAM X32I X32O 8-BIT RISC PROCESSOR OSC GEN TIME BASE INTERRUPT LOGIC I/O P O R T ABB1 - 0 ( I/O ) EFB5 - 0 ( I ) CDB3 - 0 ( I/O )
32 SEGMENTS X 4 COMMONS LCD DRIVER
7.5K BYTES ROM
128 BYTES
/ABB7 - 4 C4/ABB1 C3 - C0 Note1: By mask option, SEG31 - 28 can be defined as either segment output or I/O. (SEG31 - 28 or ABB7 - 4) Note2: By mask option, ABB1 can be defined as either I/O or common output (ABB1 or common4)
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4 Aug 03, 2016
Version: 1.3 4. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description SEG26 - 0 SEG31 - 27 30 - 4 36 - 32 O LCD driver segment output. SEG31 - 28 can be mask option for ABB7 - 4. C3 - 0 54 - 57 O LCD driver common output. ABB1 - 0 37 - 38 I/O I/O port (ABB1 can be mask option for COM4) EFB5 - 0 44 - 49 I Input port (also for key wake up input) CDB3 - 0 42 - 39 I/O I/O port is applicable for sensor. RESET 50 I System reset input. X32I 51 I 32.768KHz crystal input (provide LCD frequency) X32O 52 O 32.768KHz crystal output. TEST 53 I Test input. VDD 43 I Power input VSS 31 I Ground input. V45 I Inputs for setting LCD bias. CUP1 CUP2 I Inputs for setting LCD bias. 4.1. PAD Assignment This IC substrate should be connected to VSS or floated Note1: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible.
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5 Aug 03, 2016
Version: 1.3 5. FUNCTIONAL DESCRIPTIONS 5.1. ROM Area The GPL081A1 provides 7.5K-byte ROM with a LCD driver that is capable of controlling 4 (or 5) commons and 32 segments. (Basically, 7K byte of ROM is available for application program and data, 0.5K bytes is allocated for test program.) 5.2. Stop Clock Mode The GPL081A1 provides a power saving mode for those applications required very low stand -by current. Users can simply enable wakeup sources to stop the CPU clock by writing the STOP CLOCK Register ($09). By doing that, CPU will go to standby mode and the RAM and I/Os remain in their previous states until wakeup. There are three wake -up sources in the GPL081A1, Port EFB wake -up, TIMER wake -up an d T2Hz or T16Hz wake-up. After GPL081A1 wakes up, CPU will go to the next state of sleep. Wake -up action will not affect RAM and I/Os. Note1: T16Hz: 32Hz, 16Hz, 8Hz or 4Hz Note2: T2Hz: 2Hz or 1Hz 5.3. Timer/Counter The GPL081A1 contains an 8 -bit timer. In the timer mode, TMA is a re-loadable up-counter. It will automatically be reloaded with the user’s preset value and up-count again. The clock source is selected as the following: Timer/Counter Addr. Clock Source TMA 8-BIT TIMER $0025 CPU CLOCK (T) or CLK32K (32768Hz or CPU clock / 8) 5.4. LCD Controller GPL081A1 contains a LCD controller/driver that provides the capability of driving 5 commons and 32 segments LCD. To light the overhead of CPU, a display buffer is designed for mapping to LCD. A LCD dot/patt ern is set ON or OFF by programming the corresponding bit of the display buffer. To make the chip more flexible, the pin SEG31, 30, 29, 28, can be selected as I/O pins by mask option. In addition, the LCD bias can be programmed as 1/2 or 1/3. The duty c an be selected as 1/2, 1/3, 1/4 or 1/5. 5.5. Map of Memory and I/Os * I/O PORT: * NMI SOURCE: ─ INT1 (from TIMER) *INT SOURCE ─ 128 Hz ─ 2 KHz ─ TYHz (32Hz, 16Hz, 8Hz , 4Hz) ─ TXHz (2 Hz or 1Hz) ─ EXTERNAL (CDB1) ─ INT0 (from TIMER) H/W REGISTER, I/Os USER RAM and STACK UNUSED GENERALPLUS TEST PROGRAM USER'S PROGRAM DATA AREA $0000 $0080 $00FF $0200 $05FF $0600 $1FFF *MEMORY MAP ─ PORT ABB $0002 EFB $0003 CDB $0005 ─ I/O CONFIG $0000 $0001 $0006
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6 Aug 03, 2016
Version: 1.3 6. ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 1.7V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 6.2. DC Characteristics Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD 1.2 - 1.7 V - Halt Current 1 IHALT1 - 3.0 - A FCPU = 0.3MHz @ 1.5V, no load use 32768Hz crystal Halt Current 2 IHALT2 - 16 - A FCPU = 0.3MHz @ 1.5V, no load no use 32768Hz crystal Operating Current IOP - 35 - A FCPU = 0.3MHz @ 1.5V, no load Standby Current ISTBY - - 1.0 A VDD = 1.5V, 32768 Hz OFF OSC Frequency FOSC2 -15% 0.6 +15% MHz VDD = 1.5V 1.2 Input High Level VIH 1.1 - - V VDD = 1.5V Input Low Level VIL - - 0.5 V VDD = 1.5V Output High Current (I/O) IOH - -1.0 - mA VDD = 1.5V VOH = 1.0V Output Sink Current (I/O) IOL - 2.5 - mA VDD = 1.5V VOL = 0.5V CPU Clock FCPU -15% 0.3 +15% MHz 0.3, 0.6MHz by code option FCPU = FOSC/2 @ 1.5V 0.6 6.2.1. Frequency vs. temperature 0 10 20 30 40 50 60 70 1.10 1.20 1.15 1.25 1.30 Temperature (℃) FOSC (MHz) Frequency normalized to 25℃ VDD=1.5V 6.2.2. Frequency vs. VDD 100 200 300 400 500 600 700 800 900 VDD(Volts) Fcpu(KHz)
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7 Aug 03, 2016
Version: 1.3 7. APPLICATION CIRCUIT SEG7 SEG8 SEG15 TEST LCD Module Cs[3:0] SEGs[31:0] GPL081A1 C1 V3 V45 0.1 0.1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG25 SEG26 CUP1 CUP2 0.1 X32O X32I 20p 32768Hz 20p RESET RESETEFB2 EFB0 EFB1 EFB4 EFB3 EFB5 VSS SEG17 SEG16 SEG18 SEG23 SEG24 SEG22 SEG21 SEG19 SEG20 CDB3 SEG27 SEG28 SEG29 SEG30 SEG31 VDD 0.1 CDB2 CDB1 CDB0 ABB1 ABB0 I/O DEVICE 0.1F VDD VDD 100K 1N4148 0.1F Super Reset Circuit Note: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible. (2) Super reset circuit is able to prevent the voltage level from brown out which may further lead CPU run into unstable state.
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8 Aug 03, 2016
Version: 1.3 8. PACKAGE/PAD LOCATIONS 8.1. Ordering Information Product Number Package Type GPL081A1 - NnnV - C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
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9 Aug 03, 2016
Version: 1.3 9. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the i nformation in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alte r the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet s and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical l ife support equipment, are specifically not recommended without additional processing by GENERALPLUS for such ap plications. Please note that application circuits illustrated in this document are for reference purposes only.
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10 Aug 03, 2016
Version: 1.3 10. REVISION HISTORY Date Revision # Description Page Aug 18, 2016 1.3 Add super reset application circuit in section 7 7 OCT. 24, 2011 1.2 CPUCK frequency modified from “500KHz” to “600KHz”. 3, 6 FEB. 20, 2006 1.1 1. Modify the descriptions in section 6.2. 2. Remove the pad locations. MAR. 16, 2005 1.0 Original Note: The GPL081A1 data sheet v1.0 is a continued version of SPL081A1 data sheet v1.1.