GPCV1002A GENERALPLUS | Alldatasheet
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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENER ALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GG Advanced Multimedia Processor SOC Solution Nov 18, 2013 Version 1.0 PP3311PP11000022AA In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
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Version: 1.0 Table of Contents PAGE
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Version: 1.0 ADVANCED MULTIMEDIA PROCESSOR SOC SOLUTION 1. GENERAL DESCRIPTION The Generalplus GP31P1002A, a highly integrated SoC (System-on-a-Chip), offers a great cost-effective and high performance ratio solution for multimedia applications. It is embedded the ARM7TDMI with 8K-byte unified ID-cache and many tremendous features, SPI Flash controller which CPU can run program directly on it, WMA accelerator, TFT-LCD interface, 60-bit BCH and Randomizer for MLC/TLC NAND Flash, UART interface which support smart card interface(ISO7816), 4-channel DMA controller, 6-channel 16-bit timers, RTC, two SD/MMC card interfaces, USB 2.0 mini-host/device, interrupt controller, SPI (master/slave) controller, 8-channel sound processing unit (SPU), programmable I/O ports, stereo 16-bit DAC for audio playback, 0.5W class AB mono audio amplifier, 8-channel 12-bit ADC, MIC, PLL, I2S TX/RX for external si gma-delta CODEC, 32K-byte OTP with EV mode, power control macro and 136K-byte embedded SRAM when WMA is disable. With a complete set of common system peripherals, the GP31P1002A chip minimizes overall system cost and no additional component needs to be added. Not only does GP31P1002A feature the high-speed performance, but it is also a cost-effective system and the most importantly - compatible with all ARM based programs. 2. FEATURES ARM7TDMI CPU with 8KB unified ID-cache, embedded JTAG ICE, and working frequency up to 96MHz. Up to 136KB SRAM for local data buffer when WMA is disable. There is a dedicated 128KB internal SRAM if WMA is enable. 32KB OTP with EV mode SPI Flash controller which CPU can run program directly on it. Supports 1-bit/2-bit/4-bit IO mode both on STR and DTR. 2 SPI Flash are allowed in serial or parallel manner. WMA accelerator Four-channel DMA controller. TFT-LCD controller. z UPS051. (serial RGB) z UPS052. (serial RGB dummy) z I80 (8-bit system bus) I/F type. z CCIR601/CCIR656. Interrupt Controller. Universal Serial Bus (USB) 2.0 high/full speed compliance device and USB mini-host with built-in transceiver. Support Bulk IN/OUT, Audio ISO IN/OUT, Video ISO IN and Interrupt IN transactions. BCH 60-bit/1K and Randomizer for MLT/TLC NAND Flash 8-channel sound processing unit (SPU). Each channel in this SPU can do ADPCM/PCM decode, volume multiply and left/right channel mute control. Watchdog timer. Six 16-bit timers/counters. Two SD/ SDHC/ SDIO/ MMC card interfaces. SPI (master/slave) interface with data rate up to 24Mbps. UART (asynchronous serial I/O) interface with baud rate up to 1.8432Mbps and 115.2Kbps. The UART interface can be configured as smart card interface(ISO7816) 42 Programmable general I/O ports (GPIO) with pull-high/low control. Built-in Power macro for power on/off controller and a 4.2V to 3.3V LDO and a 3.3V to 1.2V LDO. Dedicated 4.2V to 3.3V LDO for ADC/DAC. Real-time clock (RTC) with independent power supply. 216MHz PLL, range from 24MHz to 216MHz with 6MHz step 16-bit stereo DAC (2-channel) for audio playback. 0.5W class AB mono audio amplifier 12-bit ADC with 2 line-in c hannels and 2 internal channels for battery and 1.2V measurement. MIC with PGA. (Programmable Gain Amplifier) I2S TX/RX for external sigma-delta CODEC
© Generalplus Technology Inc. Proprietary & Confidential
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Version: 1.0 3. BLOCK DIAGRAM ARM7TDMI With 8KB I/D cache 256KB LIM 128KB LDM SPI Flash Controller BCHMP3 8KB WMA RAM WMA MUX DMA AHB2APB Bridge SD1 SD2 UART SPI I2C I2S TX I2S RX TimerTimeBaseGPIO RTC DAC ADC Interrupt Binary Transform CSI TFT SPU NAND USB20 APB ARM sub-system AHB
© Generalplus Technology Inc. Proprietary & Confidential
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Version: 1.0 4. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
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Version: 1.0 5. REVISION HISTORY Date Revision # Description Page Nov 18, 2013 1.0 First edition 6