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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for an y errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus. DATA SHEET Jun 02, 201 6 Version 1.2 GGPPCCEE22004488AA 16-bit Sound Controller with 24K X 16 ROM

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Version: 1.2 Table of Contents PAGE

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Version: 1.2 16-BIT SOUND CONTROLLER WITH 24K X 16 ROM

1 GENERAL DESCRIPTION

GPCE2048A, a 16-bit architecture sound controller, features the 16-bit ’nSP™ microprocessor developed by Sunplus Technology. This high processing speed assures the ’nSP™ is capable of handling complex digital signal process ing easily and rapidly. GPCE2048A is applicable to the areas of digital sound processing and voice recognition. The operatin g voltage of 2.4V through 5.5V and speed of 0. 16MHz through 49.152MHz yield GPCE2048A to be utilized in varieties of applications. The memory capacity includes 24K-word ROM and a 2K -word working SRAM. Other features include 20 programmable multi-functional I/Os, three 16-bit timers/counters, 32768Hz Real Time Clock, Low Voltage Reset/Detection, four channels 12 -bit ADC (one channel built-in MIC amplifier with auto gain controller), one 14-bit DAC with push-pull amplifier and many others.

2 FEATURES

 16-bit ’nSP™ microprocessor  CPU Clock: 0.16MHz - 49.152MHz  Operating Voltage: 2.4V - 5.5V  Power regulator built-in with input voltage: 2.4~5.5V, output voltage: 2.4~3.3V  IO PortA & B Operating Voltage: 2.4V - 5.5V  24K-word fast speed ROM  2K-word working SRAM  Software-based audio processing  Two sets of 14-bit software channel with noise filter, mixer and scalar to play high quality sound  Standby mode for power saving  Three 16-bit timers/counters  One 14-bit DAC with push-pull amplifier. Supports cascade mode  20 general I/Os (bit programmable)  Key wakeup function (IOA0 - 15)  PLL feature for system clock  32768Hz Real Time Clock (RTC), crystal or internal resistor oscillator selected.  Four channels of 12-bit AD converter  ADC  Built-in microphone amplifier and AGC or PGA function selected  Low voltage reset and low voltage detection  Watchdog Enable (option)  One SPI serial interface I/O

3 APPLICATION FIELD

 Voice Recognition Product  Intelligent Interactive Talking Toy  Advanced Educational Toy  Kids Learning Product  Kids Storybook  General Speech Synthesizer  Long Duration Audio Product  Recording / Playback Product

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4 BLOCK DIAGRAM

un'SP 16-bit CPU AD Converter MIC 16-bits Counter/Timer / Interrupt General I/O Port 2K words Working SRAM PLL / System clock / Reset Function Memory Mapping & Control X32I X32O IOA[15:0] IOB[3:0] MICIP MICIN RESETB 24K words / GPIO Special Function TimeBase/WatchDog / PWM output Fast-speed ROM SPI MICO OPI AGC VMIC VADREF Push Pull DAC AUDP Regulator AUDN ACIN

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5 SIGNAL DESCRIPTIONS

PORT A, Port B IOA[15:0] I/O IOA[15:0]: bi-directional I/O ports It can be programmed as wakeup I/O pins IOB [3:0] I/O IOB [3:0]: bi-directional I/O ports Power & GND VDD_IOA P Power VDD for Port A VSS_IOA G Power GND for Port A VDD_IOB P Power VDD for Port B VSS_IOB G Power GND for Port B V33_ADC P Power VDD for AD(3.3V) VSS_ADC G Power GND for AD V33_REG P 3V power output from regulator VDD_REG P Positive supply for regulator(2.4V~5.5V) VSS_REG G Ground reference for regulator VDD_DAC P Positive 5V supply for push-pull DAC VDD_PDAC P Positive 5V supply for push-pull DAC post driver VSS_DAC I Ground reference for push-pull DAC VSS_ PDAC I Ground reference for push-pull DAC post driver CLK SYSTEM/ ICE INTERFACE XTI I 32KHz Oscillator crystal input XTO O 32KHz Oscillator crystal output OPTION TEST I TEST Mode selection pin, do not connect the pin TEST2 I TEST2 Mode selection pin, do not connect the pin TEST3 I TEST3 Mode selection pin, do not connect the pin R32SEL I R32K or Xtal32K select. Connected to VSS when Xtal32K is selected, and connected to V33_REG when R32K is selected. DAC AUDP O Audio output of push pull DAC AUDN O Audio output of push pull DAC ACIN U Audio analog mixer in ADC MICP I MIC amplifier input positive (Internal Floating) MICN I MIC amplifier input negative (refer to application circuit) MICOUT O MIC amplifier output (refer to application circuit) OPI I Audio amplifier negative input (refer to application circuit) AGC IO AGC by pass filter (refer to application circuit) VMIC O Microphone power supply VADREF O AVREF_DA reference pin PLL VCOIN I PLL low pass filter input Other Signal RESETB I System reset pin (active low) (internal 47Kohm pull high resistor)

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5.1 PIN Map

IOA[15] IOA[14] IOA[13] IOA[12] IOA[11] IOA[8] IOA[9] IOA[10] VDD_IOA VSS_IOA IOA[6] IOA[7] IOA[1] IOA[2] IOA[3] IOA[4] IOA[5] IOA[0] VDD_REG V33_REG TEST2 VSS_REG R32SEL TEST3 NC RESETB XTO XTI TEST VSS_ADC V33_ADC IOB[0] IOB[1] IOB[2] IOB[3] NC NC NC NC VDD_IOB VSS_IOB NC NC NC NC NC NC NC VSS_PDAC AUDN VDD_PDAC VDD_DAC AUDP VSS_PDAC VSS_DAC ACIN NC NC NC NC NC

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6 FUNCTION DESCRIPTIONS

6.1 CPU

The GPCE2048A is equipped with a 16 -bit ’nSP™ microprocessor developed by Sunplus. Eight registers are involved in ’nSP™: R1 - R4 (General -purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) and SR (Segment Register). The interrupts include three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt Request), plus one software-interrupt, BREAK.

6.2 Memory

6.2.1 SRAM

The amount of SRAM is 2K -word (including Stack), ranged from $0000 through $07FF with access speed of two CPU clock cycles. Fosc/n n:1,2,4,8,16,32,64 b2 b1 b0 of P_SystemClock(W)($2030H) CPU clock frequency selection CPU Clock32768Hz X'tal b7,b6,b5 of P_SystemClock(W)($2030H) System clock frequency selection (Default : Fosc/8) Phase Lock Loop (PLL) System Clock generator PLL OUT FOSC b7 b6 b5 24.576MHz(default) 20.48MHz 32.768MHz 40.96MHz 49.152MHz

6.2.2 ROM

GPCE2048A features a 24K-word high-speed memory with access speed of two CPU clock cycles.

6.3 PLL, Clock, Power Mode

6.3.1 PLL (Phase Lock Loop)

The purpose of PLL is to provide a base frequency (32768Hz) and to pump the frequency from 20.48MHz to 49.152MHz for system clock (FOSC). The default PLL frequency is 24.576MHz.

6.3.1.1 System clock

Basically, the system clock is provided by PLL and programmed by the Port_SystemClock (R/W) to determine the clock frequency for system. The default system clock FOSC = 24.576MHz and CPU clock is FOSC/8 if not specified. The initial CPU clock is Fosc/8 after system wakes up and adjusts to desired CPU clock via programming the Port_SystemClock ( R/W). This avoids ROM reading failure when system awakes. 6.3.1.2 32768Hz RTC The Real Time Clock (RTC) is normally used in watch, clock or other time related products. A 2Hz -RTC (0.5 seconds) function is loaded in GPCE2048A. The RTC counts the time as well as to wake CPU up whenever RTC occurs. Since the RTC is generated each 0.5 seconds, time can be traced by the number of RTC occurrences. In addition, GPCE2048A supports 32768Hz crystal oscillator in normal mode and auto-power-saving mode. In normal mode, 32768Hz OSC always run s at the highest power consumption. In auto-power-saving mode, however, it runs at normal mode for the first 7.5 seconds and switches back to power-saving mode automati cally to save powers.

6.4 Standby Mode

The GPCE2048A features a power savings mode (or called standby mode ) for low power applications. To enter standby mode, the desired key wakeup port (IOA[15:0]) must be configured to input first. And read the P ort_IOA_Data to latch the IOA state before entering the standby mode. Also remember to enable the corresponding interrupt source(s) for wakeup. After that, stop the CPU clock by writing $5555 into Port_System_Sleep(W) to enter standby mode. In such mode, SRAM an d I/Os remain in the previous states until CPU being awakened. The wakeup sources in GPCE2048A include KEY wakeup (IOA[15:0]), RTC wakeup, FIQ and IRQ0 - IRQ7. After GPCE2048A is aw akened, CPU will continue to execute the program from where it slept . Programmer can also enable or disable the 32768Hz RTC when CPU is in standby mode.

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6.5 Low Voltage Detection and Low Voltage Reset

6.5.1 Low voltage detection (LVD)

The Low Voltage Detect ion (LVD) reports the circumstance of present voltage. There are four LVD leve ls to be selected: 2.6V, 2.8V, 3.0V, and 3.2V. Those levels can be programmed via P_LVD_Ctrl. As an example, suppose LVD is given 2.8V. When the voltage drops below 2.8V, the b1 2 of P_LVD_Ctrl is read as HIGH. In such state, program can be designed to react this condition.

6.5.2 Low voltage reset

In addition to the LVD, the GPCE2048A has another important function, Low Voltage Reset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below LVR level. Without LVR, the CPU becomes unstable and malfunctions when the operating voltage drops below LVR level. T he LVR will reset all functions to the initial operational (stable) states when the voltage drops below LVR level.

6.6 Interrupt

The GPCE2048A has 1 3 interrupt sources, grouped into two types: FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The pr iority of FIQ is higher than IRQ. FIQ is a high-priority interrupt while IRQ is the low -priority one. An IRQ can be interrupted by a FIQ, but n ot by another IRQ. A FIQ cannot be interrupted by any other interrupt sources. Interrupt Source Interrupt Name / FIQ Name IRQ Priority Timer A IRQ0_TMA/FIQ_TMA 1(High) Timer B IRQ1_TMB/FIQ_TMB 2 Timer C IRQ2_TMC/FIQ_TMC 3 SPI IRQ3_SPI/FIQ_SPI 4 Key wakeup IRQ5_KEY/FIQ_KEY 5 EXT1 IRQ5_EXT1/FIQ_EXT1 6 EXT2 IRQ5_EXT2/FIQ_EXT2 7 4096Hz IRQ6_4KHz/FIQ_4KHz 8 2048Hz IRQ6_2KHz/FIQ_2KHz 9 512Hz IRQ6_512Hz/FIQ_512Hz 10 64Hz IRQ7_64Hz/FIQ_64Hz 11 16Hz IRQ7_16Hz_FIQ_16Hz 12 2Hz IRQ7_2Hz/FIQ_2Hz 13(Low)

6.7 I/O

Two I/O ports are built in GPCE2048A - PortA and PortB, total has 20 bit-programmable I/Os. The PortA is a general purpose I/O with programmable wakeup capability , i.e. IOA [15:0] is the key wakeup port. To activate key wakeup function, latch data on Port_IOA_Data and enable the key wakeup function. Wakeup is triggered when the PortA state is different from at the time latched. Furthermore, the I/O ports can be operated at 5V level, higher than the CPU core which is a 3V level system. Suppose system o perating voltage is running at 3.3V, VDDIO (power for I/O) operates from 3.3V to 5.5V. In such condition, the I/O pad is capable of operating from 0V through VDDIO. The following diagram is a n I/O schematic. Although data can be written into the same register through Port_Data and Port_Buffer, they can be read from different places, Buffer (R) and Data (R). Register Control logic pull high pull low Pin pad Buffer(R) Data(R) Port_Data(W) Port_Buffer(W) Port_DIR(R/W) Port_ATTR(R/W) In addition to a general purpose I/O port function, Port A/B also shares/carries some special functions. A summary o f Port A/B special functions is listed as follows:

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6.8 Special Function in Port

Port Special Function Function Description Note IOA0 IO_PWM IO_PWM Output Refer to Timer section IOA1 IROUT IR Output - IOA2 - - - IOA3 - - - IOA4 High driving I/O - - IOA5 High driving I/O - - IOA6 High driving I/O - - IOA7 High driving I/O - - IOA8 Feedback Input1 - Refer to below Example 1 EXT1 External interrupt source 1 (negative edge triggered) Set IOA8 as floating input mode IOA9 Feedback Output1 Work with IOA8 by adding a RC circuit between them to get an OSC to EXT1 interrupt Set IOA9 as inverted output IOA10 Feedback Input2 - Refer to below Example 1 EXT2 External interrupt source 2 (negative edge triggered) Set IOA10 as floating input mode IOA11 Feedback Output2 Work with IOA10 by adding a RC circuit between them to get an OSC to EXT2 interrupts Set IOA11 as inverted output IOA12 SPI CS SPI chip select Refer to SPI section IOA13 SPI CK SPI clock Refer to SPI section IOA14 SPI TX SPI data output Refer to SPI section IOA15 SPI RX SPI data input Refer to SPI section IOB0 AN0 ADC Channel 0 Refer to ADC section IOB1 AN1 ADC Channel 1 Refer to ADC section IOB2 AN2 ADC Channel 2 Refer to ADC section IOB3 AN3 ADC Channel 3 Refer to ADC section IOA[15:0], IOB[3:0] Io toggle Io toggle function Refer to IO Special Functions section Refer to the above table, t he configuration of IO A9, IOA10, IOA11, and IOA12 involves feedback function in which an OSC frequency can be obtained from EXT1 (EXT2) by simply adding a RC circuit between IOA8 (IOA10) and IOA9 (IOA11).

6.9 Timer / Counter

GPCE2048A provides t hree 16-bit timers/counters - TimerA, TimerB and TimerC or so called universal counter s. The clock source of Timer A/B /C are from clock source Input 1 and clock source Input 2 (see below table) which perform AND operation to form the varieties of combinations. When timer overflows, a timeout signal (TAOUT) is sent to CPU interrupt module to generate a timer interrupt signal. In addition, Timer A/B /C hardware interrupt events can be used to latch the DAC audio output and trigger ADC conversion. Example to Timer A, sending a write signal into TMA_CNT, the value of TMA_DATA (value=N) will reload into T MA_CNT and set an appropriated clock source. Timer wills up-count from N, N+1, N+2… 0XFFFF. An INT signal is generated at the moment of timer rolling over from “0xFFFF” to “0x0000”, and an INT signal is processed by INT controller immediately. At the same time, N will be reloaded into TMA_CNT and start counting again. In Timer A, the clock Input 1 is a high frequency source and clock Input 2 is a low frequency clock source. The combination of clock Input 1 and input 2 provides varieties of speeds to TimerA/CounterA - “1” representing pass signal (not gati ng), and “0” meaning timer deactivated. For instance, if Input 1= ”1”, the clock is depending on Input 2. If Input 1= ”0”, the TimerA is deactivated. The EXT1/ETX2 is the external clock source 1 and external clock source 2. TMXSEL Input 1 Input 2 0000 ‘0’ ‘0’ 0001 ‘1’ ‘1’

0010 FRTC EXT2

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0011 FPLL EXT2

0100 EXT2 64Hz

0101 EXT2 16Hz

0110 EXT2 2Hz

0111 EXT2 ‘1’

1000 FRTC 64Hz

1001 FRTC 16Hz

1010 FRTC 2Hz

1011 FRTC ‘1’

1100 FPLL 64Hz

1101 FPLL 16Hz

1110 FPLL 2Hz

1111 FPLL ‘1’

The following clock source A/B/C means clock s ource for Timer A/B/C respectively. Generally speaking, the clock source A and C are fast clock sources and source B comes from RTC system (32768Hz). Therefore, clock source B can be utilized as a precise counter for ti me counting, e.g., the 2Hz clock can be used for real time counting.

6.9.1 IO PWM

One IO PWMs which duty is selected from 1/ 256 to 254/256. Example the below figure is a 3/256-duration cycle. The PWMO waveform is made by sel ecting a pulse width through Port_PWM_Ctrl. As a result, each 256 cycles will generate a pulse width defined in control port. These PWM signals can be applied for controlling the speed of motor or other devices. Tpwmo Tduty PWMO TimerA_Timeout ... ... ... 1 2 3 4 5 6 7 8 9 1 2 3 4 5251 252 253 254 255 256

6.9.2 Timebase

Timebase, generated by 32768Hz crystal oscillator, is a combination of frequency selection. Furthermore, timebase generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt sources (FIQ6/IRQ6, FIQ7/IRQ7) for Real-Time-Clock

6.10 Sleep Mode, Wakeup, Halt Mode, and Watchdog

6.10.1 Sleep and wakeup modes

1) Sleep: After power -on reset, IC starts running until a sleep command is issued. When a sleep command is accepted, IC will turn the system clock (PLL) off. After all, it enters sleep mode. 2) Wakeup: CPU awaking from sleep mode requires a wakeup signal to turn the system clock (PLL) on. The FIQ/IRQ signal makes CPU to complete the wakeup process and initialization. The CPU wakeup source is given in the following table. Wakeup Source FIQ source Timer A interrupt Timer B interrupt Timer C interrupt SPI interrupt EXT1/EXT2/KEY RTC

6.10.2 Watchdog Reset

The GPCE2048A provides an other important feature - watchdog reset. If the watchdog function is enabled , a reset signal is generated to reset system when watchdog counter is overflow. The purpose of watchdo g is to monitor whether the system operates normally. Within a certain period, watchdog register must be cleared. If it is not cleared, CPU assumes the program has been running in an abnormal condition. As a result, the CPU will reset the system to the initial state and start running the program all over again.

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6.11 Soft Reset Protection

Software reset . Writes $5555 into P_System_Reset will reset the whole system like hardware reset (pull low RESETB pin), except a flag will set on in P_System_LVD_Ctrl(R/W).

6.12 ADC (Analog to Digital Converter) / DAC

The GPCE2048A has four channels 12-bit ADC (Analog to Digital Converter). The function of an ADC is to convert analog signal to digital signal, e.g. a voltage level into a digital word. The four channels of ADC can be four channels of line-in from IOB [3:0] or one channel microphone (MIC) input through amplifier PGA controller, and AGC controller. The MIC amplifier circuit is capable of reducing common mode noise by transmitting signals through differential MIC Inputs (MICN, MICP). Moreover, an external resistor can be applied to adjust microphone gain and time of AGC operating. The AD needs to select source of line-in before conversion. The ADC take s pad (VDD_ADC) as voltage reference.

6.13 SPI

A Serial Peripheral Interface (SPI) controller is built in GPCE2048A to facilitate communicating with other devices and components. There are four control signals on SPI - SPICS (IOA12), SPICK (IOA13), SDO (IOA14), and SDI (IOA15). D7 D6 D4D5 D2D3 D0D1 D7 D6 D5 D3D4 D2 D0D1 SPICK(POL=0) SPICK(POL=1) SDO SDI SPICS PHASE = 0 D7 D6 D4D5 D2D3 D0D1 D7 D6 D5 D3D4 D2 D0D1 SPICK(POL=0) SPICK(POL=1) SDO SDI SPICS PHASE = 1

6.14 Audio Algorithm

The following speech types can be used in GPCE2048A: PCM, SACM_S200, SACM_S480, SACM_S530, SACM_A1600, SACM_A1601, SACM_A1800, SACM_A3400pro, SACM_A3600, SACM_DVR520, SACM_DVR1600, SACM_DVR1800, SACM_DVR3200, and SACM_DVR4800. For melody synthesis, the GPCE2048A supports SACM_MS01 (FM) and SACM_MS02 (wave-table) synthesizers.

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7 ELECTRICAL SPECIFICATIONS

7.1 Absolute Maximum Ratings

Characteristics Symbol Ratings DC Supply Voltage V+ < 4.0V PortA/B Pad Supply Voltage VIO < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions see DC Electrical Characteristics. 7.2 DC Characteristics (VDD = 3.3V, VDDIO = 4.5V (PortA & B), TA = 25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD 2.7 3.3 3.6 V - Operating Current IOP - 13 - mA FOSC = 49.152MHz, AD, DAC disable, non-loading Standby Current ISTB - - 5 A Disable 32KHz crystal 10 A Enable 32KHz,Disable PLL(FOSC) Input High Level VIH 0.7VDDIO - - V - Input Low Level VIL - - 0.3VDDIO V - Output High Current IOH - -20 - mA VOH = 0.7VDD Output Low Current IOL - 20 - mA VOL = 0.3VDD Output Low Current (PA[7:4]) IOL - 40 - mA VOL = 0.3VDD Input Pull-Low Resister (PA[15:0]) RPL - 120 - K VIN = VDD Input Pull-Low Resister (PB[3:0]) RPL - 1200 - K VIN = VDD Input Pull-High Resister RPH - 110 - K VIN = VSS Internal ROSC f requency deviation ⊿F/F -3% 32768 +3% HZ V33_REG = 3.3V 7.3 DC Characteristics (VDD = 3.3V, VDDIO = 3.3V (PortA & B), TA = 25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD 2.7 3.3 3.6 V - Operating Current IOP - 13 - mA FOSC = 49.152MHz, AD, DAC disable, non-loading Standby Current ISTB - - 3 A Disable 32KHz crystal 6 A Enable 32KHz,Disable PLL(FOSC) Input High Level VIH 0.7VDDIO - - V - Input Low Level VIL - - 0.3VDDIO V - Output High Current IOH - -11 - mA VOH = 0.7VDD

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Version: 1.2 Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Output Low Current IOL - 11 - mA VOL = 0.3VDD Output Low Current (PA[7:4]) IOL - 25 - mA VOL = 0.3VDD Input Pull-Low Resister (PA[15:0]) RPL - 120 - K VIN = VDD Input Pull-Low Resister (PB[3:0]) RPL - 1200 - K VIN = VDD Input Pull-High Resister RPH - 110 - K VIN = VSS Internal ROSC f requency deviation ⊿F/F -3% 32768 +3% HZ V33_REG = 3.3V 7.4 ADC Characteristics (VDD = 3.3V, TA = 25℃) Characteristics Symbol Limit Unit Min. Typ. Max. ADC LINE_IN Input Voltage Range from IOB[3:0] VINL (Note 1) VSS-0.3 - VDD+0.3 V ADC Microphone Input Voltage Range VINM VSS-0.3 - VDD+0.3 V Resolution of ADC RESO - - 12 bits Signal-to-Noise Plus Distortion of ADC from Line in SINAD (Note 3) - 55 - dB Effective Number of Bit ENOB (Note 4) 8.0 9.0 - bits Integral Non-Linearity of ADC INL - ±8.0 - LSB (Note 2) Differential Non-Linearity of ADC DNL (Note 6) - ±3 - LSB AD Conversion Rate FCONV - - FCPU/256 Hz Microphone Amplifier Gain A MIC - - 42(Note 5) dB Note1: Internal protection diodes clamp the analog input to VDD and VSS. These diodes allow the analog input to swing from (VSS -0.3V) to (VDD+0.3V) without causing damage to the devices. Note3: The SINAD testing condition at VINLp-p = 0.8*VDD, FCONV = Fcpu/512 = 49MHz/256 = 192KHz, Fin=1.0KHz Sine waves at VDD = 3.0V from IOB [3:0] input. Note4: ENOB = (SINAD-1.76)/6.02. Note5: The microphone amplifier maximum gain = 15 * (60K/(1.5K+REXT) V/V. The REXT is external resistor between OPI and MIC OUT. The gain is 132V/V (=42dB) when REXT is 5.1K. 7.5 DAC Characteristics (V50_DAC = 5.0V, TA = 25℃) Characteristics Symbol Limit Unit Min. Typ. Max. DAC Resolution RESO - - 14 bit Noise at No Signal - - -97 - dBr A Dynamic Range(-60dB) - - -82 - dBr A

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7.6 Regulator Characteristics (TA = 25℃)

Min. Typ. Max. Input Voltage VREGI 2.3 4.5 5.5 V Maximum Current Output IREGO - - 60 mA VDD5V (Regulator in )= 4.5V, VDD (Regulator out ) <100mV Output Voltage VREGO 2.3 3.3 3.3 V Standby Current IRGES - 2.5 - uA

7.7 Pull High Resister and VDDIO

VDD(V) RPH (KΩ)

7.8 Pull Low Resister and VDDIO (Normal PAD)

110.6 110.7 110.8 110.9 111.0 111.1 111.2 111.3 111.4 111.5 2 3 4 5 6 VDD(V) RPL (KΩ)

7.9 Pull Low Resister and VDDIO (IOB[3:0] PAD with

input high) 1102.00 1102.05 1102.10 1102.15 1102.20 1102.25 1102.30 1102.35 2 3 4 5 6 VDD(V) RPL (KΩ)

7.10 I/O Output High Current IOH and VDDIO

Test Condition: VOH = 0.7 * VDDIO 2 3 4 5 6 VDD(V) IOH (mA)

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7.11 I/O Output Low Current IOL and VDDIO (Normal

Pad) Test Condition: VOL = 0.3 * VDDIO (Normal PAD) -30 -25 -20 -15 -10 2 3 4 5 6 VDD(V) IOL (mA)

7.12 I/O Output Low Current IOL and VDDIO (High

driving pad) Test Condition: VOL = 0.3 * VDDIO (High Driving PAD) -70 -60 -50 -40 -30 -20 -10 2 3 4 5 6 VDD(V) IOL (mA)

7.13 Internal ROSC and V33_REG

99.30% 99.40% 99.50% 99.60% 99.70% 99.80% 99.90% 100.00% 100.10% V33_REG(V) 32768HZ

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8 APPLICATION CIRCUITS

8.1 Application Circuit with Regulator, XTAL32K Selected

IOA[15:0] IOA[15:0] IOB[ 3 :0] IOB[ 3 :0] 0.1uF VMIC MICP MICN AGC 0.1uF VADREF OPI MICOUT X32I X32O 32768Hz 20 ~ 50pF*1 VCOIN 3.3K 3300pF 0.1uF 20 ~ 50pF*1 10uF 470K 0.22uF 0.22uF MIC 4.7uF 5.1K 0.22uF 5000pF GPCE2048A RESETB AUDN AUDP 8Ω SPEAKER 0.1uF10uF VSS_REG VSS_DAC (2.4v~5.5v) Battery 0.1uF10uF V33_REGVDD(3.3v) 0.1uF10uF V33_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IOB VSS_IOA VDD_PDAC VDD_DAC VSS_PDAC VDD_REG R32SEL Note1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note2: VDD33_REG is output of built-in regulator with maximum current 60mA. It is recommended that only use it for internal power pad.

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Version: 1.2

8.2 Application Circuit with Regulator, Internal ROSC32K Selected

IOA[15:0] IOA[15:0] IOB[ 3 :0] IOB[ 3 :0] 0.1uF VMIC MICP MICN AGC 0.1uF VADREF OPI MICOUT VCOIN 3.3K 3300pF 0.1uF IOB[3:0] IOB[3:0] ( 4-Channel Line In ) RESETB AUDN AUDP 8Ω SPEAKER GPCE2048A 0.1uF10uF VSS_REG VSS_DAC (2.4v~5.5v) Battery 0.1uF10uF V33_REGVDD(3.3v) 0.1uF10uF V33_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IOB VSS_IOA VDD_PDAC VDD_DAC VSS_PDAC VDD_REG R32SEL Note1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note2: VDD33_REG is output of built-in regulator with maximum current 60mA. It is recommended that only use it for internal power pad.

19 Jun 02, 201 6

Version: 1.2

8.3 Application Circuit without Regulator, XTAL32K Selected

IOA[15:0] IOA[15:0] IOB[3:0] IOB[3:0] 0.1uF VMIC MICP MICN AGC 0.1uF VADREF OPI MICOUT X32I X32O 32768Hz 20 ~ 50pF* VCOIN 3.3K 3300pF 0.1uF 20 ~ 50pF* IOB[3:0] IOB[3:0] ( 4-Channel Line In ) RESETB AUDN AUDP 8Ω SPEAKER GPCE2048A VDDH(2.4v~5.5v) Battery 2.2uF 0.1uF10uF VDDH(2.4v~3.6v) Battery 0.1uF10uF VSS_DAC V33_REG V33_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IOB VSS_IOA VDD_PDAC VDD_DAC VSS_PDAC VDD_REG VSS_REG R32SEL

20 Jun 02, 201 6

Version: 1.2

8.4 Push Pull DAC Mixed with another DAC

1.2K 3.18K VEXT VDACO 127.7K f ESDEXT EXT f inAeq DACO AUDN R RR VR RR VV  f EXT EXT f DACO R K2.1R VR K7.127K18.3 V  AUDNAUDP VV 

21 Jun 02, 201 6

Version: 1.2

9 PACKAGE/PAD LOCATIONS

9.1 Ordering Information

Product Number Package Type GPCE2048A-NnnV-C Chip form GPCE2048A-NnnV-QL04x Halogen Free Package Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number).

9.2 Package Information

LQFP 80 Outline Dimensions Symbol Dimension in mm Min. Typ. Max. A - - 1.60 A1 0.05 - 0.15 A2 1.35 - 1.45 b 0.17 - 0.27 c1 0.09 - 0.16 D 14.00 BSC D1 12.00 BSC

22 Jun 02, 201 6

Version: 1.2 Symbol Dimension in mm Min. Typ. Max. E 14.00 BSC E1 12.00 BSC e 0.50 BSC. L 0.45 - 0.75 L1 1 REF

23 Jun 02, 201 6

Version: 1.2

10 DISCLAIMER

The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulat ed in the terms of s ale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for u se in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical l ife support equipment, are specifically not recommended without additional processing by GENERALPLUS for su ch applications. Please note that application circuits illustrated in this document are for reference purposes only.

24 Jun 02, 201 6

Version: 1.2

11 REVISION HISTORY

Date Revision # Description Page Jun 02, 2016 1.2 Modify pin descriptions of chapter 5. 6 Jan 21, 2013 1.1 Correct the number of IOB and DAC channel. 24 Oct 30, 2012 1.0 Original 24

Product Information

GPCE2048A specifications and overview.

Summary

16-bit Sound Controller with 24K X 16 ROM

Description

16-bit Sound Controller with 24K X 16 ROM

Source title GPCE2048A Datasheet(PDF) - Generalplus Technology Inc.

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