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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this doc ument. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus. DATA SHEET Feb. 08, 20 17 Version 1.5 GGPPCCDDXXXXXXXXAA SSeerriieess MMuullttii--CChhaannnneell SSoouunndd CCoonnttrroolllleerr
© Generalplus Technology Inc. Proprietary & Confidential 2 Feb. 08, 2017 Version: 1.5 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 Feb. 08, 2017 Version: 1.5 MULTI-CHANNEL SOUND CONTROLLER 1. GENERAL DESCRIPTION The GPCDXXXXA series works with internal 128K~1M bytes ROM, 512 byt es working SRAM, three sets of 12-bit timer, 16~32 general I/Os with selectable 8+1/4+2/1+2 channels of input and one 14-bit DAC with push -pull amplifier . In audio signal processing, melody and speech can be mixed into one output. The GPCDXXXXA features up to two software channels and a high performance SPU voice engine to playback voice in ADPCM or PCM format. It is designed to operate over a wide voltage range along with low voltage reset function to assure the capability of operating at a n extremely low voltage condition . In addition , GPCDXXXXA supports a sleep mode to save powers when power resource is limited such as power from ordinary battery or solar cell. While in standby mode, it can be rapidly awaked from sleep mode by interrupt source s or IO state alterations. A Serial Peripheral Interface (SPI) controller is also available in certain GPCDXXXXA series to facilitate communicati ons with other devices and components. 2. FEATURES Working Voltage: 2.1V/2.3V - 5.5V (by body option) CPU Speed: max. 8MHz. FOSC = max. 16MHz (2 x CPU clock) ROM Size: 128KB~1M bytes (by body) RAM Size: max. 512 bytes Three 12-bit timer/counter, TMA with capture and comparison function, TMB/TMC with comparison function only (Programmable and Auto Reload) Sleep mode to reduce power consumption Key change wake-up function IRQs & NMI Interrupts Clock source with ROSC or XTAL (option) Watchdog function (option) 5.5V to 3.3V regulator Low Voltage Reset and Low Voltage Detection Bit programmable 16~32 general I/Os (by body) Eight I/Os with high sink current for LED application All general IOs with 1M -Ohm pull-low function to prevent current leakage from key touch error. One 14-bit DAC with push-pull amplifier for direct drive speaker SPU(Sound Processing Unit) en gine can output audio data with 14-bit resolution to perform high quality voice/melody IR PWM Output Hardware PWMIO supports four LED outputs with brightness control of 256-level Real-time clock 8/4/1-channel SPU engine with ADPCM/PCM wave table (by body option) Up to two sets of 14 -bit software channel with noise filter to playback high quality sound SPI master interface (by body) 3. APPLICATION FIELD Talking instrument controller General Music synthesizer General purpose controller High end toy controller Intelligent education toys And more
© Generalplus Technology Inc. Proprietary & Confidential 4 Feb. 08, 2017 Version: 1.5 4. BLOCK DIAGRAM 8-Bit controller 512 Bytes SRAM 128KB~1MB ROM (by body) Max. 32 General I/O,IOA,IOB,IOC,IOD (IOB with Special Function) 12 - Bit Timer / Counter A 12 - Bit Timer / Counter B 12 - Bit Timer / Counter C 8/4/1-CH SPU Max. 2-CH Software (by body) Digital Mixer 14-Bit Push-Pull DAC IOA 0 ~ 7 IOB 0 ~ 7 IOC 0 ~ 7 XI XO
8 Bit X 8 Bit
IOD 0 ~ 7 Regulator/LVR/Porst RESETB SPI (by body) PWMIO IOB0~3 IOD0~3 AUDP AUDN GPCDXXXXA Family (by body) (by body)
© Generalplus Technology Inc. Proprietary & Confidential 5 Feb. 08, 2017 Version: 1.5 5. GPCDXXXXA FAMILY AND FEATURE LIST Body GPCD9340A GPCD6340A GPCD3340A GPCD9300A GPCD6300A - Working Voltage FOSC = Max. 16M Working Voltage FOSC = Max. 12M RAM Size 512B 512B 512B 512B 512B - ROM Size 1MB 1MB 1MB 912KB 912KB - IO Pin 32 (IOA/B/C/D) 32 (IOA/B/C/D) 32 (IOA/B/C/D) 32 (IOA/B/C/D) 32 (IOA/B/C/D) - SPU Channel 8 4 1 8 4 - Software Channel 1 2 2 1 2 - SPI V V V V V - Body GPCD9270A GPCD6270A GPCD3270A GPCD9220A GPCD6220A - Working Voltage FOSC = Max. 16M Working Voltage FOSC = Max. 12M RAM Size 512B 512B 512B 512B 512B - ROM Size 832KB 832KB 832KB 672KB 672KB - IO Pin 32 (IOA/B/C/D) 32 (IOA/B/C/D) 32 (IOA/B/C/D) 32 (IOA/B/C/D) 32 (IOA/B/C/D) - SPU Channel 8 4 1 8 4 - Software Channel 1 2 2 1 2 - SPI V V V V V - Body GPCD9170A GPCD6170A GPCD3170A GPCD9130A GPCD6130A GPCD3130A Working Voltage FOSC = Max. 16M RAM Size 512B 512B 512B 512B 512B 512B ROM Size 512KB 512KB 512KB 416KB 416KB 416KB IO Pin 24 (IOA/B/D) 24 (IOA/B/D) 24 (IOA/B/D) 24 (IOA/B/D) 24 (IOA/B/D) 24 (IOA/B/D) SPU Channel 8 4 1 8 4 1 Software Channel 1 2 2 1 2 2 SPI V V V V V V Body GPCD9080A GPCD6080A GPCD3080A GPCD9040A GPCD6040A GPCD3040A Working V oltage FOSC = Max. 16M RAM Size 512B 512B 512B 512B 512B 512B ROM Size 256KB 256KB 256KB 128KB 128KB 128KB IO Pin 16 (IOA/B) 16 (IOA/B) 16 (IOA/B) 16 (IOA/B) 16 (IOA/B) 16 (IOA/B) SPU Channel 8 4 1 8 4 1 Software Channel 1 2 2 1 2 2 SPI X X X X X X
© Generalplus Technology Inc. Proprietary & Confidential 6 Feb. 08, 2017 Version: 1.5 6. Signal descriptions 6.1. Signal Description for GPCDXXXXA Name Type Description Note IO PORT IOA0~IOA7 I/O Bi-directional IO ports, can be wakeup pins IOA0~3 high sink, available for GPCDXXXXA series IOB0~IOB7 I/O Bi-directional IO ports, can be wakeup pins IOB0~3 high sink, available for GPCDXXXXA series IOC0~IOC7 I/O Bi-directional IO ports, can be wakeup pins Available for GPCDX340A/300A/270A/220A IOD0~IOD7 I/O Bi-directional IO ports, can be wakeup pins Available for GPCDX340A/300A/270A/220A/170A/130A Clock related XO O Oscillator crystal output XI I Oscillator crystal input/ROSC input POWER PAD VDD_REG P Positive supply for regulator (2.1/2.3~5.5V) Working voltage refers to “GPCDXXXXA Family and Feature List” in page-5 VDD_DAC1 P Positive supply for amplifier (2.1/2.3~5.5V) Working voltage refers to “GPCDXXXXA Family and Feature List” in page-5 VDD_DAC2 P Positive supply for DAC (2.1/2.3~5.5V) Working voltage refers to “GPCDXXXXA Family and Feature List” in page-5 VDD_IO1 P Positive supply for IOB,IOC (2.1/2.3~5.5V) Working voltage refers to “GPCDXXXXA Family and Feature List” in page-5 VDD_IO2 P Positive supply for IOA,IOD (2.1/2.3~5.5V) Working voltage refers to “GPCDXXXXA Family and Feature List” in page-5 VDD P Core power from regulator and recommended connect it to VDD33 via PCB It is not allowed for external components power sour ce. Short to VDD33 internally. VDD33 P Core power output from regulator It is not allowed for external components power source . Short to VDD internally. VSS_REG G Ground reference for regulator VSS G Ground reference for GPIO and core circuit VSS_DAC1~2 G Ground reference for amplifier X2 VSS_DAC3 G Ground reference for DAC Others RESETB I External reset pin(active low) Internal pull-high TEST I For test mode, NC for normal application Internal pull-low AUDP O Audio output of push-pull DAC AUDN O Audio output of push-pull DAC *Note: (1) VDD pad is recommended to be bonded for stability issue even VDD33 is shorted to VDD internally. (2) IO special function and allocation please refer to 7.6.1 IO configuration. (3) For more details about pad information, please refer to respective “Pad Assignment and Locations” document of GPCDXXXXA series. (4) VDD33 and VDD are dedicated to GPCDXXXXA internal circuits, external component power source not allowed.
© Generalplus Technology Inc. Proprietary & Confidential 7 Feb. 08, 2017 Version: 1.5 6.2. LQFP64 Package Pin Assignment for GPCDX3XXA & GPCDX2XXA 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IOC[6] IOC[7] VSS_DAC2 NC AUDP NC NC NC VSS_DAC3 NC VSS_DAC1 NC NC 60 59 58 57 56 55 54 53 52 51 50 49 48 NC 616263 NC XI XO NC NC VDD VDD_IO2 IOD[7] IOD[6] IOD[5] IOD[4] IOD[3] IOD[2] IOD[1] IOD[0] IOA[7]IOB[6] IOB[7] IOC[4] IOC[5] VDD_IO1 VSS_REG VDD_REG VDD33 NC AUDN IOC[0] IOC[1] IOC[2] IOC[3] NC VDD_DAC1 NC VDD_D AC2 GPCDx3xxA/GPCDx2xxA LQFP64 IOA[6] IOB[4] IOB[3] IOB[2] IOB[1] IOB[0] VSS IOB[5] IOA[0] IOA[1] IOA[2] IOA[3] IOA[4] TEST IOA[5] RESETB
© Generalplus Technology Inc. Proprietary & Confidential 8 Feb. 08, 2017 Version: 1.5 6.3. LQFP64 Package Pin Assignment for GPCDX1XXA 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NC NC VSS_DAC2 NC AUDP NC NC NC VSS_DAC3 NC VSS_DAC1 NC NC 60 59 58 57 56 55 54 53 52 51 50 49 48 NC 616263 NC XI XO NC NC VDD VDD_IO2 IOD[7] IOD[6] IOD[5] IOD[4] IOD[3] IOD[2] IOD[1] IOD[0] IOA[7]IOB[6] IOB[7] NC NC VDD_IO1 VSS_REG VDD_REG VDD33 NC AUDN NC NC NC NC NC VDD_DAC1 NC VDD_D AC2 GPCDx1xxA LQFP64 IOA[6] IOB[4] IOB[3] IOB[2] IOB[1] IOB[0] VSS IOB[5] IOA[0] IOA[1] IOA[2] IOA[3] IOA[4] TEST IOA[5] RESETB
© Generalplus Technology Inc. Proprietary & Confidential 9 Feb. 08, 2017 Version: 1.5 6.4. LQFP48 Package Pin Assignment for GPCDX1XXA IOA[3] IOA[2] IOA[1] IOA[0] IOB[0] RESETB TEST IOA[4] IOB[1] IOB[2] IOB[3] IOB[5] 14 15 16 17 18 19 20 21 22 23 NC NC NC VDD_DAC2 VDD_DAC1 AUDN VSS_DAC1 VDD/VDD33 VSS_DAC3 VSS_DAC2 AUDP VDD_REG VSS_REG 35 XO 12IOB[4] 24VDD_IO1 36 XI IOD[2] IOD[3] IOD[4] IOD[5] IOD[6] IOD[7] VDD_IO2 IOD[1] IOD[0] IOA[7] IOA[6]
48 IOA[5]
IOB[6] IOB[7] NC NC NC NC NC GPCDx1xxA LQFP48
© Generalplus Technology Inc. Proprietary & Confidential 10 Feb. 08, 2017 Version: 1.5 7. FUNCTIONAL DESCRIPTIONS 7.1. SRAM The 512 -byte SRAM (including Stack) area is located in $000000~$0002FF. 7.2. ROM GPCDXXXXA is ca pable of accessing internal ROM . The ROM size for various bodies are indicated in following table: Body ROM Size ROM Address GPCD9/6/3340A 1MB 0x00840~0xFFFFF GPCD9/6300A 912KB 0x00840~0xE3FFF GPCD9/6/3270A 832KB 0x00840~0xCFFFF GPCD9/6220A 672KB 0x00840~0xA7FFF GPCD9/6/3170A 512KB 0x00840~0x7FFFF GPCD9/6/3130A 416KB 0x00840~0x67FFF GPCD9/6/3080A 256KB 0x00840~0x3FFFF GPCD9/6/3040A 128KB 0x00840~0x1FFFF 7.3. Low Voltage Reset The GPCDXXXXA provides another important feature - Low Voltage R eset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below LVR. Without LVR, the CPU becomes unstable and malfunction when working voltage is extremely low. 7.4. Interrupt The GPCDXXXXA has two in terrupt (INT) modes: IRQ (interrupt Request) and NMI (Non -Mask Interrupt Request). The interrupt controller controls fifteen IRQs and seven NMIs. A NMI cannot be interrupted by any other IRQs. Interrupt Source Interrupt Name Priority Timer A NMI_TIMER_A NMI Timer B NMI_TIMER_B NMI Timer C NMI_TIMER_C NMI CPU_CLOCK/1024 NMI_D1024 NMI CPU_CLOCK/4096 NMI_D4096 NMI KEY NMI_KEY NMI EXT NMI_EXT NMI TIMER A IRQ_TIMER_A IRQ1 TIMER B IRQ_TIMER_B IRQ2 TIMER C IRQ_TIMER_C IRQ3 CPU_CLOCK/1024 IRQ_D1024 IRQ4 CPU_CLOCK/4096 IRQ_D4096 IRQ5
16 Hz IRQ_16Hz IRQ6
2 Hz IRQ_2 Hz IRQ7
Interrupt Source Interrupt Name Priority KEY IRQ_KEY IRQ8 EXT IRQ_EXT IRQ9 SPU IRQ_SPU IRQ10 SPI * IRQ_SPI IRQ11 QD1_F IRQ_QD1_F IRQ12 QD1_B IRQ_QD1_B IRQ13 QD2_F IRQ_QD2_F IRQ14 QD2_B IRQ_QD2_B IRQ15 *Note: SPI interrupt is not available for GPCDX080A/040A series. 7.5. Hardware PWMIO Hardware PWMIO supports four LED outputs from IOB0~3 with brightness control of 256 levels. The clock source of PWMIO can be selected by user’s request. 7.6. I/O The purpose of input and output port is mainly to communicate with other devices or components. Maximum 32 programmable I/O ports are built in GPCDXXXXA series, including Port A, Port B, Port C, and Port D (by body option). All ports are general I/Os with programmable wak e-up capability and 1M -Ohm pull-low function. In addition , these ports also provide some special functions in certain pins. PortA0~3 and PortB0~3 supports large sink current for LED application. The Port D0~3 is sharing with SPI function (by body option). Please r efer to following figure for IO Sharing. 7.6.1. I/O Configuration The following diagram is the I/O schematic. I/O A, B, C, D Schematic: Register Control logic pull high pull low Pin pad Buffer(R) Data(R) Port_Data(W) Port_Buffer(W) Port_DIR(R/W) Port_ATTR(R/W) Port_Data and Port_Buffer are written into the same register but reading from different node. To activate key wakeup function, user should latch data on IO X_Data and enable the key wake up function. Wak eup is triggered when the state of port is different from that of latched data.
© Generalplus Technology Inc. Proprietary & Confidential 11 Feb. 08, 2017 Version: 1.5 A summary of IO sharing is listed as following. IO Sharing IOA IOB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Wake up V V V V V V V V V V V V V V V V High sink V V V V V V V V PWMIO V V V V IR(Output) V External INT V External Clock V(TMC) V(TMB) V(TMA) RTC V V IIS out/in V(in) V(in) V(in) V(out) V(out) V(out) QD V(qd2) V(qd2) V(qd1) V(qd1) CC TMC TMB TMA TMC TMB TMA 1M pull low V V V V V V V V V V V V V V V V IOC IOD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Wake up V V V V V V V V V V V V V V V V SPI V(rx) V(tx) V(ck) V(cs) 1M pull low V V V V V V V V V V V V V V V V *Note: (1) QD means quadrature decoder; CC means Capture/Comparison. (2) IOC is available for GPCDX340A/300A/270A/220A. IOD is available for GPCDX340A/300A/270A/220A/170A/130A. 7.7. Timer/Counter (Timer A/Timer B/Timer C) Three 12-bit timers are embedded in GPCD XXXXA: Timer A, Timer B and Timer C. These timers all have a 12 -bit up counter, a preloaded register, and variety of programmable clock source s. Timer A/B can also be the clock source of the software channel 1/2 respectively. The clock source of each timer can be set individually. Two clock sources including CPU clock and external clock can be selected respectively or combination to be timer’s clock source. Furthermore, capture and comparison funct ions are s upported by TMA and in contrast, only c omparison is supported by TMB and TMC. Clock Source 000 001 010 011 100 101 110 Source1 Selection Fcpu/8 32768Hz 16Hz 2Hz Fcpu/256
11 Source2
(PORTAX) EXT input (PORTAX) Fcpu/32
© Generalplus Technology Inc. Proprietary & Confidential 12 Feb. 08, 2017 Version: 1.5 7.8. Sleep, Wakeup and Watchdog 7.8.1. Sleep and Wakeup Sleep mode save s power by stopping clock while device is not in operating. When entering into sleep mode, the d evice runs from operating mode to standby mode. Wake-up from sleep mode returns system back to operating mode. 1). Sleep: After power-on reset, CPU starts operating until a sleep command is given. When a sleep signal is accepted, CPU will turn off system clock and enter into sleep mode. 2). Wake-up: while a n IRQ/NMI interrupt signal is generated, GPCDXXXXA awakes from sleep mode. While wake-up is completed, program counter will continue to execute the following commands. 7.8.2. Watchdog The pur pose of watchdog is to monitor whether a system is operating normally. Within a certain period of time , watchdog must routinely be cleared. It prevents system from incorrect code execution by generating a system reset signal when software is failed to clear watchdog flag within 0.75 second s. Watchdog function can be removed by option. 7.9. Speech and DAC The GPCDXXXXA uses a high performance SPU voice engine to achieve 8 /4/1-channel voice with ADPCM/PCM (by body) . The SPU also supports automatic zero -crossing concatenate function. A hardware multiplier is also embedded in this SPU for software usage. The fixed address of RAM area $0000 - $007F/3F/0F is designed as address pointers and a data buffer for the 8/4/1-channel speech/melody generation. Moreover, up to two sets of 14 -bit software channel with noise filter are equipped. There is one 14-bit D AC with push -pull amplifier for direct audio output. 7.10. SPI Controller A Serial Peripheral Interface (SPI) co ntroller is a significant feature to facilitate communication tasks with other devices and components. The SPI requires four control signals which includes SPICSN, SPICLK (SCK), SPITX (SDO), and SPIRX (SDI); these four signals are shared with IO ports: PortD0, PortD1, PortD2 and PortD3. While SPI module is enabled by respective control bit s. These four pins cannot be GPIOs and any setting on corresponding GPIO control register will have no effect . Four types of timing are presented as follows: MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX MSB MSB Master Mode, SPO = 0, SPH=0 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX Q Q Master Mode, SPO = 0, SPH=1 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX Q Master Mode, SPO = 1, SPH=0
© Generalplus Technology Inc. Proprietary & Confidential 13 Feb. 08, 2017 Version: 1.5 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX Q Q Master Mode, SPO = 1, SPH=1 *Note: SPI is not available for GPCDX080A/040A series. 7.11. Reset Key De-bounce For system stability, reset key de-bounce time for GPCDXXXXA is 48 system clock s. Please refer to the following diagram for de-bounce timing. SYSCLK Reset Key Effective Key Reset 48*SYSCLK
© Generalplus Technology Inc. Proprietary & Confidential 14 Feb. 08, 2017 Version: 1.5 8. ELECTRICAL SPECIFICATIONS 8.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions , see DC Electrical Characteristics. 8.2. DC Characteristics (VDD_IO/VDD_REG=3.0V, TA=25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD 2.1 / 2.3* - 3.6 V For 2-battery Operating Current-1 IOP1 - 9 - mA VDD_IO/VDD_ADC/VDD_REG=3.0V FCPU = 8MHz , DAC on, no load Operating Current-2 IOP2 - 6 - mA VDD_IO/VDD_ADC/VDD_REG=3.0V FCPU = 8MHz , DAC off, no load Standby Current ISTBY - - 3 A VDD_IO/VDD_ADC/VDD_REG=3.0V OSC Frequency FOSC - - 16 MHz VDD_IO/VDD_ADC/VDD_REG=3.0V Input High Level VIH 0.7*VDD - - V - Input Low Level VIL - - 0.3*VDD V - Output High Current (IOA/B/C/D[7:0]) IOH - 5 - mA VDD_IO/VDD_ADC/VDD_REG=3.0V, VOH =2.1V Output Low Sink Current (IOA/B[7:4], IOC/D[7:0]) IOL1 - 10 - mA VDD_IO/VDD_ADC/VDD_REG=3.0V, VOL =0.9V Output Low Sink Current (IOA/B[3:0]) IOL2 - 19 - mA VDD_IO/VDD_ADC/VDD_REG=3.0V, VOL =0.9V Input Pull-Low Resistor (IOA/B/C/D[7:0]) RPL - 1400 - Kohm VDD_IO/VDD_ADC/VDD_REG=3.0V, Vin=3.0V Input Pull-High Resistor (IOA/B/C/D[7:0]) RPH - 155 - Kohm VDD_IO/VDD_ADC/VDD_REG=3.0V, Vin=VSS 8.3. DC Characteristics (VDD_IO/VDD_REG=4.5V, TA=25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current-1 IOP1 - 11 - mA VDD_IO/VDD_ADC/VDD_REG=4.5V FCPU = 8MHz , DAC on, no load Operating Current-2 IOP2 - 7 - mA VDD_IO/VDD_ADC/VDD_REG=4.5V FCPU = 8MHz , DAC off, no load Standby Current ISTBY - - 4 A VDD_IO/VDD_ADC/VDD_REG=4.5V OSC Frequency FOSC - - 16 MHz VDD_IO/VDD_ADC/VDD_REG=4.5V Input High Level VIH 0.7*VDD - - V - Input Low Level VIL - - 0.3*VDD V -
© Generalplus Technology Inc. Proprietary & Confidential 15 Feb. 08, 2017 Version: 1.5 Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Output High Current (IOA/B/C/D[7:0]) IOH - 11 - mA VDD_IO/VDD_ADC/VDD_REG=4.5V, VOH =3.15V Output Low Sink Current (IOA/B[7:4], IOC/D[7:0]) IOL1 - 18 - mA VDD_IO/VDD_ADC/VDD_REG=4.5V, VOL =1.35V Output Low Sink Current (IOA/B[3:0]) IOL2 - 35 - mA VDD_IO/VDD_ADC/VDD_REG=4.5V, VOL =1.35V Input Pull-Low Resistor (IOA/B/C/D[7:0]) RPL - 865 - Kohm VDD_IO/VDD_ADC/VDD_REG=4.5V, Vin=4.5V Input Pull-High Resistor (IOA/B/C/D[7:0]) RPH - 97 - Kohm VDD_IO/VDD_ADC/VDD_REG=4.5V, Vin=VSS 8.4. DAC Characteristics (VDD_IO/VDD_REG/VDD_DAC=4.5V, RL=8Ω, f=1KHz, TA=25℃) Characteristics Symbol Limit Unit Min. Typ. Max. DAC Resolution RESO - - 14 bit Noise at No Signal - - -97 - dBr A Dynamic Range (-60dB) - - -80 - dBr A 8.5. Regulator Characteristics (TA=25℃) Characteristics Symbol Limit Unit Min. Typ. Max. Input Voltage VREGI 2.1 4.5 5.5 V Maximum Current Output IREGO - - 30 mA Output Voltage VREGO 2.1 3.3 3.6 V Standby Current IREGS - - 2.0 uA 8.6. The Relationship between ROSC and FOSC (TA=25℃) 8.7. The Relationship between FOSC and IOP (TA=25℃) Fosc VS. Iop 4.0 6.0 8.0 10.0 12.0 4 6 8 10 12 14 16 Fosc (MHz) Iop (mA) _ 3.0V 4.5V
© Generalplus Technology Inc. Proprietary & Confidential 16 Feb. 08, 2017 Version: 1.5 9. APPLICATION CIRCUITS 9.1. GPCDXXXXA Application Circuit with 32K Crystal Mode and without IO Output Driving Application(ROSC-mode) GPCDXXXXA Reset RESETB VSSB 0.1u VSS_REG VDD_REG VDDB VDD33 VDD 2.2u XO XI 47K VSSB IOA0~7 IOA0~7 IOB0~7 IOB0~7 (Battery Power)(Common Ground) (Regulator Power) VDD_IO1 VSS 10u VDD_DAC1~2 VSS_DAC1~3 AUDN AUDP VDD_IO2 (Battery Power) 8Ω SPEAKER Note: 1. 4Ω speaker application is not allowed in GPCDXXXXA. 2. Above illustration only suggested for no IO heavy driving output, such as only key input trigger and no LED or motor driver output. 3. C1/C2 value may vary with system application. 4. If system is not stable, it is suggested to refer to following 9.3~9.6 circuits. 5. C4/C5 values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~60K and CL1=CL2 =26~36pF (including PCB parasitic loading, for example, user should apply additional 20~30pF on X32I and X32O if PCB parasitic loading is 6pF) IOC0~7 (by body) IOD0~7 (by body) IOC0~7 (by body) IOD0~7 (by body) 25p VSSB *C5 32768Hz 25p *C4 IOB4 IOB5
© Generalplus Technology Inc. Proprietary & Confidential 17 Feb. 08, 2017 Version: 1.5 9.2. GPCDXXXXA Application Circuit without IO Output Driving Application(XTAL-mode) GPCDXXXXA Reset RESETB VSSB 0.1u VSS_REG VDD_REG VDDB VDD33 VDD 2.2u VSSB IOA0~7 IOA0~7 IOB0~7 IOB0~7 (Battery Power)(Common Ground) (Regulator Power) VDD_IO1 VSS 10u VDD_DAC1~2 VSS_DAC1~3 AUDN AUDP VDD_IO2 (Battery Power) 8Ω SPEAKER Note: 1. 4Ω speaker application is not allowed in GPCDXXXXA. 2. Above illustration only suggested for no IO heavy driving output, such as only key input trigger and no LED or motor driver output. 3. C1/C2 value may vary with system application. 4. If system is not stable, it is suggested to refer to following 9.3~9.6 circuits. 5. The values of C4/C5 are for design guidance only, different values may be needed for different crystal/resonator used. XO XI 20p VSSB *C5 12MHz 20p*C4 IOC0~7 (by body) IOD0~7 (by body) IOC0~7 (by body) IOD0~7 (by body)
© Generalplus Technology Inc. Proprietary & Confidential 18 Feb. 08, 2017 Version: 1.5 9.3. GPCDXXXXA Application Circuit with ROSC Option GPCDXXXXA Reset RESETB VSSB 0.1u VSS_REG VDD_REG VDDB VDD33 VDD 2.2u XO XI 47K VSSB IOA0~7 IOA0~7 IOB0~7 IOB0~7 (Battery Power)(Common Ground)(Regulator Power) VDD_IO1 VSS 47u 0.1u VDD_DAC1~2 10u VSS_DAC1~3 AUDN AUDP VDDB VSSB (DAC Power) VDD_IO2 (Battery Power) 8Ω SPEAKER Note: 4Ω speaker application is not allowed in GPCDXXXXA. IOC0~7 (by body) IOD0~7 (by body) IOC0~7 (by body) IOD0~7 (by body)
© Generalplus Technology Inc. Proprietary & Confidential 19 Feb. 08, 2017 Version: 1.5 9.4. GPCDXXXXA Application Circuit with Crystal Option GPCDXXXXA Reset RESETB VSSB 0.1u VSS_REG VDD_REG VDDB VDD33 VDD 2.2u XO XI VSSB IOA0~7 IOA0~7 IOB0~7 IOB0~7 (Battery Power)(Common Ground)(Regulator Power) VDD_IO1 VSS 47u 0.1u VDD_DAC1~2 10u VSS_DAC1~3 AUDN AUDP VDDB VSSB (DAC Power) SPEAKER VDD_IO2 (Battery Power) 20p VSSB *C6 12MHz 20p*C7 Note: 1. 4Ω speaker application is not allowed in GPCDXXXXA. 2. The values of C6/C7 are for design guidance only, different values may be needed for different crystal/resonator used. IOC0~7 (by body) IOD0~7 (by body) IOC0~7 (by body) IOD0~7 (by body)
© Generalplus Technology Inc. Proprietary & Confidential 20 Feb. 08, 2017 Version: 1.5 9.5. GPCDXXXXA Application Circuit with IO Heavy Loading(1):High Sourcing GPCDXXXXA Reset RESETB VSSB 0.1u VSS_REG VDD_REG VDDB VDD33 VDD 2.2u XO XI VSSB IOB0~7 IOB0~7 IOA0 (Battery Power)(Common Ground)(Regulator Power) VDD_IO1 VSS 47u 0.1u C3 VDD_DAC1 10u VSS_DAC1~2 AUDN AUDP VDDB VSSB (AMP. Power) VDD_IO2 (Battery Power) 20p VSSB *C6 12MHz 20p*C7 VDD_DAC2 22u VSS_DAC3 VDDB VSSB (DAC Power) 10ΩR1 Note: 1. 4Ω speaker application is not allowed in GPCDXXXXA. 2. For system stability and performance, it is recommended to add R1/C8 for the applications that IOs toggle with high current sourcing, such as LEDs or motor drivers. 3. The value of R2~R9/C8 depends on applications. Basically, the more IO toggles, the larger C8 is suggested. 4. The values of C6/C7 are for design guidance only, different values may be needed for different crystal/resonator used. IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 VSSB 8Ω SPEAKER IOC0~7 (by body) IOD0~7 (by body) IOC0~7 (by body) IOD0~7 (by body)
© Generalplus Technology Inc. Proprietary & Confidential 21 Feb. 08, 2017 Version: 1.5 9.6. GPCDXXXXA Application Circuit with IO Heavy Loading(2):High Sinking GPCDXXXXA Reset RESETB VSSB 0.1u VSS_REG VDD_REG VDDB VDD33 VDD 2.2u XO XI VSSB IOB0~7 IOB0~7 IOA0 (Battery Power)(Common Ground)(Regulator Power) VDD_IO1 VSS 47u 0.1u C3 VDD_DAC1 10u VSS_DAC1~2 AUDN AUDP VDDB VSSB (AMP. Power) 8Ω SPEAKER VDD_IO2 (Battery Power) 20p VSSB *C6 12MHz 20p*C7 VDD_DAC2 22u VSS_DAC3 VDDB VSSB (DAC Power) 10ΩR1 VDDB Note: 1. 4Ω speaker application is not allowed in GPCDXXXXA. 2. For system stability and performance, it is recommended to add R1~R9/C8 for the applications that IOs toggle with high current sinking, such as LEDs or motor drivers. 3. The value of R2~R9/C8 depends on the system application. 4. Basically, the more IO toggles, the larger C8 is suggested. 5. The values of C6/C7 are for design guidance only, different values may be needed for different crystal/resonator used. IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 IOC0~7 (by body) IOD0~7 (by body) IOC0~7 (by body) IOD0~7 (by body)
© Generalplus Technology Inc. Proprietary & Confidential 22 Feb. 08, 2017 Version: 1.5 10. PACKAGE 10.1. Ordering Information Product Number Package Type GPCD3040A-NnnV-C Chip form GPCD3080A-NnnV-C Chip form GPCD3130A-NnnV- QL02x Green Package – LQFP64 GPCD3130A-NnnV- QL01x Green Package – LQFP48 GPCD3170A-NnnV- QL02x Green Package – LQFP64 GPCD3170A-NnnV- QL01x Green Package – LQFP48 GPCD3270A-NnnV- QL02x Green Package – LQFP64 GPCD3340A-NnnV- QL02x Green Package – LQFP64 GPCD6040A-NnnV-C Chip form GPCD6080A-NnnV-C Chip form GPCD6130A-NnnV- QL02x Green Package – LQFP64 GPCD6130A-NnnV- QL01x Green Package – LQFP48 GPCD6220A-NnnV- QL02x Green Package – LQFP64 GPCD6300A-NnnV- QL02x Green Package – LQFP64 GPCD6170A-NnnV- QL02x Green Package – LQFP64 GPCD6170A-NnnV- QL01x Green Package – LQFP48 GPCD6270A-NnnV- QL02x Green Package – LQFP64 GPCD6340A-NnnV- QL02x Green Package – LQFP64 GPCD9040A-NnnV-C Chip form GPCD9080A-NnnV-C Chip form GPCD9130A-NnnV- QL02x Green Package – LQFP64 GPCD9130A-NnnV- QL01x Green Package – LQFP48 GPCD9220A-NnnV- QL02x Green Package – LQFP64 GPCD9300A-NnnV- QL02x Green Package – LQFP64 GPCD9170A-NnnV-QL02x Green Package – LQFP64 GPCD9170A-NnnV-QL01x Green Package – LQFP48 GPCD9270A-NnnV-QL02x Green Package – LQFP64 GPCD9340A-NnnV-QL02x Green Package – LQFP64 Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc. Proprietary & Confidential 23 Feb. 08, 2017 Version: 1.5 10.2. Package Information 10.2.1. LQFP 64 Outline Dimensions
© Generalplus Technology Inc. Proprietary & Confidential 24 Feb. 08, 2017 Version: 1.5 10.2.2. LQFP 48 Outline Dimensions
© Generalplus Technology Inc. Proprietary & Confidential 25 Feb. 08, 2017 Version: 1.5 11. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or rega rding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Appl ications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 26 Feb. 08, 2017 Version: 1.5 12. REVISION HISTORY Date Revision # Description Page Jan. 18, 2017 1.5 Add LQFP64 pin assignment 7,8,9 22,23,24 OCT. 07, 2013 1.4 Modify 9.1 Application circuit 13 JUL. 26, 2013 1.3 Add LVD description and content update NOV. 10, 2011 1.2 Application circuit modify 13-14 SEP. 13, 2011 1.1 1. Modify working voltage in “GPCDXXXXA Family and Feature list” 2. Remove IOA0 auto-wakeup function in “IO configuration” 3. Add “Reset Key De-bounce” 4. Update “The Relationship between ROSC and FOSC” 4,6,7,12,13 FEB. 14, 2011 1.0 Original 21