GPCE20XXB-NnnV-C | DigiCamel IC Datasheet

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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to o btain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPL US products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the exp ress written approval of Generalplus. DATA SHEET Apr. 13, 2015 Version 1.2 GGPPCCEE2200XXXXBB 16-bit Sound Controller

1 GENERAL DESCRIPTION

GPCE20XXB, a 16-bit architecture sound controller, features a 16-bit microprocessor, ’nSP™ (pronounced as micro-n-SP). This high processing spee d assures the ’nSP™ is capable of handling complex digital signal processes easily and rapidly. Therefore, the GPCE20XXB is applicable to the areas of digital sound process and voice recogniti on. The operating voltage of 2.4V through 5.5V and speed of 0 .16MHz through 49.152MHz yield the GPCE20xxB to be easily used in varieties of applications. The memory capacity includes an internal ROM plus a 2K -word working SRAM. Other features include 20 programmable multi-functional I/Os, three 16-bit timers/counters, 32KHz clock, Low Voltage Reset/Detection, four channels 12-bit ADC (one channel built-in MIC amplifier with auto gain controller), one 14-bit DAC with push-pull amplifier and many others.

2 FEATURES

 16-bit ’nSP™ microprocessor  CPU Clock: 0.16MHz - 49.152MHz  Operating Voltage: 2.4V - 5.5V  Power regulator built-in with input voltage: 2.4~5.5V, output voltage: 2.4~3.0V  IO PortA & B Operating Voltage: 2.4V - 5.5V  2K-word working SRAM  Software-based audio processing  Two sets of 14-bit software channel with noise filter, mixer and scalar to play high quality sound  Standby mode for power saving  Three 16-bit timers/counters  One 14-bit DAC with push-pull amplifier, supporting cascade mode  20 general I/Os (bit programmable)  Key wakeup function (IOA0 - 15)  PLL feature for system clock  32kHz internal resistor oscillator selected.  Four channels 12-bit AD converter  ADC  Built-in microphone amplifier and AGC or PGA function selected  Low voltage reset and low voltage detection  Watchdog Enable (option)  One SPI serial interface I/O  Available bodies and ROM size: Body ROM size GPCE2064B 32K Words GPCE2048B 24K Words

3 APPLICATION FIELD

 Voice Recognition Products  Intelligent Interactive Talking Toys  Advanced Educational Toys  Kids Learning Products  Kids Storybook  General Speech Synthesizer  Long Duration Audio Products  Recording / Playback Products

4 BLOCK DIAGRAM

un'SP 16-bits CPU AD Converter MIC 16-bits Counter/Timer / Interrupt General I/O Port 2K(word) Working SRAM PLL / System clock / Reset Function Memory Mapping & Control IOA[15:0] IOB[3:0] MICIP MICIN RESETB / GPIO Special Function TimeBase/WatchDog Stack Protect / / PWM output SPI MICO OPI AGC VMIC VADREF Push Pull DAC AUDP AUDN ACIN Words ROM

5 SIGNAL DESCRIPTIONS

5.1 Signal Pin:

5.1.1 All Pins and LQFP64 pin descriptions

PIN No. (LQFP64) Type Description PORT A, Port B IOA[15:0]: bi-directional I/O ports It can be programmed as wakeup I/O pins IOB [3:0] 18-15 I/O IOB [3:0]: bi-directional I/O ports Power & GND VDD_IOA 29 P Power VDD for Port A VSS_IO 28 G Power GND for IO Port VDD_IOB 19 P Power VDD for Port B V3_ADC 7 P Power VDD for AD VSS_ADC 6 G Power GND for AD V3_REGO 63 P 3V power output from regulator VDD_REG 62 P Positive supply for regulator(2.4V~5.5V) VSS_REG 64 G Ground reference for regulator VDD_DAC 54 P Positive 5V supply for push-pull DAC VDD_PDAC 50 P Positive 5V supply for push-pull DAC post driver VSS_DAC 53 I Ground reference for push-pull DAC VSS_ PDAC 48,52 I Ground reference for push-pull DAC post driver OPTION TEST 5 I TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low) TEST2 1 I TEST2 Mode selection pin, do not connect the pin TEST3 2 I TEST3 Mode selection pin, do not connect the pin DAC AUDP 49 O Audio output of push pull DAC AUDN 51 O Audio output of push pull DAC ACIN 55 U Audio analog mixer in ADC MICP 14 I MIC amplifier input positive (Internal Floating) MICN 13 I MIC amplifier input negative (refer to application circuit) MICOUT 12 O MIC amplifier output (refer to application circuit) OPI 11 I Audio amplifier negative input (refer to application circuit) AGC 10 IO AGC by pass filter (refer to application circuit) VMIC 8 O Microphone power supply VADREF 9 O AVREF_DA reference pin PLL VCOIN 3 I PLL low pass filter input Other Signal RESETB 4 I System reset pin (active low)

5.1.2 SOP24 (HS101) pin descriptions:

PIN No. (HS101) Type Description PORT A, Port B IOA[0] IOA[12] IOA[13] IOA[14] IOA[15] I/O IOA : bi-directional I/O ports It can be programmed as wakeup I/O pins IOB[2] IOB[3] I/O IOB : bi-directional I/O ports Under OTP ROM programming mode, IOB2SCK, IOB3SDA. Power & GND VDD_IOA 19 P Power VDD for Port A VDD_IOB 13 P Power VDD for Port B V3_ADC 9 P Power VDD for AD VSS_ADC 8 G Power GND for AD V3_REGO 1 P 3V power output from regulator VDD_REG 24 P Positive supply for regulator(2.4V~5.5V) VSS_REG 2 G Ground reference for regulator VDD_PDAC 22 P Positive 5V supply for push-pull DAC post driver VSS_ PDAC 20 I Ground reference for push-pull DAC post driver OPTION TEST 7 I TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low) TEST2 3 I TEST2 Mode selection pin, do not connect the pin TEST3 4 I TEST3 Mode selection pin, do not connect the pin DAC AUDP 21 O Audio output of push pull DAC AUDN 23 O Audio output of push pull DAC ADC VADREF 10 O AVREF_DA reference pin PLL VCOIN 5 I PLL low pass filter input Other Signal RESETB 6 I System reset pin (active low)

5.1.3 SOP24 (HS102) pin descriptions:

PIN No. (HS102) Type Description PORT A, Port B IOA[0] IOA[1] IOA[12] IOA[14] IOA[15] IOA[13] IOA[8] IOA[7] IOA[6] IOA[3] I/O IOA : bi-directional I/O ports It can be programmed as wakeup I/O pins IOB[0] IOB[1] IOB[2] IOB[3] I/O IOB : bi-directional I/O ports Under OTP ROM programming mode, IOB2SCK, IOB3SDA. Power & GND VDD_IOA 21 P Power VDD for Port A VDD_IOB 13 P Power VDD for Port B V3_REGO 3 P 3V power output from regulator VDD_REG 4 P Positive supply for regulator(2.4V~5.5V) VSS_REG 5 G Ground reference for regulator OPTION TEST 8 I TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low) TEST2 2 I TEST2 Mode selection pin, do not connect the pin TEST3 1 I TEST3 Mode selection pin, do not connect the pin PLL VCOIN 6 I PLL low pass filter input Other Signal RESETB 7 I System reset pin (active low)

5.2 PIN Map

5.2.1 LQFP64 (QL021):

GPCE20XXB (QL021)

5.2.2 SOP24 (HS101):

GPCE20XXB (HS101)

5.2.3 SOP24 (HS102):

GPCE20XXB (HS102)

6 FUNCTION DESCRIPTIONS

6.1 CPU

The GPCE20XXB is equipped with a 16-bit ’nSP™ (pronounced as micro-n-SP) microprocessor. E ight registers are involved in ’nSP™: R1 - R4 (General -purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) and SR (Segment Register). The interrupts include three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt Request), plus one software-interrupt, BREAK.

6.2 Memory

6.2.1 SRAM

The amount of SRAM is 2K -word (including Stack), ranged from $0000 through $07FF with access speed of two CPU clock cycles.

6.2.2 ROM

GPCE20XXB features an internal high-speed memory. The ROM size is depicted in following table: Body ROM size GPCE2064B 32K Words GPCE2048B 24K Words

6.3 PLL, Clock, Power Mode

6.3.1 PLL (Phase Lock Loop)

The purpose of PLL is to provide a base frequency (32 kHz) and to pump the frequency from 20.48MHz to 49.152MHz for system clock (FOSC). The default PLL frequency is 24.576MHz.

6.3.1.1 System clock

Basically, the system clock is provide d by PLL and programmed by the Port_SystemClock (R/W) to determine the clock frequency for system. The default system clock F OSC = 24.576MHz and CPU clock is FOSC/8 if not specified. The initial CPU clock is Fosc/8 after system wak es up and adjusts to desired CPU clock via programming the Port_SystemClock ( R/W). This avoids ROM reading failure when system wakes up. 6.3.1.2 32KHz clock The 32KHz clock is normally used in watch, clock or other time related products. A 2Hz ( 0.5 seconds) function is loaded in GPCE20XXB. It counts the tim e as well as to wake CPU up whenever 2Hz occurs. Since the clock is generated each 0.5 seconds, time can be traced by the num ber of 32KHz occurrences. In addition, GPCE20XXB supports 32KHz internal resistor oscillator in normal mode and auto-power-saving mode.

6.4 Standby Mode

The GPCE20XXB features a power savings mode (or called standby mode ) for low power applications. To ent er standby mode, the demanded key wakeup port (IOA[15:0]) must be configured to input first. And read the P ort_IOA_Data to latch the IOA state before entering the standby mode. Also remember to enable the corresponding interrupt source(s) for wakeup. After that, stop the CPU clock by writing $5555 into Port_System_Sleep(W) to enter standby mode. In such mode, SRAM and I/Os retain in their previous states until CPU being awakened. The wakeup sources in GPCE20XXB include KEY wakeup ( IOA[15:0]), 32KHz wakeup, FIQ and IRQ0 - IRQ7. After GPCE20XXB is aw akened, CPU will continue to execute the program from where it slept. Programmer can also enable or disable the 32kHz when CPU is in standby mode.

6.5 Low Voltage Detection and Low Voltage Reset

6.5.1 Low voltage detection (LVD)

The Low Voltage Detect ion (LVD) reports the circumstance of present voltage. There are four LVD levels to be selected: 2.6V, 2.8V, 3.0V and 3.2V. Those levels can be programmed via P_LVD_Ctrl. As an example, suppose LVD i s given 2.8V. When the voltage drops below 2.8V, the b1 2 of P_LVD_Ctrl is read as HIGH. In such state, program can be designed to react this condition.

6.5.2 Low voltage reset

In addition to the LVD, the GPCE20XXB has another important function, Low Voltage Reset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below LVR level. Without LVR, the CPU becomes unstable and malfunctions when the operating voltage drops below LVR level. T he LVR will rese t all functions to the initial operational (stable) states when the voltage drops below LVR level.

6.6 Interrupt

The GPCE20XXB has 13 interrupt sources, grouped into two types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The pr iority of FIQ is higher than IRQ. FIQ is a high -priority interrupt while IRQ is the low -priority one. An IRQ can be interrupted by a FIQ, but not by another IRQ. A FIQ cannot be interrupted by any other interrupt sources.

6.7 I/O

Two I/O ports are built in GPCE20XXB - PortA and PortB, total of 20 bit-programmable I/Os. The PortA is a general purpose I/O with programmable wakeup capability , i.e. IOA [15:0] is the key wakeup port. To activate key wakeup function, latch data on Port_IOA_Data and enable the key wakeup function. Wakeup is triggered when the PortA state is different from at the time latched. Furthermore, the I/O ports can be operated at 5V level, higher than the CPU core which is a 3V level system. Suppose system o perating voltage is running at 3.3V, VDDIO (power for I/O) operates from 3.3V to 5.5V. In such condition, the I/O pad is capable of operating from 0V through VDDIO. The following diagram is a n I/O schematic. Although data can be written into the same register through Port_Data and Port_Buffer , they can be read from different places, Buffer (R) and Data (R). Register Control logic pull high pull low Pin pad Buffer(R) Data(R) Port_Data(W) Port_Buffer(W) Port_DIR(R/W) Port_ATTR(R/W) In addition to a general purpose I/O port function, PortA/B also shares/carries some special functions.

6.8 Timer / Counter

GPCE20XXB provides t hree 16-bit timers/coun ters - TimerA, TimerB and TimerC or so called universal counter s. The clock source of Timer A/B/C are from clock source Input 1 and clock source Input 2 (see below table) which perform AND operation to form the varieties of combinations. When timer overf lows, a timeout signal (TAOUT) is sent to CPU interrupt module to generate a timer interrupt signal. In addition, Timer A/B/C hardware interrupt events can be used to latch the DAC audio output and trigger ADC conversion.

6.9 IO PWM

One IO PWMs which duty is selected from 1/ 256 to 254/256. Example the below figure is a 3/256-duration cycle. The PWMO waveform is made by sel ecting a pulse width through Port_PWM_Ctrl. As a result, each 256 cycles will generate a pulse width defined in control port. These PWM signals can be applied for controlling the speed of motor or other devices. Tpwmo Tduty PWMO TimerA_Timeout ... ... ... 1 2 3 4 5 6 7 8 9 1 2 3 4 5251 252 253 254 255 256

6.10 Timebase

Timebase, generated by 32KHz crystal oscillator, is a combination of frequency selection. Furthermore, timebase generates 4KHz, 2KHz, 5 12Hz, 64Hz, 16Hz and 2Hz interrupt sources for Real-Time-Clock

6.11 Sleep Mode, Wakeup, and Watchdog

6.11.1 Sleep and wakeup modes

1) Sleep: After power -on reset, IC starts running until a sleep command is issued . When a sleep command is accepted, IC will turn the sys tem clock (PLL) off. After all, it enters sleep mode. 2) Wakeup: CPU awaking from sleep mode requires a wakeup signal to turn the system clock (PLL) on. The FIQ/IRQ signal makes CPU to complete the wakeup process and initialization.

6.11.2 Watchdog Reset

The GPCE20XXB provides another important feature, watchdog reset. If the watchdog function is enabled , a reset signal is generated to reset system when watchdog counter is overflow. The purpose of watchdog is to monitor whether the system operates normally. W ithin a certain period, watchdog register must be cleared. If it is not cleared, CPU assumes the program has been running in an abnormal condition. As a result, the CPU will reset the system to the initial state and start running the program all over again.

6.12 Soft Reset Protection

Software reset . Writes $5555 into P_System_Reset will reset the whole system like hardware reset (pull low RESETB pin), except a flag will set on in P_System_LVD_Ctrl(R/W).

6.13 ADC (Analog to Digital Converter) / DAC

The GPCE20XXB has eight channels 12-bit AD C (Analog to Digital Converter). The function of an ADC is to convert analog signal to digital signal, e.g. a voltage level into a digital word . The four channels of ADC can be four channels of line -in from IOB [ 3:0] or one ch annel microphone (MIC) input through amplifier PGA controller, and AGC controller. The MIC amplifier circuit is capable of reducing common mode noise by transmitting signals through differential MIC Inputs (MICN, MICP). Moreover, an external resistor can be applied to adjust microphone gain and time of AGC operating. The AD needs to select source of line-in before conversion. The ADC take pad (VDD_ADC) as voltage reference.

6.14 SPI

A Serial Peripheral Interface (SPI) controller is built in GPCE20XXB to facilitate communicating with other devices and components. There are four control signals on SPI - SPICS (IOA12), SPICK (IOA13), SDO (IOA14), and SDI (IOA15).

6.15 Audio Algorithm

The following speech types can be used in GPCE20XXB: PCM, SACM_S200, SACM_S480, SA CM_S530, SACM_A1600, SACM_A1601, SACM_A1800, SACM_A3400pro, SACM_A3600, SACM_DVR520, SACM_DVR1600, SACM_DVR1800, SACM_DVR3200, and SACM_DVR4800. For melody synthesis, the GPCE20XXB supports SACM_MS01 (FM) and SACM_MS02 (wave-table) synthesizers.

7 ELECTRICAL SPECIFICATIONS

7.1 Absolute Maximum Ratings

Characteristics Symbol Ratings DC Supply Voltage V+ < 4.0V PortA/B Pad Supply Voltage VIO < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions see DC Electrical Characteristics. 7.2 DC Characteristics (V3_REGO = 3.0V, VDDIO = 4.5V (PortA & B), TA = 25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD_REG 2.4 - 5.5 V - Operating Current IOP - 13 - mA FOSC = 49.152MHz, AD, DAC disable, no load Standby Current ISTB - - 5 A Disable 32KHz, Disable PLL(FOSC) 10 A Enable 32KHz,Disable PLL(FOSC) Input High Level VIH 0.7VDDIO - - V - Input Low Level VIL - - 0.3VDDIO V - Output High Current IOH - -20 - mA VOH = 0.7VDDIO Output Low Current (PA[3:0], PB[3:0]) IOL - 20 - mA VOL = 0.3VDDIO Output Low Current (PA[7:4]) IOL - 40 - mA VOL = 0.3VDDIO Input Pull-Low Resister (PA15:0) RPL - 120 - K VIN = VDDIO Input Pull-Low Resister (PB[3:0]) RPL - 1200 - K VIN = VDDIO Input Pull-High Resister (PA15:0) RPH - 110 - K VIN = VSS Internal ROSC f requency deviation ⊿F/F -3% 32768 +3% HZ V3_REGO = 3.0V 7.3 DC Characteristics (V3_REGO = 3.0V, VDDIO = 3.3V (PortA & B), TA = 25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD_REG 2.4 - 5.5 V - Operating Current IOP - 13 - mA FOSC = 49.152MHz, AD, DAC disable, no load Standby Current ISTB - - 3 A Disable 32KHz, Disable PLL(FOSC) 6 A Enable 32KHz,Disable PLL(FOSC) Input High Level VIH 0.7VDDIO - - V - Input Low Level VIL - - 0.3VDDIO V - Output High Current IOH - -11 - mA VOH = 0.7VDDIO

© Generalplus Technology Inc. Proprietary & Confidential 15 Apr. 13, 2015 Version: 1.2 Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Output Low Current (PA[3:0], PB[3:0]) IOL - 11 - mA VOL = 0.3VDDIO Output Low Current (PA[7:4]) IOL - 25 - mA VOL = 0.3VDDIO Input Pull-Low Resister (PA15:0) RPL - 120 - K VIN = VDDIO Input Pull-Low Resister (PB[3:0]) RPL - 1200 - K VIN = VDDIO Input Pull-High Resister (PA15:0, PB3:0) RPH - 110 - K VIN = VSS Internal ROSC f requency deviation ⊿F/F -3% 32768 +3% HZ V3_REGO = 3.0V 7.4 DAC Characteristics (VDD_DAC = 5.0V, TA = 25℃) Characteristics Symbol Limit Unit Min. Typ. Max. DAC Resolution RESO - - 14 bit Noise at No Signal - - -97 - dBr A Dynamic Range(-60dB) - - -82 - dBr A

7.5 Regulator Characteristics (TA = 25℃)

Min. Typ. Max. Input Voltage VDD_REG 2.4 - 5.5 V Maximum Current Output IREGO - - 40 mA VDD_REG (Regulator in )= 4.5V,VDD (Regulator out) <100mV Standby Current IRGES - 2.5 - uA

7.6 Pull High Resister and VDDIO

VDD(V) RPH (KΩ)

7.7 Pull Low Resister and VDDIO (Normal PAD)

110.6 110.7 110.8 110.9 111.0 111.1 111.2 111.3 111.4 111.5 2 3 4 5 6 VDD(V) RPL (KΩ)

7.8 Pull Low Resister and VDDIO (IOB[3:0] PAD with

input high) 1102.00 1102.05 1102.10 1102.15 1102.20 1102.25 1102.30 1102.35 2 3 4 5 6 VDD(V) RPL (KΩ)

7.9 I/O Output High Current IOH and VDDIO

Test Condition: VOH = 0.7 * VDDIO 2 3 4 5 6 VDD(V) IOH (mA)

7.10 I/O Output Low Current IOL and VDDIO (Normal

Pad) Test Condition: VOL = 0.3 * VDDIO (Normal PAD) -30 -25 -20 -15 -10 2 3 4 5 6 VDD(V) IOL (mA)

7.11 I/O Output Low Current IOL and VDDIO (High

driving pad) Test Condition: VOL = 0.3 * VDDIO (High Driving PAD) -70 -60 -50 -40 -30 -20 -10 2 3 4 5 6 VDD(V) IOL (mA)

7.12 Internal ROSC and V3_REGO

97.50% 98.00% 98.50% 99.00% 99.50% 100.00% 100.50% V33_REG(V) IROSC(%) (ref to 32768Hz) V3_REGO(V)

8 APPLICATION CIRCUITS

8.1 Application Circuit with MIC_IN Selected

IOA[15:0] IOA[15:0] IOB[3:0] 0.1uF VMIC MICP MICN AGC 0.1uF VADREF OPI MICOUT VCOIN 3.3K 3300pF 0.1uF 10uF 470K 0.22uF 0.22uF MIC 4.7uF 5.1K 0.22uF 5000pF RESETB AUDN AUDP 8Ω SPEAKER 0.1uF10uF VDD_REG VSS_REG VSS_DAC (2.4v~5.5v) Battery 0.1uF10uF V3_REGO2.4V~3.0V 0.1uF10uF V3_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IO VDD_PDAC VDD_DAC VSS_PDAC IOB[3:0] Note: V3_REGO is output of built-in regulator with maximum current 40mA. It is recommended that only use it for internal power pad. GPCE20XXB

8.2 Application Circuit with LINE-IN Selected

IOA[15:0] IOA[15:0] IOB[3:0] 0.1uF VMIC MICP MICN AGC 0.1uF VADREF OPI MICOUT VCOIN 3.3K 3300pF 0.1uF RESETB AUDN AUDP 8Ω SPEAKER 0.1uF10uF VDD_REG VSS_REG VSS_DAC (2.4v~5.5v) Battery 0.1uF10uF V3_REGO2.4V~3.0V 0.1uF10uF V3_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IO VDD_PDAC VDD_DAC VSS_PDAC IOB[3:0] (4 channel Line-In) Note: V3_REGO is output of built-in regulator with maximum current 40mA. It is recommended that only use it for internal power pad. GPCE20XXB

9 PACKAGE/PAD LOCATIONS

9.1 Ordering Information

Product Number Package Type GPCE20XXB-NnnV-C Chip form GPCE20XXB-NnnV-QL02x Halogen Free Package – LQFP64 GPCE20XXB-NnnV-HS10x Halogen Free Package – SOP24 Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number).

9.2 LQFP64 Package Information

Min. Typ. Max. A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c1 0.09 - 0.16 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF S 0.20 REF θ 3.5° REF θ1 5.0° REF θ2 12° REF θ3 12° REF R1 0.16 REF R2 0.15 REF

9.3 SOP24 Package Information

Min. Typ. Max. A 0.093 0.099 0.104 A1 0.004 -- 0.012 D 0.599 0.600 0.614 E 0.291 0.295 0.299 H 0.394 0.406 0.419 L 0.016 0.035 0.050 θ° 0 -- 8

10 DISCLAIMER

The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulat ed in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in thi s publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercia l applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical l ife support equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.

11 REVISION HISTORY

Date Revision # Description Page Dec. 25, 2013 1.1 2. Correct the value of V3_REGO at P3,P10,P11,P14 and P15 Sep. 25, 2013 1.0 Original 19

Product Information

GPCE20XXB-NnnV-C specifications and overview.

Summary

16-bit Sound Controller

Description

16-bit Sound Controller

Source title GPCE20XXB-NnnV-C Datasheet(PDF) - Generalplus Technology Inc.

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