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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPLLBB3399BB LCD CONTROLLER JAN. 07, 2008 Version 1.5 In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 JAN. 07, 2008 Version: 1.5 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 JAN. 07, 2008 Version: 1.5 LCD CONTROLLER 1. GENERAL DESCRIPTION The GPLB39B, an 8-bit CMOS mi croprocessor, contains 8128 bytes working RAM, 2M bytes ROM, 21 I/Os, interrupt/wakeup controller, UART for serial comm unication, Serial SRAM interface and Bus memory interface for memory expansion, and automatic display controller/driver for LCD. It also features one PWM driver with two audio channels to produce attractive sound effects easily. Its large ROM area can be used to store both program and audio data. The built-in UART and SPI speeds up data transmission between two devices. Furthermore, a SLEEP (power-down) function is also built in to ex tend power life. The GPLB39B is designed with state-of-the-art technology to fulfill LCD application needs, especially for hand-held products. 2. FEATURES Built-in 8-bit processor − 8128 bytes SRAM with individual Power Pad − 2M bytes ROM − Max. operating speed: 4.0MHz @ 2.4V - 3.6V 6.0MHz @ 3.6V - 5.5V − CPU clock is software programmable, can be /1, /2, /4, /8, /16, /32, /64 R-oscillator clock frequency − 6 wake-up sources − 7 interrupt sources Asynchronous serial interface (UART) Serial SRAM interface Bus memory interface Serial peripheral interface (SPI) Built-in voltage regulator for external memory devices Key scan function − SEG[15:0] can be used to send key scan output Programmable LCD driver − 112x8, 112x16, 112x32, 112x48, 96x64 dots duty capability − 14x64 bytes dedicated LCD RAM − Built-in voltage regulator to generate VLCD for LCD driver − 32-level contrast control Power saving SLEEP mode Low voltage detector − 8-level 2.9V ~ 2.2V/4.35V ~ 3.3V detection − 2.2V Low voltage reset Wide operating voltage range: − 2.4V - 3.6V − 3.6V - 5.5V Peripherals − Max. 21 I/O pins (PA[7:0], PB[7:0], PC[4:0]) . Dedicated I/Os: PA[4:0] . Shared pin I/Os: PA[7:5]/SPI SCK/SDI/SDO PB[7:0]/BMI AD Bus [7:0] PC[1:0]/BMI MC[1:0]/SSRAM SDA, SCK PC[3:2]/UART Rx/Tx PC[4]/external interrupt COM[48:63]/SEG[96:111] − 32.768KHz oscillator circuit for RTC − RC-oscillator (only one resistor is needed) − Two 16-bit reloadable timer/counters − 2-channel PWM audio outputs − Watchdog Timer for reliable operation Low-power consumption: − 1000μA typical @ 3.0V, FCPU = 1.0MHz, FOSC = 4.0MHz − 80μA typical halt current @ 3.0V − <1.0μA typical standby current @ 3.0V 3. APPICATION FIELD Hand held games Scientific calculator Talking calculator, Talking clock Talking instrument controller General speech synthesizer Data Bank
© Generalplus Technology Inc. Proprietary & Confidential 4 JAN. 07, 2008 Version: 1.5 4. BLOCK DIAGRAM RC-Oscillator System Clock Gen. Power Supply Voltage Detect 1M bytes ROM 2560 bytes RAM Two 16-bit / Auto-reload Timers
32 KHz
Max.20 I/O Ports
64 Commons X 112 Segments LCD Driver
(I/O) COM[47:0] SEG[111:0] LCD RAM 896 bytes ROSC32 AUDB Serial SRAM I/F SDA/PC1 SCK/PC0 BUS Mem I/F MC[1:0]/PC[1:0] AD[7:0]/PB[7:0] PA[7:0] PB[7:0] PC[4:0] Voltage Regulator VROUT SPI SDO/PA5 SCK/PA7 SDI/PA6 Note1: COM[48:63] share pins with SEG[96:111]. Note2: PB[7:0] share pins with Bus memory interface Addr/Data bus. Note3: PC[1:0] share pins with Bus memory interface MC[1:0]. Also share pins with Serial SRAM interface SDA/SCK. Note4: PC[3:2] share pins with UART Rx/Tx. Note5: PA[7:5] share pins with SPI SCK/SDI/SDO.
© Generalplus Technology Inc. Proprietary & Confidential 5 JAN. 07, 2008 Version: 1.5 5. SIGNAL DESCRIPTIONS Total: 214 pins Mnemonic PIN No. Type Description SEG95 - 0 199 - 213 2 - 82 O LCD driver segment output. SEG15 - 0 share pin with key scan port. COM48 - 63 / SEG 96 - 111 198 - 183 O LCD driver common output. SEG96 - 111 can be optioned to COM48 - 64. COM19 - 0 COM23 - 20 COM47 - 24 103 - 84 107 - 104 182 - 159 O LCD driver common output. COM47 - 0. PA4 - 0 142 - 146 I/O Port A 4- 0 is a bi-directional I/O port, which can be software programmed as wake up I/O. PA7 - 5 139 - 141 I/O Port A 7- 5 is a bi-directional I/O port, which can be software programmed as wake up I/O. Share pin with SPI SCK/SDI/SDO. PB7 - 0 136 - 129 I/O Port B is a bi-directional I/O port. Share pin with Bus Memory Interface Addr/Data. PC1 / MC1 / SDA PC0 / MC0 / SCK 128 127 I/O Port C is a bi-directional I/O port. Share pin with Bus Memory MC1 - 0. Also share pin with SDA/SCK. PC3 / Rx 148 I/O UART input. Share pin with PC3. PC2 / Tx 147 I/O UART output. Share pin with PC2. PC4 149 I/O Port C 4 is a bi-directional I/O port. It can be used as an external interrupt. ROSC 124 I ROSC input, connect to VDD through a resistor. RESET 123 I System reset input, low active. AUDA, AUDB 152, 150 O PWM audio output. X32I 122 I 32.768KHz crystal input or connects to VDD through a resistor (option). X32O 120 O 32.768KHz crystal output. TESTP 121 I Test input. CAP1P, CAP1N 117, 116 P LCD voltage generation. Charge pump capacitor interconnection pins. CAP2P, CAP2N 114, 115 P LCD voltage generation. Charge pump capacitor interconnection pins. VPP 113 P LCD voltage generation. Voltage generated by charge pump. VCI 118 P LCD voltage generation. The source of Charge pump. VLCD 112 P LCD voltage generation. The highest Voltage for LCD display. VROUT 126 P Internal regulator output. Enable or disable via masking option. Should be connected to VDD if internal Regulator is disabled. VDD 138 P Positive supply for logic and IO pins. VDD 125 P Analog power pin. VDD1 83 P Positive supply for SRAM only. VDD2 214 P Positive supply for Segment / Common Pads only. VSSx2 137, 119 P Ground reference for logic and IO pins. VSS2 1 P Ground reference for Segment / Common Pads only. PVDD 151 P Positive supply for PWM driver. PVSS 153 P Ground reference for PWM driver. V1, V2, V3, V4 108 - 111 O LCD Bias voltage output. TPAD1-TPAD5 154 - 158 I Test Pads. Legend: I = Input, O = Output, P = Power
© Generalplus Technology Inc. Proprietary & Confidential 6 JAN. 07, 2008 Version: 1.5 5.1. PAD Assignment The IC substrate should be connected to VSS Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible. Note3: The power and ground pads should be double wire bonded to reduce ground bouncing.
© Generalplus Technology Inc. Proprietary & Confidential 7 JAN. 07, 2008 Version: 1.5 6. FUNCTIONAL DESCRIPTIONS 6.1. Memories The GPLB39B contains 2M-byte ROM and 8128-byte SRAM. Cooperating with Generalplus bus extender, GPBA01B, the external memory, either RAM or ROM, can be extended up to 4MB. Serial SRAM interface is also provided in GPLB39B, thus SRAM space can be extended by using Generalplus Serial SRAM, GPRS256B or GPRS512C. 6.2. Map of Memory and I/Os *NMI SOURCE: - L V D E T E C T - T I M E R 1 *INT SOURCE: - E X T I N T - TBL (2/4/8/16Hz) - TBH (128/256/512/1KHz) - T I M E R 0 - T I M E R 1 - U A R T T X - U A R T R X ROM (Bank)H I/O & $0000-$003F $3C00-$3FFF $4000-$7FFF $8000-$BFFF $C000-$FFF9 $FFFA-$FFFF CPU View ROM View 63H Bank Address: $0 $C000-$FFFF always mapping into 0L . . . Reg. $0040-$1FFF ROM (Bank)L Interrupt ROM DPRAM RAM $1F8000 - $1FBFFF $000000 - $003FFF $004000 - $007FFF $008000 - $00BFFF $00C000 - $00FFFF $010000 - $013FFF $014000 - $017FFF 63L $1FF000 - $1FFFFF 1. $4000-$BFFF can be external memory if MEXT ($03.7) = 1 and Bank port ($00.7) = 1. 2. $C000-$FFFF can be external memory if MEXT ($03.7) = 1 and EXC($0b.1) = 1. 3. User program should start from $C800. $C000-$C7FF is the test program area. 4. User program interrupt vector: $FFFA ~ $FFFF 5. Test program interrupt vector: $FFF2 ~ $FFF7 6.3. Operating States There are three operation modes involved in GPLB39B: standby, halt and operating. The following table shows the differences between these modes. Operating Halt Standby CPU ON OFF OFF 32768Hz oscillator ON ON OFF LCD driver ON ON/OFF OFF 6.3.1. Operating mode In operating state, all functions (CPU, 32768Hz oscillator, timer/counter, LCD driver…) are ac tivated. Generally speaking, this mode consumes the highest current. 6.3.2. Standby mode Write “07H” to P_04H_CPU_Clk_Ctrl Register ($04) and turn off 32768Hz oscillator to activate standby mode. The standby mode is a mode where the device is placed in its lowest current consumption state. In standby mode, all functions are turned off; in addition, RAM and I/Os will remain in their previous states. 6.3.3. Halt mode Write “07H” to P_04H_CPU_Clk_Ctrl Register ($04) but still keeps 32768Hz oscillator running to enter halt mode. In halt mode, CPU clock halts and waits for an event (e.g. key press, timer overflow) to wake up. The 32768Hz related functions, such as timer/counter and LCD driver, may remain active in the halt mode.
© Generalplus Technology Inc. Proprietary & Confidential 8 JAN. 07, 2008 Version: 1.5 The following figure is the GPLB39B state diagram: GPLB39B State Diagram 6.4. Speech and Melody For speech synthesis, the GPLB 39B provides several timer interrupts for a precise sampling frequency. The sound data can be stored into ROM and be played back. Several algorithms are recommended for high fidelity and good compression of sound such as PCM and ADPCM. For melody synthesis, the GPLB39B provides a dual tone mode. Once in the dual tone mode, users only need to program the tone frequency for each channel by writing to the timer/counter TM0 and TM1, and set the envelope of each channel. The hardware will toggle the tone wave automatically. 6.5. LCD Controller/Driver The GPLB39B contains a 6144-dot LCD controller/driver. Programmers are able to define t he LCD configuration by setting up the LCD Control Register. Once the LCD configuration is completed, the desired pattern can be displayed by filling the LCD buffer with proper data. The LCD driver can also operate during sleep by keeping 32768Hz oscillator running. The LCD driver in GPLB39B supports 1/8 - 1/64 duty and 1/4 - 1/9 bias. 6.6. LCD Voltage Generation The GPLB39B offers a voltage regulator and a charge-pumping circuit. The charge-pumping circ uit provides VPP as the power source for voltage regulator. The voltage regulator generates the LCD bias voltages (VLCD, V1~V4) needed for the LCD driver. VPP and VLCD can be adjusted by program settings. Enabling the voltage regulator and charge-pumping circuit gets a stable VLCD that will not be affected by VDD. The VLCD is adjustable from 4.4V to 5.7V (in 1/4, 1/5bias), 5.28V to 6.83V (in 1/6, 1/7 bias), or 6.2V to 8.06V (in 1/8, 1/9 bias) with 32 levels. Users should be noted that VPP and VLCD voltage difference should be larger than 0.5V (VPP-VLCD>0.5V) to optimize voltage regulator performance. Also, VDD should be higher than VPP/3 to keep VPP stable. HALT OPERATING STANDBY Write $07h to CPU_Clk_Ctrl register, 32768 oscillator OFF Wake-up or user reset Write $07h to CPU_Clk_Ctrl register, 32768 oscillator ON Wake-up or user reset 6.7. PWM Output Internally, the GPLB39B has a pa ir of PWM drivers, supporting two sound channels. Each channel is able to play speech or tone individually. The PWM drivers can directly drive speaker or buzzer without buffer or amplification circuit. 6.8. Serial SRAM Interface The Serial SRAM interface is able to expand the data storage SRAM. The Control Registers are ranged from $30-$36. Note that the pins of SDA and SCK are shared with PC [1:0] and therefore, users should set PC[1:0] as Serial SRAM interface by writing to Port $27[1:0]. SDA SCK change of data allowed data line stable; data valid START condition (S) SDA SCK STOP condition (P) 6.8.1. Read/Write timing R/WA23 D7A0 D6 D5 D4 D3 D2 D1 D0SDA SCK stopstart 6.8.2. Continuous Read/Write timing R/WA23 D7A0 D6 D0 D7 D0 D7 D0 D0D7SDA SCK addr stopstart addr+1 addr+n
© Generalplus Technology Inc. Proprietary & Confidential 9 JAN. 07, 2008 Version: 1.5 6.9. Bus Memory Interface A built-in Bus memory interface is available on GPLB39B. Through the use of Bus memory interface, user can expand the memory space by using an external Bus memory (SRAM, mask ROM or Flash). The Bus memory interface includes 10 signal pins: MC1, MC0 and AD BUS[7:0] which shared pad with port B. Before using the Bus memory interface, users should set MEXT=1 ($03.7) and BANK register ($0), then access address $4000-BFFF to read or write data from external bus memory. Note that when using Bus memory interface, CPU clock setting can not be set as F OSC/1, should be /2 or slower. MC1 MC0 AD BUS [7:0] L L Data for Write L H Data for Read H L AL (Address Low byte) H H AH (Address High byte) 6.10. Voltage Regulator The GPLB39B offers a voltage regulator, which supplies power source for external memory devices. The voltage regulator can The output voltage level should be properly selected based on the electrical characteristics of external memory devices involved. 6.11. Asynchronous Serial Interface The GPLB39B supports a 1- channel UART for serial communications. The bit-rate is up to 115.2kbps. UART operation is controlled by UART command registers. Configurations such as Tx/Rx interrupt, parity check, parity even/odd and clock source can be configured in the command registers. Two interrupts are generated by Rx and Tx. The Rx or Tx interrupt activates when a byte is received or transmitted. Reading the status register informs whether the interrupt is generated by Rx or Tx. Frame, overrun and parity errors are detected as each byte is receiv ed and all error status can be read from status register. The UART supports clock auto calibration. If auto calibration is selected, standard baud rate from 1.2kbps to 115.2kbps are available. The baud rate is selected by writing to the baud rate control registers. The supported baud rates and their minimum R-oscillator clock frequency requirements are shown in the table below. Baud Rate(bps) Min. Frosc(Hz) 1200 24000 2400 48000 4800 96000 9600 192000 19200 384000 38400 768000 51200 1024000 57600 1152000 102400 2048000 115200 2304000 If the auto calibration is not selected, users can get desired baud rates by writing appropriate values to pre-scalar registers. Non-standard baud rates can be obtained by this method. In the non-calibration mode, users should understand that the R-oscillator frequency may alter due to manufacturing process variations, supply voltage, operating temperature and tolerance of external R components used. 6.12. Low Voltage Detection The GPLB39B provides an 8-level (Software programmable) low voltage detector to detect low voltage events. Users can turn on the low detection to monitor VDD periodically to check if it is lower than the given value. In addition, if LV NMI is enabled, a NMI will be issued to notify CPU if power voltage drops below the given value. Also, the voltage detector will generate a system reset if power supply voltage drops below 2.2V. When LVR function is enabled, care must be taken not to turn off 32kHz crystal oscillator. Otherwise an unexpected reset may occur when 32kHz crystal is being turned on again. 6.13. Watchdog Timer (WDT) An on chip watchdog timer is also available in the GPLB39B. The WDT is designed to recover the system from abnormal operation. In some cases, if WDT is not cleared within one second, the WDT will generate a system reset to restart system. If WDT is enabled, the WDT should be cleared periodically to avoid accidental reset. The WDT can be cleared through software programming. Note that the WDT only works when 32768Hz clock is activated. 6.14. Serial Peripheral Interface (SPI) GPLB39B provide a serial interface to communicate with SPCP825A USB controller. These pins are share with PA7(SCK), PA6(SDI) and PA5(SDO) pins. PA 7~5 were set as SCK, SDI and SDO automatically when SPI was enabled.
© Generalplus Technology Inc. Proprietary & Confidential 10 JAN. 07, 2008 Version: 1.5 6.15. Mask Options 6.15.1. 32768 oscillator 1). X’TAL 2). R-oscillator 6.15.2. Watchdog timer 1). Enable 2). Disable 6.15.3. Voltage regulator for external memory devices 1). Enable 2). Disable 6.15.4. Regulator output voltage selection 1). 2.5V 2). 2.6V 3). 2.7V 4). 3.0V
© Generalplus Technology Inc. Proprietary & Confidential 11 JAN. 07, 2008 Version: 1.5 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to + 60 ℃ Storage Temperature TSTO -50℃ to + 150 ℃ Note: Stresses beyond those given in the Absolute Maximum Rating ta ble may cause operational errors or damage to the device. For no rmal operational conditions see AC/DC Electrical Characteristics. 7.2. DC Characteristics Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition 2.4 - 3.6 V For 2-battery Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 1000 - μA FCPU = 1.0MHz @ 3.0V FROSC = 4.0MHz, no load Halt Current IHALT - 80 - μA VDD = 3.0V, 32K X’tal ON, LCD ON, no LCD panel Standby Current ISTBY - - 1.0 μA VDD = 3.0V, all off - -20 - mA VDD = 3.0V, VOH = 2.5V Audio Output Current IOH - -40 - mA VDD = 3.0V, VOH = 2.0V - 20 - mA VDD = 3.0V, VOL = 0.5V Audio Output Current IOL - 40 - mA VDD = 3.0V, VOL = 1.0V Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output High Current (I/O) IOH -1.0 - - mA VDD = 3.0V, VOH = 2.4V Output Sink Current (I/O) IOL 1.0 - - mA VDD = 3.0V, VOL = 0.8V 4.4 - 5.70 V VDD = 3.0V, 1/4,1/5 bias, no load 5.28 - 6.83 V VDD = 3.0V, 1/6,1/7 bias, no load LCD Driver Voltage (VLCD - VSS) VLCD 6.20 - 8.06 V VDD = 3.0V, 1/8,1/9 bias, no load - 2.5 - - 2.6 - - 2.7 - Regulator Output Voltage VREG - 3.0 - V Output voltage is selected by bonding option Regulator Output Voltage Drop VRDROP - - 100 mV IL = 1.0mA, VDD = 3.6V OSC Resistor ROSC - 160 - KΩ FOSC = 2.0MHz @ 3.0V - - 4.0 MHz FCPU = FOSC/1 @ 2.4V CPU Clock FCPU - - 6.0 MHz FCPU = FOSC/1 @ 3.6V Note: VLCD should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
© Generalplus Technology Inc. Proprietary & Confidential 12 JAN. 07, 2008 Version: 1.5 8. APPLICATION CIRCUITS 8.1. 6144 Dots LCD Driver, 96 Segments × 64 Commons with External Serial SRAM, Regulator Disabled - (1) Note*1: Pin VROUT should be connected to VDD if internal Regulator is disabled. Note*2: These capacitor values are for design guidance only. Different capacitor values may be requir ed for different crystal/resonator used. Note*3: Usually, these resistors/capacitors may not be needed when large L CD panel is connected. Differ ent resistor/capacitor values may be required for different LCD panel connected.
© Generalplus Technology Inc. Proprietary & Confidential 13 JAN. 07, 2008 Version: 1.5 8.2. 6144 Dots LCD Driver, 96 Segments × 64 Commons with External Bus ROM, Regulator Disabled - (2) Note*1: Detail settings of these pins please refer to the data sheet of GPR3206A. Note*2: Pin VROUT should be connected to VDD if internal Regulator is disabled. Note*3: These capacitor values are for design guidance only. Different capacitor values may be requir ed for different crystal/resonator used. Note*4: Usually, these resistors/capacitors may not be needed when large L CD panel is connected. Differ ent resistor/capacitor values may be required for different LCD panel connected.
© Generalplus Technology Inc. Proprietary & Confidential 14 JAN. 07, 2008 Version: 1.5 8.3. 6144 Dots LCD Driver, 96 Segments × 64 Commons with External Bus Flash, Regulator Enabled - (3) Note*1: Detail settings of these pins please refer to the data sheet of GPR1024A. Note*2: Pin VROUT should be connected to VDD if internal Regulator is disabled. Note*3: These capacitor values are for design guidance only. Different capacitor values may be requir ed for different crystal/resonator used. Note*4: Usually, these resistors/capacitors may not be needed when large L CD panel is connected. Differ ent resistor/capacitor values may be required for different LCD panel connected.
© Generalplus Technology Inc. Proprietary & Confidential 15 JAN. 07, 2008 Version: 1.5 8.4. 6144 Dots LCD Driver, 96 Segments × 64 Commons with Bus Extender, Regulator Disabled - (4) ROSC PC2/Tx PC3/Rx COM[63:0] SEG[95:0] PA0 PA1 PA2 PA3 PA4 PA5 PA6 Note*1: Pin VROUT should be connected to VDD if internal Regulator is disabled. Note*2: These capacitor values are for design guidance only. Different capacitor values may be requir ed for different crystal/resonator used. Note*3: Usually, these resistors/capacitors may not be needed when large L CD panel is connected. Differ ent resistor/capacitor values may be required for different LCD panel connected.
© Generalplus Technology Inc. Proprietary & Confidential 16 JAN. 07, 2008 Version: 1.5 8.5. Serial Communications between two GPLB39Bs - (5) Tx Rx Tx Rx GPLB39BGPLB39B 8.6. Serial Communications between GPLB39B and GPUSB101A Controller- (6) PA7 GPLB39BGPUSB101A PA6 PA5 PA4 SPI_CLK SPI_Tx SPI_Rx SPI_CSN
© Generalplus Technology Inc. Proprietary & Confidential 17 JAN. 07, 2008 Version: 1.5 9. PACKAGE/PAD LOCATIONS 9.1. Ordering Information Product Number Package Type GPLB39B-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc. Proprietary & Confidential 18 JAN. 07, 2008 Version: 1.5 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provis ions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, st atutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing or ders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 19 JAN. 07, 2008 Version: 1.5 11. REVISION HISTORY Date Revision # Description Page JAN. 07, 2008 1.5 Modify the diagrams in section 8. APPLICATION CIRCUITS. 12 - 16 DEC. 13, 2006 1.4 Modify the description to section 6.12. 8 JAN. 11, 2006 1.3 1. Modify the note4 to section 8.1 and 8.3. 2. Modify the note3 to section 8.2 and 8.4. 9, 11 10, 12 SEP. 23, 2005 1.1 Application circuits are modified. 8-11 MAR. 02, 2005 1.0 Original Note: The GPLB39B data sheet v1.0 is a continued version of SPLB39B data sheet v0.1.