GPLB31A

GPLB31A GENERALPLUS | Alldatasheet

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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPLLBB3311AA LCD CONTROLLER JAN. 07, 2008 Version 1.4 In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

© Generalplus Technology Inc. Proprietary & Confidential 2 JAN. 07, 2008 Version: 1.4 Table of Contents PAGE

© Generalplus Technology Inc. Proprietary & Confidential 3 JAN. 07, 2008 Version: 1.4 LCD CONTROLLER 1. GENERAL DESCRIPTION The GPLB31A, an 8-bit CMOS mi croprocessor, contains 4288 bytes working RAM, 256K bytes ROM, 14 I/Os, interrupt/wakeup controller, UART for serial comm unication, Serial SRAM interface and Bus memory interface for memory expansion, and automatic display controller/driver for LCD. It also features one PWM driver with two audio channels to produce attractive sound effects easily. Its large ROM area can be used to store both program and audio data (speech duration is approx. 69 seconds at a 7KHz sampling rate using a 4-bit ADPCM). The built-in UART speeds up data transmission between two devices. Furthermore, a SLEEP (power-down) function is also built in to extend power life. The GPLB31A is designed with state-of-the-art technology to fulfill LCD application needs, especially for hand-held products. 2. BLOCK DIAGRAM RC-Oscillator System Clock Gen. Power Supply Voltage Detect 256K bytes ROM 4288 bytes RAM Two 16-bit / Auto-reload Timers

32 KHz

Max.29 I/O Ports

32 Commons X 74 Segments LCD Driver

(I/O) COM[31:0] SEG[73:0] LCD RAM 296 bytes ROSC32 AUDB Serial SRAM I/F SDA/PC1 SCK/PC0 BUS Mem I/F MC[1:0]/PC[1:0] AD[7:0]/PB[7:0] PA[7:0] PB[7:0] PC[7:0] PD[4:0] Voltage Regulator x Note1: PA[3:7] share pins with SEG[73:69] (mask option). Note2: PB[7:0] share pins with Bus memory interface Addr/Data bus. Note3: PC[1:0] share pins with Bus memo ry interface MC[1:0]. Also share pins with Serial SRAM interface SDA/SCK. Note4: PC[3:2] share pins with UART Rx/Tx. Note5: PC[4:7] share pins with SEG[68:65] (mask option). Note6: PD[0:4] share pins with COM[31:27] (mask option). 3. FEATURES „ Built-in 8-bit processor ─ 4288 bytes SRAM ─ 256K bytes ROM ─ Max. operating speed: 4.0MHz @ 2.4V - 3.6V 5.0MHz @ 3.6V - 5.5V ─ CPU clock is software programmable, can be /1, /2, /4, /8, /16, /32, /64 R-oscillator clock frequency ─ Provides 6 wake-up sources ─ Provides 7 interrupt sources „ Asynchronous serial interface (UART) „ Serial SRAM interface „ Bus memory interface „ Built-in voltage regulator for external memory devices „ Key scan function ─ SEG[15:0] can be used to send key scan output „ Programmable LCD driver ─ Up to 74 segments, up to 32 commons, maximum 2368 dots ─ 1/5, 1/6 bias; 1/32 duty capability ─ 296 bytes dedicated LCD RAM ─ Built-in voltage regulator to generate VLCD for LCD driver ─ 32-level contrast control „ Power saving SLEEP mode „ Low voltage detector ─ 8-level 2.9V - 2.2V/4.35V - 3.3V detection ─ 2.2V Low voltage reset „ Wide operating voltage range: ─ 2.4V - 3.6V ─ 3.6V - 5.5V „ Peripherals ─ Max. 29 I/O pins (PA[7:0], PB[7:0], PC[7:0], PD[4:0]) . Dedicated I/Os: PA[2:0] . Shared pin I/Os: PA[3:7]/SEG[73:69] PB[7:0]/BMI AD Bus [7:0] PC[1:0]/BMI MC[1:0]/SSRAM SDA, SCK PC[3:2]/UART Rx/Tx PC[4:7]/SEG[68:65] PD[0:4]/COM[31:27] ─ 32.768KHz oscillator circuit for RTC ─ RC-oscillator (only one resistor is needed) ─ Two 16-bit reloadable timer/counters ─ 8-bit DAC resolution, 2-channel PWM audio outputs ─ Watchdog Timer for reliable operation

© Generalplus Technology Inc. Proprietary & Confidential 4 JAN. 07, 2008 Version: 1.4 „ Low-power consumption: ─ 600μ A typical @ 3.0V, FCPU = 1.0MHz, FOSC = 4.0MHz ─ 25μ A typical halt current @ 3.0V ─ <1 μA typical standby current @ 3.0V 4. APPICATION FIELD „ Handheld games „ Scientific calculator „ Talking calculator, Talking clock „ Talking instrument controller „ General speech synthesizer „ Data Bank

© Generalplus Technology Inc. Proprietary & Confidential 5 JAN. 07, 2008 Version: 1.4 5. SIGNAL DESCRIPTIONS Total: 142 pins Mnemonic PIN No. Type Description SEG24 - 0 SEG64 - 25 SEG68 - 65 / PC4 - 7 SEG73 - 69 / PA3 - 7 1 - 25 103 - 142 99 - 102 94 - 98 O LCD driver segment output. SEG15 - 0 share pin with key scan port. SEG68 - 65 optioned to PC4 – 7(PortC 4, 5 shared with Ext-I, Ext-ck). SEG73 - 69 optioned to PA3 - 7. COM15 - 0 COM26 - 16 COM31 - 27 / PD0 - 4 24 - 41 88 - 78 93 - 89 O LCD driver common output. COM31 - 27 can be optioned to PD0 - 4. PA2 - 0 58 - 60 I/O Port A is a bi-directional I/O port, which can be software programmed as wake up I/O. PB7 - 0 50 - 57 I/O Port B is a bi-directional I/O port. Share pin with Bus Memory Interface Addr/Data. PC1 / MC1 / SDA PC0 / MC0 / SCK I/O Port C is a bi-directional I/O port. S hare pin with Bus Memory MC1 - 0. Also share pin with SDA/SCK. PC3 / Rx 46 I/O UART input. Share pin with PC3. PC2 / Tx 47 I/O UART output. Share pin with PC2. ROSC 62 I ROSC input, connect to VDD through a resistor. RESET 66 I System reset input, low active. AUDA, AUDB 45, 43 O PWM audio output. X32I 65 I 32.768KHz crystal input or connect to VDD through a resistor (option). X32O 64 O 32.768KHz crystal output. TEST 63 I Test input. CUP4 - 1 72 - 69 P LCD voltage generation. Charge pump capacitor interconnection pins. VLCD 77 P LCD voltage generation. V4 - 1 76 - 73 P LCD voltage generation. VROUT 68 P Internal regulator output. Enable or disable via bonding option. Should be connected to VDD if internal Regulator is disabled. VDD 67 P Power supply voltage input. VSS 61 P Ground reference. PVDD 44 P PWM driver power. PVSS 42 P PWM driver ground reference. BOPT1 - 0 67A, 44A B Internal regulator output voltage select option pin (internally pull-low)*. BOPT2 61A B Internal regulator enable/disable option pin (internally pull-high)*. Legend: I = Input, O = Output, P = Power, B = Bonding option Note: *See bonding option section for details.

© Generalplus Technology Inc. Proprietary & Confidential 6 JAN. 07, 2008 Version: 1.4 5.1. PAD Assignment This IC substrate should be connected to VSS Note1: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible. Note2: Pin VROUT should be connected to VDD if internal Regulator is disabled.

© Generalplus Technology Inc. Proprietary & Confidential 7 JAN. 07, 2008 Version: 1.4 6. FUNCTIONAL DESCRIPTIONS 6.1. Memories The GPLB31A contains 256K-byte ROM and 4288-byte SRAM. Cooperating with Generalplus bus extender, GPBA01B, the external memory, either RAM or ROM, can be extended up to 4MB. Serial SRAM interface is also provided in GPLB31A, thus SRAM space can be extended by using Generalplus Serial SRAM, GPRS256B or GPRS512C. 6.2. Map of Memory and I/Os *NMI SOURCE: - L V D E T E C T - T I M E R 1 *INT SOURCE: - E X T I N T - TBL (2/4/8/16Hz) - TBH (128/256/512/1KHz) - T I M E R 0 - T I M E R 1 - U A R T T X - U A R T R X ROM (Bank)H I/O & $0000-$003F $3E00-$3FFF $4000-$7FFF $8000-$BFFF $C000-$FFF9 $FFFA-$FFFF CPU View ROM View Bank Address: $0 $C000-$FFFF always mapping into 0L . . . Reg. $0040-$10FF ROM (Bank)L Interrupt ROM DPRAM RAM $38000 - $3BFFF $3C000 - $3FFFF $00000 - $03FFF $04000 - $07FFF $08000 - $0BFFF $0C000 - $0FFFF $10000 - $13FFF $14000 - $17FFF 1. $4000-$BFFF can be external memory if MEXT ($07.7) = 1 and Bank port ($00.7) = 1. 2. $C000-$FFFF can be external memory if MEXT ($07.7) = 1 and EXC($0b.1) = 1. 3. User program should start from $C800. $C000-$C7FF is the test program area. 4. User program interrupt vector: $FFFA ~ $FFFF 5. Test program interrupt vector: $FFF2 ~ $FFF7 6.3. Operating States There are three operation modes involved in GPLB31A: standby, halt and operating. The following table shows the differences between these modes. Operating Halt Standby CPU ON OFF OFF 32768Hz oscillator ON ON OFF LCD driver ON ON/OFF OFF 6.3.1. Operating mode In operating state, all functions (CPU, 32768Hz oscillator, timer/counter, LCD driver…) are ac tivated. Generally speaking, this mode consumes the highest current. 6.3.2. Standby mode Write “07H” to P_04H_CPU_Clk_Ctrl Register ($04) and turn off 32768Hz oscillator to activate standby mode. The standby mode is a mode where the device is placed in its lowest current consumption state. In standby mode, all functions are turned off; in addition, RAM and I/Os will remain in their previous states. 6.3.3. Halt mode Write “07H” to P_04H_CPU_Clk_Ctrl Register ($04) but still keeps 32768Hz oscillator running to enter halt mode. In halt mode, CPU clock halts and waits for an event (key press, timer overflow) to wake up. The 32768Hz related functions, such as timer/counter and LCD driver, may remain active in the halt mode.

© Generalplus Technology Inc. Proprietary & Confidential 8 JAN. 07, 2008 Version: 1.4 The following figure is the GPLB31A state diagram: GPLB31A State Diagram 6.4. Speech and Melody For speech synthesis, the GPLB 31A provides several timer interrupts for a precise sampling frequency. The sound data can be stored into ROM and be played back. Several algorithms are recommended for high fidelity and good compression of sound such as PCM and ADPCM. For melody synthesis, the GPLB31A provides a dual tone mode. Once in the dual tone mode, users only need to program the tone frequency for each channel by writing to the timer/counter TM0 and TM1, and set the envelope of each channel. The hardware will toggle the tone wave automatically. 6.5. LCD Controller/Driver The GPLB31A contains a 2368-dot LCD controller/driver. Programmers is able to define the LCD configuration by setting up the LCD Control Register. Once the LCD configuration is completed, the desired pattern can be displayed by filling the LCD buffer with proper data. The LCD driver can also operate during sleep by keeping 32768Hz oscillator running. The LCD driver in GPLB31A supports 1/16 - 1/32 duty and 1/5 - 1/6 bias. 6.6. LCD Voltage Generation The GPLB31A offers a voltage regulator and a charge-pumping circuit. The voltage regulator pr ovides a reference voltage (V2) for the charge-pumping circuit to generate VLCD. Users can get the desired VLCD by changing the output reference voltage (writing to register) of the voltage regulator. Enabling the voltage regulator and charge-pumping circuit gets a stable VLCD that will not be affected by VDD. The VLCD is adjustable from 2.45V to 5.75V (in 1/5 LCD bias) or 2.95V to 6.85V (in 1/6 LCD bias) with 32 levels. 6.7. PWM Output Internally, the GPLB31A has a pair of PWM drivers, supporting two sound channels. Each channel is able to play speech or tone individually. The PWM drivers can directly drive speaker or buzzer without buffer or amplification circuit. HALT OPERATING STANDBY Write $07h to CPU_Clk_Ctrl register, 32768 oscillator OFF Wake-up or user reset Write $07h to CPU_Clk_Ctrl register, 32768 oscillator ON Wake-up or user reset 6.8. Serial SRAM Interface The Serial SRAM interface is able to expand the data storage SRAM. The Control Registers are ranged from $30-$36. Note that The pins of SDA and SCK are shared with PC [1:0] and therefore, users should set PC[1:0] as Serial SRAM interface by writing to Port $27[1:0]. SDA SCK change of data allowed data line stable; data valid START condition (S) SDA SCK STOP condition (P) 6.8.1. Read/Write timing R/WA23 D7A0 D6 D5 D4 D3 D2 D1 D0SDA SCK stopstart 6.8.2. Continuous Read/Write timing R/WA23 D7A0 D6 D0 D7 D0 D7 D0 D0D7SDA SCK addr stopstart addr+1 addr+n 6.9. Bus Memory Interface A built-in Bus memory interface is available on GPLB31A. Through the use of Bus memory interface, user can expand the memory space by using an external Bus memory (SRAM, mask ROM or Flash). The Bus memory interface includes 10 signal pins: MC1, MC0 and AD BUS[7:0] which shared pad with port B.

© Generalplus Technology Inc. Proprietary & Confidential 9 JAN. 07, 2008 Version: 1.4 Before using the Bus memory interface, users should set MEXT=1 ($03.7) and BANK register ($0), then access address $4000-BFFF to read or write data from external bus memory. Note that when using Bus memory interface, CPU clock setting can not be set as F OSC/1, should be /2 or slower. MC1 MC0 AD BUS [7:0] L L Data for Write L H Data for Read H L AL (Address Low byte) H H AH (Address High byte) 6.10. Voltage Regulator The GPLB31A offers a voltage regulator, which supplies power source for external memory devices. The voltage regulator can The output voltage level should be properly selected based on the electrical characteristics of external memory devices involved. 6.11. Asynchronous Serial Interface (UART) The GPLB31A supports a 1- channel UART for serial communications. The bit-rate is up to 115.2kbps. UART operation is controlled by UART command registers. Configurations such as Tx/Rx interrupt, parity check, parity even/odd and clock source can be configured in the command registers. Two interrupts are generated by Rx and Tx. The Rx or Tx interrupt activates when a byte is received or transmitted. Reading the status register informs whether the interrupt is generated by Rx or Tx. Frame, overrun and parity errors are detected as each byte is receiv ed and all error status can be read from status register. The UART supports clock auto calibration. If auto calibration is selected, standard baud rate from 1.2kbps to 115.2kbps are available. The baud rate is selected by writing to the baud rate control registers. The supported baud rates and their minimum R-oscillator clock frequency requirements are shown in the table below. Baud Rate(bps) Min. Frosc(Hz) 1200 24000 2400 48000 4800 96000 9600 192000 19200 384000 38400 768000 51200 1024000 57600 1152000 102400 2048000 115200 2304000 If the auto calibration is not selected, users can get desired baud rates by writing appropriate values to pre-scalar registers. Non-standard baud rates can be obtained by this method. In the non-calibration mode, users should understand that the R-oscillator frequency may alter due to manufacturing process variations, supply voltage, operating temperature and tolerance of external R components used. 6.12. Low Voltage Detection The GPLB31A provides an 8-level (Software programmable) low voltage detector to detect low voltage events. Users can turn on the low detection to monitor VDD periodically to check if it is lower than the given value. In addition, if LV NMI is enabled, a NMI will be issued to notify CPU if power voltage drops below the given value. Also, the voltage detector will generate a system reset if power supply voltage drops below 2.2V. When LVR function is enabled, care must be taken not to turn off 32KHz crystal oscillator. Otherwise an unexpected reset may occur when 32KHz crystal is being turned on again. 6.13. Watchdog Timer (WDT) An on chip watchdog timer is also available in the GPLB31A. The WDT is designed to recover the system from abnormal operation. In some cases, if WDT is not cleared for one second, the WDT will generate a system reset to restart system. If WDT is enabled, the WDT should be clear ed every 0.5 second to avoid accidental reset. The WDT can be cleared through software programming. Note that the WDT only works when 32768Hz clock is activated.

© Generalplus Technology Inc. Proprietary & Confidential 10 JAN. 07, 2008 Version: 1.4 6.14. Mask Options 6.15. Bonding Options 1). X’TAL 1). Enable 2). R-oscillator 2). Disable 1). Enable 1). 2.5V 2). Disable 2). 2.6V 3). 2.7V Each port/segment can be optioned as I/O or LCD segment output individually. Each port/segment can be optioned as I/O or LCD segment output individually. Each port/segment can be optioned as I/O or LCD segment output individually. Figure1: Bonding option for regulator Enable/Disable VSS BOPT2 BOPT2 = 1 Regulator disable VSS BOPT2 BOPT2 = 0 Regulator enable PCB IC PVDD BOPT1 = 0 BOPT0 = 0 V REG = 2.5V VDD PVDD BOPT1= 0 BOPT0 = 1 V REG = 2.6V VDD PVDD BOPT0 BOPT1 = 1 BOPT0 = 0 V REG = 2.7V VDD BOPT1 PVDD BOPT0 BOPT1 = 1 BOPT0 = 1 V REG = 3.0V VDD BOPT1 BOPT0 BOPT1 BOPT0 BOPT1 IC PCB IC PCB Figure2: Bonding option for regulator output voltage select

© Generalplus Technology Inc. Proprietary & Confidential 11 JAN. 07, 2008 Version: 1.4 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating ta ble may cause operational errors or damage to the device. For no rmal operational conditions see AC/DC Electrical Characteristics. 7.2. DC Characteristics Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition 2.4 - 3.6 V For 2-battery Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 600 - μA FCPU = 1.0MHz @ 3.0V FROSC = 4.0MHz, no load Halt Current IHALT - 25 - μA VDD = 3.0V, 32K X’tal ON, LCD ON, no LCD panel Standby Current ISTBY - - 1.0 μA VDD = 3.0V, all off - -20 - mA VDD = 3.0V, VOH = 2.5V Audio Output Current IOH - -40 - mA VDD = 3.0V, VOH = 2.0V - 20 - mA VDD = 3.0V, VOL = 0.5V Audio Output Current IOL - 40 - mA VDD = 3.0V, VOL = 1.0V Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output High Current (I/O) IOH -1.0 - - mA VDD = 3.0V, VOH = 2.4V Output Sink Current (I/O) IOL 1.0 - - mA VDD = 3.0V, VOL = 0.8V 2.45 - 5.75 V VDD = 3.0V, 1/5 bias, no load LCD Driver Voltage (VLCD - VSS) VLCD 2.95 - 6.85 V VDD = 3.0V, 1/6 bias, no load - 2.5 - - 2.6 - - 2.7 - Regulator Output Voltage VREG - 3.0 - V Output voltage is selected by bonding option Regulator Output Voltage Drop VRDROP - - 100 mV IL = 1.0mA, VDD = 3.6V OSC Resistor ROSC - 160 - KΩ FOSC = 2.0MHz @ 3.0V 32KHz OSC Resistor R32K - 680 - KΩ F32K=32KHz@3.0V - - 4.0 MHz FCPU = FOSC/1 @ 2.4V CPU Clock FCPU - - 5.0 MHz FCPU = FOSC/1 @ 3.6V Note: VLCD should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.

© Generalplus Technology Inc. Proprietary & Confidential 12 JAN. 07, 2008 Version: 1.4 7.3. The Relationships between the ROSC and the FOSC 7.3.1. VDD = 3.0V 0 100 200 300 400 500 600 700 800 900 Rosc (kΩ) Fosc(MHz) 7.3.2. VDD = 4.5V 0 100 200 300 400 500 600 700 800 900 Rosc (kΩ) Fosc(MHz) 7.4. The Relationships between the VDD and the FOSC 22 . 533 . 544 . 555 . 5 VDD(V) Fosc(MHz) Rosc=97KΩ Rosc=207kΩ 7.5. The Relationships between the FOSC and the IOP 200 400 600 800 1000 1200 1400 012345 VDD(V) Iop(uA) 7.6. The Relationships between the VDD and the R32K R32K 22 . 433 . 544 . 555 . VDD KHz R32768=638kΩ R32768=730kΩ

© Generalplus Technology Inc. Proprietary & Confidential 13 JAN. 07, 2008 Version: 1.4 8. APPLICATION CIRCUITS 8.1. 2240 Dots LCD Driver, 70 Segments × 32 Commons with External Serial SRAM, Regulator Disabled - (1) GPLB31A LCD Panel (32x70) PVDD PVSS AUDB ROSC X32I X32O RESET VDD AUDA PA0 PA1 PA2 PA3 PA4 PA5 VDD PC2/Tx PC3/Rx COM[31:0] SEG[69:0] PB[7:1] VDD VSS SCK SDA CSB PC1/SDA PC0/SCK PB0 VDD GPRS512C SEG0 SEG1 SEG14SEG2 SEG15 PA1 PA2 PA3 PA4 PA5 VLCD CUP1 CUP2 CUP3 CUP4 C*3 1/5, 1/6 Bias PA6 C C C C C C VROUT *1 VDD 4.7μF0 . 1 μF 20pF*2 20pF*2 0.1μF 30pF Note*1: Pin VROUT should be connected to VDD if internal Regulator is disabled. Note*2: These capacitor values are for design guidance only. Differ ent capacitor values may be required for different crystal/resonator used. Note*3: The value of the capacitance(C) would range from 0.1μF to 4.7μF to stable the output voltage.

© Generalplus Technology Inc. Proprietary & Confidential 14 JAN. 07, 2008 Version: 1.4 8.2. 2240 Dots LCD Driver, 70 Segments × 32 Commons with External Bus ROM, Regulator Disabled - (2) GPLB31A LCD Panel (32x70) PVDD PVSS AUDB ROSC X32I X32O RESET VDD AUDA PA0 PA1 PA2 PA3 PA4 PA5 VDD PC2/Tx PC3/Rx COM[31:0] SEG69:0] SEG0 SEG1 SEG14SEG2 SEG15 PA1 PA2 PA3 PA4 PA5 PA6 VLCD CUP1 CUP2 CUP3 CUP4 1/5, 1/6 Bias C C C C C C C *4 MC0 MC1 AD[7:0] PC1/MC1 PC0/MC0 PB[7:0] VDD VSS CF[3:0] VDD (SPR3206A) Bus ROM RESET VROUT *2 VDD 4 *1 4.7μF0 . 1 μF 20pF *3 20pF *3 0.1μF 30pF Note*1: Detail settings of these pins please refer to the data sheet of SPR3206A. Note*2: Pin VROUT should be connected to VDD if internal Regulator is disabled. Note*3: These capacitor values are for design guidance only. Different capacitor values may be requir ed for different crystal/resonator used. Note*4: The value of the capacitance(C) would range from 0.1μF to 4.7μF to stable the output voltage.

© Generalplus Technology Inc. Proprietary & Confidential 15 JAN. 07, 2008 Version: 1.4 8.3. 2240 Dots LCD Driver, 70 Segments × 32 Commons with External Bus Flash, Regulator Enabled - (3) GPLB31A LCD Panel (32x70) PVDD PVSS AUDB ROSC X32I X32O RESET VDD AUDA PA0 PA1 PA2 PA3 PA4 PA5 VDD PC2/Tx PC3/Rx COM[31:0] SEG[69:0] MC0 MC1 AD[7:0] PC1/MC1 PC0/MC0 PB[7:0] SEG0 SEG1 SEG14SEG2 SEG15 PA1 PA2 PA3 PA4 PA5 PA6 VSS CF[4:0] VDD (GPR1024A) Bus Flash 5 *1 VLCD CUP1 CUP2 CUP3 CUP4 1/5, 1/6 Bias RESET SDA SCK ENZ C *4 VROUT *2 10μF0 . 1 μF 4.7μF0 . 1 μF 20pF *3 20pF *3 0.1μ F 30pF C C C C C C Note*1: Detail settings of these pins please refer to the data sheet of GPR1024A Note*2: Pin VROUT should be connected to VDD if internal Regulator is disabled. Note*3: These capacitor values are for design guidance only. Different capacitor values may be requir ed for different crystal/resonator used. Note*4: The value of the capacitance(C) would range from 0.1μF to 4.7μF to stable the output voltage.

© Generalplus Technology Inc. Proprietary & Confidential 16 JAN. 07, 2008 Version: 1.4 8.4. 2240 Dots LCD Driver, 70 Segments × 32 Commons with Bus Extender, Regulator Disabled - (4) GPLB31A LCD Panel (32x70) PVDD PVSS AUDB ROSC X32I X32O RESET AUDA VDD PC2/Tx PC3/Rx COM[31:0] SEG[69:0] MC0 MC1 AD[7:0] PC1/MC1 PC0/MC0 PB[7:0] VDD SEG0 SEG1 SEG14SEG2 SEG15 PA1 PA2 PA3 PA4 PA5 VSS CI VDD Bus Extender GPBA01B VLCD CUP1 CUP2 CUP3 CUP4 1/5, 1/6 Bias DVP VDD XP[10:17] XP[20:26] XP[03:00] WR RD XP27 A[7:0] A[14:8] A[18:15] WE OE CE D[7:0]8 VDD VDD VSS External ROM/SRAM PA6 PA0 PA1 PA2 PA3 PA4 PA5 C C C C C C C *3 VROUT *1 VDD 4.7μF0 . 1 μF 20pF *2 20pF *2 0.1μF 30pF Note*1: Pin VROUT should be connected to VDD if internal Regulator is disabled. Note*2: These capacitor values are for design guidance only. Different capacitor values may be requir ed for different crystal/resonator used. Note*3: The value of the capacitance(C) would range from 0.1μF to 4.7μF to stable the output voltage.

© Generalplus Technology Inc. Proprietary & Confidential 17 JAN. 07, 2008 Version: 1.4 8.5. Serial Communications between two GPLB31As - (5) Tx Rx Tx Rx GPLB31AGPLB31A

© Generalplus Technology Inc. Proprietary & Confidential 18 JAN. 07, 2008 Version: 1.4 9. PACKAGE/PAD LOCATIONS 9.1. Ordering Information Product Number Package Type GPLB31A-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).

© Generalplus Technology Inc. Proprietary & Confidential 19 JAN. 07, 2008 Version: 1.4 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in th is publication or regarding the freedom of t he described chip(s) from patent infringement. FURTHER, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are curr ent before placing orders. Products descri bed herein are intended for use in normal com mercial applications. Applications involving unusual environmental or reliability requirements, e.g. militar y equipment or medical lif e support equipment, are specifically not recommended wi thout additional processing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.

© Generalplus Technology Inc. Proprietary & Confidential 20 JAN. 07, 2008 Version: 1.4 11. REVISION HISTORY Date Revision # Description Page JAN. 07, 2008 1.4 Modify the diagrams in section 8. APPLICATION CIRCUITS. 13 - 17 FEB. 14, 2007 1.3 1. Modify the DC Characteristic to section 7.2. 2. Add “The Relationships between the VDD and R32K” to section 7.6. DEC. 12, 2006 1.2 Modify the description to section 6.12. 8 DEC. 14, 2005 1.1 1. Modify port C shared pin to section 3 and 5. 2. Modify the descriptions to section 6.1 and 8. 1, 3 4, 10 MAR. 03, 2005 1.0 Original Note: The GPLB31A data sheet v1.0 is a continued version of SPLB31A data sheet v0.4.