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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. G G G L Sep. 11, 2013 Version 1.2 PPLL881111PP0088AA GPPLL881111PP0044AA Looww PPoowweerr 666600 DDoottss LLCCDD CCoonnttrroolllleerr wwiitthh 6644KKBB//3322KKBB OOTTPP RRoomm In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
/GPL811P04A © Generalplus Technology Inc. Proprietary & Confidential 2 Sep. 11, 2013 Version: 1.2 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 Sep. 11, 2013 Version: 1.2 LOW POWER 660 DOTS LCD CONTROLLER WITH 64KB/32KB OTP ROM 1. GENERAL DESCRIPTION GPL811P08A/GPL811P04A, a s pecial designed CMOS 8-bit microprocessor by Generalplus, offers the best cost/performance ratio in the industry. It combines RAM, one-time programmable (OTP) ROM, I/Os, an interrupt controller, and an automatic display controller/driver in a small device. Its extraordinary features is the capability of operating in low voltage range from 2.2V ~ 3.6V and also operating under low power. This device is capable for many application fields such as low power watch and other LCD related products. 2. FEATURES Built-in 8-bit processor 2432-byte SRAM 64K-byte OTP ROM(GPL811P08A) 32K-byte OTP ROM(GPL811P04A) 88 byte DPRAM Built-in 225k/500k/1000k/1800kHz RC oscillator for system operation - adjustable CPU clock speed : 1, 1/2, 1/4, 1/8, 1/16 for R OSC Built-in 30.72kHz RC oscillator & 32768 Crystal oscillator circuit for timebase Low standby current, ISTBY < 1uA @3.6V, 25 ℃ 22 general I/O pins. - PD[5:0](PD[5:3] shared with SEG[57:59]; PD[1:0] shared with 2 buzzers) - PC[3:0](shared with SEG[53:56]) - PA[3:0](shared with SPI SDO/SDI/SCK/CSN pin - PE[7:0] - Built-in 2 x RFC function (PD2 used as input, PD[5:3] used as output) Serial Peripheral Interface(SPI) - CSN/SCK/SDI/SDO pin shared with PA[0:3] LCD configurations: 11 coms x 60 segs (MAX) , 3x60, 4x60, 5x60, 6x60, 8x60, 9x60, 10x60, 4x64 One 16-bit reloadable timer/ counter(Timer0), one 8-bit reloadable timer/counter(Timer1) Watchdog mode (~2 sec) 9 interrupt sources (TMBB, TMBA, 128Hz, 2KHz, Timer0, Timer1, EXT(PD2), SPI, LVD(2.0V/2.2V/2.4V/2.6V)) Power down mode (wake-up source: key input, TMBB, TMBA, 128Hz, Timer0) Low power consumption: - 200u @ 3.6V, F CPU = 225KHz for operating mode - 3u@ 3.6V, F CPU = 225KHz for halt mode - I stby < 1uA @ 3.0V Built_in internal regulator for LCD operation, 5-level contrast control Built_in Low voltage reset to avoid system runaway at low voltage Note1: TMBB: 4KHz, 1KHz, 128Hz, 64Hz, 32Hz, 16Hz, 8Hz or 4Hz Note2: TMBA: 2Hz or 1Hz
© Generalplus Technology Inc. Proprietary & Confidential 4 Sep. 11, 2013 Version: 1.2 3. BLOCK DIAGRAM 3.1. GPL811P08A PA[3:0] PC[3:0] PD[5:0] PE[7:0] ACON 8-bit CPU SPI VLCD Generator LVR & LVD 64 kB OTP ROM 2432 B RAM Watchdog Timer Power Saving Control 16 -bit Timer/Counter 8 -bit Timer
11 Com * 60 Seg
(HF/LF) CSN, SCK, SDI, SDO CUP[1:0] VLCD,V3X, V2X,V1XCOM[10:0] SEG[52:0] PTEST XTAL32K X32I X32O OTP SIF/PIFVPP, PIEP Internal Regulator VREG 3.2. GPL811P04A
© Generalplus Technology Inc. Proprietary & Confidential 5 Sep. 11, 2013 Version: 1.2 4. SIGNAL DESCRIPTIONS 4.1. PIN Description Mnemonic Type Description VDD O Power input VSS I Ground input VREG O Internal regulator output. COM[2:0] O LCD driver common output COM[10:3] O LCD driver common output. (COM[10:4] can be option to SEG[57:63];COM3 can be option to SEG56) SEG[52:0] O LCD driver segment output PD[5:0] I/O GPIO I/O port. (PD[5:3] shared with SEG[57:59]; PD[1:0] shared with 2 buzzers) In RFC application, PD[5:3]is used as pass-through (output) pin and connected to sensor. PD2 used as input-floating pin and connected to sensor & capacitor. PC[3:0] I/O GPIO I/O port (shared with SEG[53:56]) PE[7:0] I/O GPIO I/O port PA[3:0] I/O GPIO I/O port (PA[0:3] shared with SPI CSN/CLK/SDI/SDO pin) PIEP I OTP programming interface enable ACON I Clear or system power on pin (active low) and 4ms de-bounce circuit inside VPP P OTP programming power. Should left floating or connect to VSS in normal operating mode PTEST I Test mode input pin (active high) X32I I 32768Hz crystal input X32O O 32768Hz crystal output V1X V2X V3X VLCD O VLCD generator output CUP1 CUP2 I Inputs for setting LCD bias 101pin
© Generalplus Technology Inc. Proprietary & Confidential 6 Sep. 11, 2013 Version: 1.2 4.2. PIN Map(128 pin LQFP) SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 NC NC SEG21 SEG22 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PA1 PA0 ACON PIEP X32I X32O PTEST VREG VSS CUP2 CUP1 V1X V2X V3X VLCD SEG0 SEG1 SEG2 SEG3 SEG4 COM9 COM10 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 PD1 PD0 PD2 PA2 PA3 PD3 PD4 PD5 PC0 PC1 PC2 PC3 COM0 COM1 COM2 COM3 COM4 COM5 COM8 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 VDD VPP COM6 COM7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
© Generalplus Technology Inc. Proprietary & Confidential 7 Sep. 11, 2013 Version: 1.2 5. FUNCTIONAL DESCRIPTIONS 5.1. CPU The 8-bit microprocessor in GPL811P08A/GPL811P04A is a high performance processor equipped with Accumulator, Program Counter, X Register, Y Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). 5.2. Clock Source The GPL811P08A/GPL811P04A equips with two groups of clock sources: (1) High speed frequency (RCHF) to support the whole system operation. It offers four frequency options: 225k/ 500k/ 1000k/ 1800kHz and can be selected by register $18H that rely on user different application. GPL811P08A/GPL811P04A provides programmable CPU clock speed 1, 1/2, 1/4, 1/8, or 1/16 of RCHF for power saving. (2) Low speed frequency to control LCD frame rate and time base timer. It comes from XTAL32K or IOSC30K selected by mask option. 5.3. ROM/RAM Area The GPL811P08A/GPL811P04A features 64K-byte ROM that can be defined as the program area and its address located from $4000 to $FFFF. Its RAM consists of 2432 bytes (including Stack) at locations from $60 through $9DF. 5.4. Stop Clock Mode The GPL811P08A/GPL811P04A prov ides a power saving mode for those applications required very low stand-by current. Users can simply enable the wake-up sources to stop the CPU clock by writing the STOP CLOCK Register ($09). By doing that, CPU will go to standby mode and the RAM and I/Os remain in their previous states until awake. Th ere are five wake-up sources in the GPL811P08A/GPL811P04A: Port PortE wake-up, TMBB, TMBA, T128Hz or Timer0 wake-up. After the GPL811P08A/GPL811P04A wakes up, CPU will go to the next state where CPU enters sleep mode. Wake-up action will not influence RAM and I/Os. Note1: TMBB: 4KHz, 1KHz, 128Hz, 64Hz, 32Hz, 16Hz, 8Hz or 4Hz Note2: TMBA: 2Hz or 1Hz 5.5. I/O Ports The GPL811P08A/GPL811P04A has four ports: PortA, PortC, PortD, and PortE. These port pins all equip with special features for key board scan. In general, when an initial reset starts, all ports are used as a general purpose input port. All PortA, PortC, PortD, and PortE contain three parts: data, direction and attribution registers. Program mer should follow the table below to define each I/O function with corresponding bit in each port. PortA[3:0], PortC[3:0], PortD[5:0] , PortE[7:0] Attribution Direction Data Function Description 0 0 0 Input with pull-low 0 0 1 Pure Input 0 1 0 Output Low 0 1 1 Output High General Purpose I/O function 1 1 0 Pad Floating Special function 5.6. RFC Function The RFC (Resistor to Frequency Converter) ci rcuit contains a RC oscillation circuit and a 16-bit time r/counter to calculate the resistance of temperature or humidity sensor relative to referenced resistor. The circuit is shown below.
© Generalplus Technology Inc. Proprietary & Confidential 8 Sep. 11, 2013 Version: 1.2 RREF RTH RTEMP PD5 PAD PD4 PAD PD3 PAD PD2 PAD SMT 16 bit Timer/Counter 8-Bit data bus RFCEN PD5 floating control PD4 floating control PD3 floating control 5.7. LCD Controller GPL811P08A/GPL811P04A contains a LCD controller/driver that provides the capability to dr ive 11 commons and 60 segments LCD. To light the overhead of CPU, a display buffer is designed for mapping to LCD. A LCD dot/pattern is set ON or OFF by programming the corresponding bit of the display buffer. In addition, the LCD bias can be programmed as 1/3 or 1/4. The duty can be selected as 1/3, 1/4, 1/5, 1/6, 1/8, 1/9, 1/10 or 1/11. The frame rate is set to 71Hz at 1/9 duty, 77Hz at 1/10 or 1/5 duty, and 70Hz at 1/11 duty. When 1/3, 1/4, 1/6 or 1/8 duty is selected, its frame rate is set to 80Hz. The frame rate is measured when low speed frequency is 30.72KHz. 5.8. LCD Voltage Generation The GPL811P08A/GPL811P04A offers a voltage regulator and a charge-pumping circuit. The voltage regulator provides a reference voltage V1X for the charge-pumping circuit to generate V2X, V3X and VLCD. Users can get the desired VLCD by changing the output reference voltage (writing to register) of the voltage regulator. Enabling the voltage regulator and charge-pumping circuit gets a stable VLCD that will not be affected by VDD. The VLCD is adjustable from 3V to 4.5V with 5 levels at 1/3bias, or 4.0V to 6.0V with 5 levels at 1/4bias. 5.9. Buzzer Driver PD[1:0] can be used as buzzer output. When $16.b1 = b0 = ’1’, PD.1 and PD.0 are set for buzzer output. Or else when b1 = b0 = ’0’, PD.1 and PD.0 are set to normal I/O. When counter overflows, it will toggle PD.1 and PD.0 for driving buzzer. 5.10. Auxiliary Calculation Hardware GPL811P08A/GPL811P04A contai ns auxiliary calculation hardware. This hardware allows some nibble operation to accomplish only at one store and load instruction. The original data content should be stored at t he register ($50, $51) firstly and then many decimal operations, e.g. x10,/10 or nibble swap, can be gotten just by executing reading instruction at the relative register ($52~5F). It speeds up many decimal operations that originally need many instructions for one operation. 5.11. Analog Block In addition to the LCD controller and clock source, GPL811P08A/GPL811P04A also provides many low power and useful analog blocks. 1.5V internal regulator by re gister provides whole system operation at low current environment. Internal low voltage reset analog block prevents system from abnormality at the voltage lower than the operation range. 5.12. SPI Controller A Serial Peripheral Interface (SPI) controller is built in GPL811P08A/GPL811P04A to facilitate communicating with other devices and components. There are four control signals on SPI including SPICSN, SPICLK (SCK), SPIRX (SDI), and SPITX (SDO); the four signals are shared with PA0, PA1, PA2 and PA3. While SPI module is enabled by corres ponding control bit. These four pins cannot be IO and any setti ng on corresponding GPIO control register will have no effect. Four types of timing are supported as follows:
/GPL811P04A © Generalplus Technology Inc. Proprietary & Confidential 9 Sep. 26, 2012 Version: 1.0 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX MSB MSB Master Mode, SPO = 0, SPH=0 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX Q Q Master Mode, SPO = 0, SPH=1 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX Q Master Mode, SPO = 1, SPH=0 MSB LSB SPICLK SPICSN SPITX SPIOE 8b i t s MSB LSBSPIRX Q Q Master Mode, SPO = 1, SPH=1
© Generalplus Technology Inc. Proprietary & Confidential 10 Sep. 11, 2013 Version: 1.2 5.13. Map of Memory 5.13.1. GPL811P08A 5.13.2. GPL811P04A 5.14. OTP Programming Circuit Note1: Don’t connect any component with PE7 and PE6 when programming. Note2: Connect PIEP to VDD during OTP programming cycle, and keep it floating in normal run. Note3: Connect VPP to Writer during OTP programming cycle, and keep it floating in normal run.
© Generalplus Technology Inc. Proprietary & Confidential 11 Sep. 11, 2013 Version: 1.2 6. ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ -0.3~5 V Input Voltage Range VIN -0.3V to V+ + 0.3V Operating Temperature TOPR -20℃ to +70℃ Storage Temperature TSTG -40℃ to +125℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to t he device. For normal operational conditions see AC/DC Electrical Characteristics. 6.2. DC Characteristics(TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Terminal Test Condition Operating Voltage VCC 2.2 - 3.6 V VDDSW Input High Level VIH Vdd*0.7 - Vdd V Input Low Level VIL - - Vdd*0.3 V PA,PC, PD,PE Output High Current (I/O) IOH 2 - - mA Vdd = 3.0V, VOH = 0.7*Vdd Output Sink Current (I/O) IOL 4 - - mA PA,PC, PD,PE Vdd = 3.0V, VOL = 0.3*Vdd Output High Current (Buzzer) IOH 8 - - mA Vdd = 3.0V, VOH = 0.7*Vdd Output Sink Current (Buzzer) IOL 12 - - mA PD[1:0] Vdd = 3.0V, VOL = 0.3*Vdd 3.0~4.5 1/3 bias At 25 deg LCD Bias Voltage VLCD -5% 4.0~6.0 +5% V VLCD 1/4 bias At 25 deg Pull low Resistance RPL - 60 - Koh m PA, PC, PD,PE VDD=2.2~3.6V -20% 225 +20% Clock select as 225kHz
500 Clock select as 500kHz
1000 Clock select as 1000kHz
-20% 30.72 +20% Low speed clock select as IOSC30K Low Frequency FL - 32768 - kHz X32I,X32O Low speed clock select as XTAL32K - 200 - uA High Frequency =225kHz, CPU on, LCD on, no load (VDD=3.0V) - 350 - uA High Frequency =500kHz, CPU on, LCD on, no load (VDD=3.0V) - 600 - uA High Frequency =1000kHz, CPU on, LCD on, no load (VDD=3.0V) Operating Current IOP - 1000 - uA High Frequency =1800kHz, CPU on, LCD on, no load (VDD=3.0V) Halt Current IHALT - 3 - uA Low Frequency active, CPU off, LCD on, no load(VDD=3.0V) @50℃ Standby Current ISTBY - - 1 uA Clock is stopped, LCD off(VDD=3.0V) @25℃ Note: Vlcd should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
© Generalplus Technology Inc. Proprietary & Confidential 12 Sep. 11, 2013 Version: 1.2 7. APPLICATION CIRCUITS GPL811P08A /GPL811P04A LCD Panel (11x60) V2X CUP2 CUP1 VLCD PD[2:0] COM[10:0] SEG[59:0] 0.1uF 0.1 uF PE[7:0] I/O or key matrix 0.1uF V1X 0.1uF V3X 0.1uF 0.1uF VREGACON VDD VSS 10uF Key 0.1uF X32I X32O 12-20pF*1 32768Hz 12-20pF*1 CSN CLK SDI SDO SPI module Note1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc. Proprietary & Confidential 13 Sep. 11, 2013 Version: 1.2 8. PACKAGE/PAD LOCATIONS 8.1. Ordering Information Product Number Package Type GPL811P08A -NnnV - C Chip form GPL811P04A -NnnV - C Chip form GPL811P08A -NnnV – QL09X Halogen Free 128 pin LQFP Package GPL811P04A -NnnV – QL09X Halogen Free 128 pin LQFP Package Note1: Code number (NnnV) is assigned for customer. Note2: Code number (N = A-Z or 0-9, nn=00-99); version (V = A - Z) Note3: Package form number (X = 0-9, serial number) 8.2. Package Information 8.2.1. LQFP 128L outline dimensions
© Generalplus Technology Inc. Proprietary & Confidential 14 Sep. 11, 2013 Version: 1.2 Millimeter Symbol Min. Nom. Max. A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 D 16.00 BSC. D1 14.00 BSC. E 16.00 BSC. E1 14.00 BSC. e 0.40 BSC. θ 0° 3.5° 7° b 0.13 0.16 0.23 c 0.09 - 0.20 L 0.45 0.60 0.75 L1 1.00 REF
© Generalplus Technology Inc. Proprietary & Confidential 15 Sep. 11, 2013 Version: 1.2 9. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 16 Sep. 11, 2013 Version: 1.2 10. REVISION HISTORY Date Revision # Description Page Sep. 11, 2013 1.2 Modify Frame rate at 1/9 & 1/11 duty; 8 Jul. 10, 2013 1.1 Modify 4.2 PIN Map 6 Sep. 26, 2012 1.0 1. DC characteristics updated; 2. Package information added; P4,P11 P6,P13 Feb. 6, 2012 0.1 Original 15