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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPLL119911CC
1024 Dots LCD Controller/Driver
Mar. 08, 2010 Version 1.1 In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 Mar. 08, 2010 Version: 1.1 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 Mar. 08, 2010 Version: 1.1
- GENERAL DESCRIPTION The GPL191C is an 8-bit CMOS microprocessor featuring 704 bytes working RAM, 256K bytes ROM, 12 I/Os, interrupt/wakeup controller, UART for serial communication, and automatic display controller/driver for LCD. It has one PWM driver with two audio channel outputs. Attractive sound effects can easily be generated. Its large ROM area can be used to store both program and audio data (speech duration is approx. 80 seconds at a 6KHz sampling rate using 4-bit ADPCM). The built-in UART speeds up data transmission between two chips. Furthermore, a SLEEP (power-down) feature is also built-in to reduce power consumption. The GPL191C is designed with state-of-the-art technology to fulfill LCD application requirements, especially hand-held products. 2. FEATURES Built-in 8-bit processor ─ 704 bytes SRAM ─ 256K bytes ROM ─ Max. Operating Speed: 4.0MHz @ 2.4V ─ CPU clock is software programmable, can be 1/2, 1/4, 1/8 or 1/16 R-oscillator clock frequency ─ Key wake-up function ─ Provides 8 interrupt sources Asynchronous serial interface (UART) ─ Supports bit rate up to 115.2 Kbps Programmable LCD Driver ─ Up to 64 segments, up to 16 commons, maximum 1024 dots ─ 1/4 or 1/5 bias capability ─ 1/8, 1/12 or 1/16 duty ─ 128 bytes dedicated LCD RAM ─ Built-in voltage doubler and voltage regulator to generate VLCD for LCD driver ─ 16-level VLCD adjustable Power saving SLEEP mode (wakeup source: key input, 2Hz, 16Hz, and timer) Low Voltage Detector ─ 2.6V and 2.4V detection Wide Operating Voltage: ─ 2.4V - 3.6V ─ 3.6V - 5.5V Peripherals ─ 12 I/O pins shared with LCD segments (mask option) ─ 4 I/O pins (IOEF3 - 0) ─ Extra 2 general I/O pins (IOEF5 - 4) or 2 UART pins (TXD - RXD) (mask option) ─ Extra 2 I/O pins (IOEF7 - 6) if LCD is 1/8 or 1/12 duty (mask option) ─ Built-in 32.768KHz oscillator circuit for real time clock Function ─ Built-in R-oscillator (only one resistor required) ─ Internal time base generator ─ Two 16-bit reloadable timer/counters (TM0 & TM1) ─ 2-channel of 8-bit audio decoders ─ One PWM output (can drive speaker or buzzer directly) ─ Watchdog Timer for reliable operation Low-power consumption 3. APPICATION FIELD Handheld Games Scientific Calculator Talking Calculator, Talking Clock Talking Instrument Controller General Speech Synthesizer Data Bank
© Generalplus Technology Inc. Proprietary & Confidential 4 Mar. 08, 2010 Version: 1.1 4. BLOCK DIAGRAM PROCESSOR OSC GEN TIME BASE INTERRUPT LOGIC 256K BYTES ROM
704 BYTES
P O R T P W M
128 Bytes LCD
64 SEGMENTS x 16 COMMONS LCD DRIVER
IOEF3-0 ( I/O) AUDP AUDN TxD/IOEF4 RxD/IOEF5 COM15-0 SEG51-0 SEG59-52/IOAB7-0 SEG63-60/IOCD3-0 REGULATOR DOUBLER Watchdog Timer VOLTAGE DETECTOR U A R T 52 8 4 8-BIT MICRO Note1: IOAB7 - 0 can be enabled by mask option from Segment 59 - 52. Each I/O (segment) can be mask optioned individually. Note2: IOCD3 - 0 can be applied as segment 63 - 60 by mask option. Each I/O corresponds to one segment. Note3: Common 15 - 12 can be optioned to IOEF7 - 6 when LCD driving type is selected as 1/8 duty or 1/12 duty. Note4: TxD and RxD can be optioned to IOEF5 - 4 when UART is not used.
© Generalplus Technology Inc. Proprietary & Confidential 5 Mar. 08, 2010 Version: 1.1 5. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description SEG3 - 0 SEG51 - 4 SEG63 - 52 4 - 1 54 - 101 37 - 48 O LCD driver segment output. SEG59 - 52 can be re-assigned as IOAB7 - 0 bi-directional I/O ports. Also , SEG60 - 63 can be re-assigned as IOCD0 - 3 bi-directional I/O port. (mask option) COM13 - 0 COM15 - 14 18 - 5 29 - 30 O LCD driver common output. COM15 - 14 can be re-assigned as IOEF7 - 6 bi-directional I/O port. (mask option) IOEF3 - 0 33 - 36 I/O Port EF is a bi-directional I/O port, can be software programmed as wake up I/O. RxD 31 I UART input. Can be optioned to IOEF5. TxD 32 O UART output. Can be optioned to IOEF4. ROSC 28 I ROSC input, connect to VDD through a resistor. RESET 22 I System reset input, low active. AUDP AUDN O PWM audio output. X32I 25 I 32.768KHz crystal input or connects to VDD through a resistor. (option) X32O 24 O 32.768KHz crystal output. TEST 23 I Test input VLCD 26 P LCD voltage. Connect to VSS through a capacitor if voltage doubler is enabled. HVLCD 21 P LCD voltage generation. Connect to VSS through a capacitor if voltage regulator is enabled. CUP1 CUP2 P LCD voltage generation. Charge pump capacitor interconnection pins. VDD 27 P Power supply voltage input. VSS 53 P Ground reference. PVDD 49 P PWM driver power. PVSS 52 P PWM driver ground reference. Legend: I = Input, O = Output, P = Power
© Generalplus Technology Inc. Proprietary & Confidential 6 Mar. 08, 2010 Version: 1.1 5.1. PAD Assignment GPL191C This IC substrate should be connected to VSS or floated Note1: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc. Proprietary & Confidential 7 Mar. 08, 2010 Version: 1.1 6. FUNCTIONAL DESCRIPTIONS 6.1. ROM Area The GPL191C is a large ROM based micro-controller with 1024 dots LCD driver. The large ROM can be defined as program ROM, LCD fonts and audio data continuously without any limitation. To access ROM, users should program the Bank Select register, choose bank, and then access bank address to fetch data. 6.2. Map of Memory and I/Os *I/O PORT: *NMI SOURCE: *INT SOURCE: - INT1 ( from TIMER 1 ) - I/O AB_CTRL $0001 - PORT IOAB $0002 - PORT IOEF $0004 - PORT IOCD $0003 - I/O CD_CTRL $0000 - I/O EF_CTRL $0006 - INT0 ( from TIMER 0 ) - INT1 ( from TIMER 1 ) - 2 K H z - T2 Hz ( 2Hz / 1 Hz) - T16 Hz ( 4Hz/8Hz/16Hz/32Hz ) - 128 Hz - EXT INT ( from IOCD1 pin ) - UART *MEMORY MAP H/W registers , I/Os $00000 WORKING SRAM (192 bytes) $0003F $00040 GENERALPLUS TEST PROGRAM $000FF $00400 USER's PROGRAM DATA AREA SRAM for STACK and Data Storage (512 bytes) $00100 $002FF $007FF $00800 $07FFF $08000 ROM BANK #1$0FFFF $10000 ROM BANK #2$17FFF $18000 ROM BANK #3$1FFFF $20000 ROM BANK #4$27FFF $28000 ROM BANK #5 $2FFFF ROM BANK #0 $00300 LCD Buffer (128 bytes) $0037F ROM BANK #6$30000 ROM BANK #7 $37FFF $38000 $3FFFF Note: $7FFA - $7FFF in ROM bank#0, and $FFFA - $FFFF in bank#1 – 7 are reserved for reset vectors. $7FF2 - $7FF7 in bank#0, and $FFF2 - $FFF7 in bank#1 – 7 are reserved for GENERALPLUS testing. 6.3. Operating States The GPL191C supports three operating states: standby, halt, and operating. Following table shows the differences between the three operating states. Operating Halt Standby CPU ON OFF OFF 32768 oscillator ON ON OFF LCD driver ON ON/OFF OFF In the operating state, all modules (CPU, 32768Hz oscillator, timer/counter, LCD drive, etc.) are activated. The halt/standby state is entered by writing to the SLEEP register. There are four wake-up sources in GPL191C: port IOEF wake-up, Timer0 wake-up, 4Hz/ 8Hz/ 16Hz/ 32Hz wake-up and 2Hz/ 1Hz wake-up. If any wake-up event occurs, execution of the next instruction continues in the operating state. When in standby, all modules are shut down, and RAM and I/Os remain in their previous stat es. Current consumption is minimized in standby. By writing to the SLEEP register while the 32768Hz oscillator running, the system is in halt state. In halt state, CPU clock is halted while it waits for an event (key press, timer overflow) to generate a wake-up. The 32768 related modules (timer/counter, LCD drive, etc.) may remain active in the halt state. The following figure is the GPL191C state diagram. HALT OPERATING STANDBY Write to SLEEP register, 32768 oscillator OFF Wake-up or user resetWrite to SLEEP r egister, 32768 oscillator ON Wake-up or user reset GPL191C State Diagram 6.4. Speech and Melody Since the GPL191C provides large ROM and wide range of CPU operating speed, it is very suitable for speech and melody synthesis. For speech synthesi s, GPL191C provides several timer interrupts for precise sampling frequency. Users can record or synthesize the sound and digitize it into the ROM. The sound then can be played back in the sequence assigned by the users’ programs. Several algorithms are recommended for high fidelity and good compression of sound: such as PCM and ADPCM. For melody synthesis, the GPL191C provides a dual tone mode. Once in the dual tone mode, users need only to program the tone frequency for each channel by writing to the timer/counter TM0 and TM1, and set the envelope for each channel. The hardware will toggle the tone wave automatically.
© Generalplus Technology Inc. Proprietary & Confidential 8 Mar. 08, 2010 Version: 1.1 6.5. LCD Controller/Driver GPL191C contains a 1024-dot LCD driver. Programmers can set the LCD configuration (bias, duty, voltage doubler) by writing to LCD control register ($20). Once the LCD configuration is initialized, the desired pattern can be displayed by filling the LCD buffer with appropriate data. The LCD driver can also operate during sleep by keeping 32768Hz o scillator running. The LCD driver in GPL191C is designed to fi t most LCD specifications. It can either be programmed as 1/4 or 1/5 bias and the duty is also programmable as 1/8, 1/12, or 1/16 duty. 6.6. Voltage Doubler/Regulator The GPL191C also contains a built-in voltage doubler and a voltage regulator. The voltage regulator provides a reference voltage (HVLCD) for the voltage doubler to generate VLCD (by charge-pumping). Users can get desired VLCD by changing the output reference voltage (writing to register) of the voltage regulator. By enabling the voltage doubler and regulator, users can get a stable VLCD that will not be affected by VDD. The three possible configurations of voltage doubler and regulator are shown in the following table: Regulator Doubler VLCD OFF OFF VDD (not regulated) OFF ON 2*VDD (not regulated) ON OFF N/A ON ON Adjustable Note that when voltage regulator and voltage doubler are enabled, VDD should be lower than V LCD-0.5V to prevent forward biasing the p-n junction of I/O’s output PMOS. 6.7. PWM Output Internally, the GPL191C has one PWM output with two sound channels. Each channel can be set to play speech or tone individually. GPL191C uses Puls e Width Modulation that could directly drive speaker or buzzer without any buffer or amplification circuit. 6.8. Asynchronous Serial Interface (UART) The GPL191C supports a 1-channel UART for serial communications. It supports bit rates up to 115.2kbps. UART operation is controlled by UART command registers. Configurations such as Tx/Rx interrupt, parity check, parity even/odd and clock source can be set in command registers. Two interrupts are generated by Rx and Tx. The Rx or Tx interrupt activates when a byte is received or transmitted. By reading the status register, users can tell whether the interrupt is generated by Rx or Tx. Framing, overrun and parity errors are detected as each byte is received. All error status can be read from status register. The UART supports clock auto calibration. If this clocking scheme is selected, standard baud rates from 1.2kbps to 115.2kbps are available. The baud rate is selected by writing to baud rate control registers. The supported standard baud rates and their minimum R-oscillator clock frequency required are shown in the following table: Baud Rate(bps) Min. Frosc(Hz) 1200 24000 2400 48000 4800 96000 9600 192000 19200 384000 38400 768000 51200 1024000 57600 1152000 102400 2048000 115200 2304000 If the auto calibration clocking scheme is not selected, users can get desired baud rates by writing appropriate values to pre-scalar registers. Non-standard baud rates can be obtained this way. When using the non-calibration mode, one should be aware that the frequency of R-oscillator may alter due to manufacturing process variations, supply voltage, operating temperature and tolerance of external R components used. 6.9. Low Voltage Detection The GPL191C provides a 2.6V/2.4V voltage detector to detect a low voltage event. Users can turn on 2.6V detection and read bit1 of the port periodically to monitor whether VDD is lower than 2.6V. In addition, if 2.4V detection is turned on and VDD drops below 2.4V, after a SLEEP command is issued, system will shut down all activities (LCD bias, LCD display, 32768Hz oscillator) and enters standby mode to reduce current consumption. This low voltage power-down can be awakened by a PEF0 key change or RESET. Users can use this feature to implement the low battery check/battery change function. OPERATING STANDBY VDD < 2.4V and SLEEP Port EF0 Key wake-up or user reset State Diagram of Low Voltage Power Down
© Generalplus Technology Inc. Proprietary & Confidential 9 Mar. 08, 2010 Version: 1.1 6.10. Watchdog Timer (WDT) An on-chip watchdog timer is available in the GPL191C. The WDT is designed for recovering the system from abnormal operation. If the system is stalled, the WDT will generate a system reset to restart system after one second. If WDT is enabled, the WDT should be cleared every 0.5 seconds to avoid accidental reset. The WDT can be cleared by writing to WDT clear register. Note that the WDT only works when 32768 Hz clock is available. 6.11. Mask Options 6.11.1. 32768Hz oscillator 1). X’TAL 2). R-oscillator 6.11.2. Watchdog timer 1). Enable 2). Disable 6.11.3. TxD/RxD select 1). TxD as UART transmit output, RxD as UART receive input 2). TxD as I/O port EF4, RxD as I/O port EF5 6.11.4. Port EF bit7 – 0 with 600K, Pull-Low Each bit can be optioned to Enable/Disable individually. 6.11.5. I/O and LCD driver Some examples are shown below: Dots Segment Common Input/Output Input/Output Input/Output 1024 64 16 4 IOEF3 – 0 - - 960 60 16 4 IOEF3 – 0 4 IOCD3 – 0 - 832 52 16 4 IOEF3 – 0 4 IOCD3 – 0 8 IOAB7 – 0 768 64 12 8 IOEF3 – 0 - - Each input/output port, IOAB7 – 0 and IOCD3 – 0, can be optioned to LCD segments independently, and LCD commons (COM15 – 12) can be optioned to IOEF7 – 6 when LCD mode is 1/8 duty or 1/12 duty. If UART is not used, 2 more I/O ports (TxD/IOEF4, RxD/IOEF5) can be used.
© Generalplus Technology Inc. Proprietary & Confidential 10 Mar. 08, 2010 Version: 1.1 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating ta ble may cause operational errors or damage to the device. For no rmal operational conditions see AC/DC Electrical Characteristics. 7.2. DC Characteristics Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition 2.4 - 3.6 V For 2-battery Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 650 - μA FOSC = 4.0MHz, F CPU = 1.0MHz @ 3.0V, no load Standby Current ISTBY - - 1.0 μA VDD = 3.0V, ALL OFF Halt Current IHALT - 16 - μA VDD = 3.0V, 32K X’tal ON, LCD ON, VLCD = 4.8V, no LCD panel - -60 - mA VDD = 3.0V, VOH = 2.5V Audio Output Current IOH - -115 - mA VDD = 3.0V, VOH = 2.0V - 75 - mA VDD = 3.0V, VOL = 0.5V Audio Output Current IOL - 145 - mA VDD = 3.0V, VOL = 1.0V VLCD Variation VLCD_VAR - ±0.2 - V VDD = 2.4V – 5.4V, VLCD = 4.8V No LCD panel applied Low Voltage Detection Level VLV26 2.50 2.60 2.70 V - Voltage difference of 2.6V and 2.4V detection level VDIF 0.1 - - V - Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output High Current (I/O) IOH - -3.3 - mA VDD = 3.0V, VOH = 2.4V Output Sink Current (I/O) IOL - 10.0 - mA VDD = 3.0V, VOL = 0.8V CPU Clock FCPU - - 4.0 MHz FCPU = FOSC/2 @ 2.4V Note1: VLCD variation is subject to change due to the variation of process, temperature, supply voltage and loadings. Note2: When voltage regulator and voltage doubler are enabled, VDD should be lower than VLCD-0.5V to prevent forward biasing the p-n j unction of I/O’s output PMOS.
© Generalplus Technology Inc. Proprietary & Confidential 11 Mar. 08, 2010 Version: 1.1 7.3. The Relationship between the ROSC and the FOSC Rosc v.s. Fosc 0 50 100 150 200 250 300 350 Rosc(Kohm) Fosc(MHz) Rosc v.s. Fosc 0 50 100 150 200 250 300 350 Rosc(Kohm) Fosc(MHz) 7.4. The Relationship between the R32K and the F32K R32K v.s. F32K 100 0 500 1000 1500 2000 2500 R32K(Kohm) F32K(KHz) R32K v.s. F32K 100 0 500 1000 1500 2000 2500 R32K(Kohm) F32K(KHz) 7.5. The Relationship between the VDD and the Frequency 7.5.1. VDD vs. FOSC @ROSC=59kohm, TA = 25℃ VDD v.s. Fosc 7.4 7.6 7.8 8.2 8.4 8.6 0123456 VDD(V) Fosc(MHz) 7.5.2. VDD vs. F32k@R32K=820Kohm, TA = 25℃ VDD v.s. F32K 0123456 VDD(V) F32K(KHz)
© Generalplus Technology Inc. Proprietary & Confidential 12 Mar. 08, 2010 Version: 1.1 8. APPLICATION CIRCUITS 8.1. 960 Points LCD Driver, 60 Segments × 16 Commons Note1: IOEF4, IOEF5 are shared with TxD, RxD(UART), if UART is not used, these two pins can be used as I/O ports Note2: These capacitors must be connected if voltage doubler and voltage regulator are used. Note3: Wire route path from capacitors (C6 – 1) to chip should be as close as possible. Note4: If voltage doubler and voltage regulator are not used, VLCD should be connected to VDD. Note5: C7, C8 and crystal should be placed as close as possible to X32I and X32O. A shielding by ground is suggested. Note6: The value of C7 and C8 are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note7: The capacitor value of C1 is from 30pF to 200pF, according to system noise level.
© Generalplus Technology Inc. Proprietary & Confidential 13 Mar. 08, 2010 Version: 1.1 8.2. 1024 Points LCD Driver, 64 Segments × 16 Commons Note1: IOCD3 – 0 can be mask-option for segment 63 – 60. Note2: These capacitors must be connected if voltage doubler and voltage regulator are used. Note3: Wire route path from capacitors (C6 – 1) to chip should be as close as possible. Note4: If voltage doubler and voltage regulator are not used, VLCD should be connected to VDD. Note5: C7, C8 and crystal should be placed as close as possible to X32I and X32O. A shielding by ground is suggested. Note6: The value of C7 and C8 are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note7: The capacitor value of C1 is from 30pF to 200pF, according to system noise level.
© Generalplus Technology Inc. Proprietary & Confidential 14 Mar. 08, 2010 Version: 1.1 8.3. LCD in 1/8 Duty or 1/12 Duty, IOAB7 – 0, IOCD3 – 0, IOEF5 – 0 Note1: SEG59 – 52 can be mask-option for IOAB7 – 0. TxD and RxD can be used for IOEF4, IOEF5 when UART is not used. Note2: These capacitors must be connected if voltage doubler and voltage regulator are used. Note3: Wire route path from capacitors (C6 – 1) to chip should be as close as possible. Note4: If voltage doubler and voltage regulator are not used, VLCD should be connected to VDD. Note5: C7, C8 and crystal should be placed as close as possible to X32I and X32O. A shielding by ground is suggested. Note6: The value of C7 and C8 are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note7: The capacitor value of C1 is from 30pF to 200pF according to system noise level.
© Generalplus Technology Inc. Proprietary & Confidential 15 Mar. 08, 2010 Version: 1.1 8.4. 32K Frequency Option Connection 8.4.1. Crystal option X32I X32O 8.4.2. External resistor option 8.5. Serial Communications between two GPL191Cs 8.6. Power-Ground Layout Illustration Note1: PVDD and VDD are branched from the power source. Do not connect in series. Note2: PVSS and VSS are branched from the power source. Do not connect in series.
© Generalplus Technology Inc. Proprietary & Confidential 16 Mar. 08, 2010 Version: 1.1 9. PACKAGE/PAD LOCATIONS 9.1. Ordering Information Product Number Package Type GPL191C-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A – Z or 0 – 9, nn = 00 – 99); version (V = A – Z).
© Generalplus Technology Inc. Proprietary & Confidential 17 Mar. 08, 2010 Version: 1.1 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 18 Mar. 08, 2010 Version: 1.1 11. REVISION HISTORY Date Revision # Description Page Mar. 08, 2010 1.1 1. Modify 1.GENERAL DESCRIPTION. 2. Modify 2.FEATURES. 3. Modify 6.7. PWM Output. May 15, 2009 1.0 1. Add chapter 7. ELECTRICAL SPECIFICATIONS. 2. Modify chapter 8. APPLICATION CIRCUITS. 10-16 Nov. 11, 2008 0.1 Preliminary version 18