GPL15B1 GENERALPLUS | Alldatasheet
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72KB LCD CONTROLLER/DRIVER 1. GENERAL DESCRIPTION The GPL15B1 is a C MOS 8-bit single chip microprocessor which contains RAM, ROM, I/Os, inter rupt cont roller, 8 -bit PWM audio output and automatic display controller/driver for LCD. For power saving, a sof tware controllable st andby sw itch is also built-in. This chip is implemented with advanced design and process technology. It is ver y suit able f or LCD t ype ha ndheld product s. The R OM sp ace of this chip can be used to store prog ram o r audio dat a. (T he speech dat a is about 18 se conds at 7KHz sampling rate by using 4bit-ADPCM) 2. BLOCK DIAGRAM 8-BIT RISC PROCESSOR OSC GEN TIME BASE INTERRUPT LOGIC 72K BYTES ROM
128 BYTES
P O R T P W M
24 SEGMENTS X 4 COMMONS LCD DRIVER
(INPUT) IOCD3 - 0 (I/O) IOAB1 - 0 (I/O) X32OX32IROSC 3. FEATURES Built-in 8-bit CPU 128 bytes SRAM 72K bytes ROM Max. CPU frequency: 2.0MHz @ 3.0V Wide operating voltage: 2.4V - 3.6V 3.6V - 5.5V Built-in 32.768KHz oscillator circuit for real time clock Built-in RC oscillator(only one resistor is needed) Internal time base generator Key wake-up mode Provide 7 INT sources Operating current: 400µA/600KHz @ 3.0V Very low standby current, ISTBY < 1µA 24 segments x 4 commons LCD driver LCD 1/2, 1/3 bias, 1/2, 1/3, 1/4 duty Two 12-bit timers 6 general I/O pins, 6 input pins Provide standby function (stop osc) Built-in 8-bit PWM output (directly drive a speaker) Note: Patent Circuit Included. Tawain Patent No. 68824. © Generalplus Technology Inc. Proprietary & Confidential 1 MAR. 23, 2005 Version: 1.0
- SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description SEG23 - 0 36 - 13 O LCD driver segment output COM3 - 0 37 - 40 O LCD driver common output IOAB1 - 0 12 - 11 I/O I/O port IOEF5 - 0 1 - 6 I INPUT port (also for key wake-up input) IOCD3 - 0 10 - 7 I/O I/O port ROSC 49 I R-osc input, connect to VDD through resistor RESET 50 I System reset input AUDP 52 O PWM Audio output AUDN 54 O PWM Audio output X32I 48 I 32.768KHz crystal input (provide LCD frequency) X32O 47 O 32.768KHz crystal output TEST 46 I Test input VDD 42, 53 I Positive supply voltage input VSS 51 I Ground input VDD1, VDD2 43, 41 I Inputs for setting LCD bias CUP1, CUP2 44, 45 I Inputs for setting LCD bias © Generalplus Technology Inc. Proprietary & Confidential 2 MAR. 23, 2005 Version: 1.0
- FUNCTIONAL DESCRIPTIONS 5.1. ROM Area GPL15B1 is a large R OM b ased micro-controller with 96 segments LCD driver . The l arge R OM can be defined as program ROM, LCD font and audio dat a continuously without any limitation. T o a ccess the ROM area, user should program the BANK SELECT register ($07) fir st, then access the bank #1 or bank #2 b y addressing the highe r bank address ($8000 - $FFFF) to fetch the data. 5.2. Stop Clock Mode GPL15B1 sup ports a po wer saving mode for t hose application s needing ver y low standby current. The user simply enables th e wake-up sour ces to stop the CPU clock by writing the ST OP CLOCK register($09). Thus CP U will go to st andby mode and the RAM and I/ O remain in their pr evious st ate until awakened. There are t hree sources of wake-up in this chip, PO RT IO EF wake-up, TIMER 0 wake up and 2 Hz wake up. After the chip is awakened, th e i nternal CP U will go to the RES ET st ate. The RAM and I/O are not affected by this wake-up reset. 5.3. Map of Memory and I/Os H/W REGISTER, I/Os USER RAM and STACK UNUSED GENERALPLUS TEST PROGRAM USER'S PROGRAM DATA AREA ROM BANK UNUSED ROM BANK #2 *MEMORY MAP (ROM view) $00000 $00080 $00200 $00600 $08000 $16000 $17FFF $00100 *I/O PORT: ─ PORT IOAB $0002 IOCD $0003 IOEF $0004 ─ I/O CONFIG $0000 *NMI SOURCE: ─ INT1 (from TIMER 1) *INT SOURCE ─ INT0 (from TIMER 0) ─ INT1 (from TIMER 1) ─ 2KHz ─ LCDL (1/3, 1/4 duty 256Hz; 1/2 duty 128Hz) ─ 128Hz ─ EXT INT ─ 2Hz ROM BANK #1 $10000 $15FFF $0FFFF 5.4. Timer/Counter GPL15B1 cont ains tw o 12-bit timer/counters, TM0 and TM1 respectively. In the timer mode , TMA and TMB are reloadable up-counters. When the timer overflo ws from 0F FF to 0000, the carry signal will generate the IN T signal if the corresponding bit i s enabled in INT ENABLE register ($0d). The timer will auto reload to the user’s preset value and up-count again. If TM0 is specified as a counter , th e user can rese t the counter b y loading 0 into register $14 and $1C. After the counter is activated, the count value can also be read f rom ab ove registers on-the-fl y and th e read instruction will not affect the counter's value or reset it. The clock sour ce of the time r/counter are s elected as the following: Timer/Counter Addr. Clock Source
12 BIT TIMER
$0014 $001C CPU CLOCK (T) or T/4 TM0
12 BIT COUNTER
$0014 $001C T/128, T/256, T/2048 or EXT CLK MODE SELECT REGISTER $000B Select TM0 timer or counter TIMER CLOCK SELECTOR $001C Select T or T/4 5.5. Speech and Melody Since GPL15B1 could provide large R OM size and wide CPU operation speed , it is most suitable for speech and melod y synthesis. For speech synthesis, this chip could provide I NT for precise sampling frequency. Users may record or synthesize the sound and digitize it into the RO M. The sound could be play ed back in the sequence of the cont rol functions as designed b y the internal user's program. Several algorithms are suggested to be used for the hig h fidelity and go od compression of sound: PCM, LOG PCM, DM and ADPCM. For melod y s ynthesis, GPL15B1 provides dual tone mode, once ent ered the dual tone mode, users mere only program the TM0 and TM1 to tone f requency for each channel, count the envelope of each channel, and the hard ware may to ggle the tone wave aut omatically without using INT t o handle it. © Generalplus Technology Inc. Proprietary & Confidential 3 MAR. 23, 2005 Version: 1.0
5.6. LCD Controller GPL15B1 contains a tot al of 96 segments of LCD controller and drivers. In nor mal operation, t he LCD is ref reshed b y L CDL interrupt. The INT routine will read the number of common patterns which are under servi ce, and send the next common pattern to the L CD port ($10 H - $13H) from the RAM buf fer. In stop clock mode, the hardware will auto ref resh the LCD after writing to OPT ION register ($1 FH). The LCD d river is designed to fit most LCD specificat ions in GPL15B1: It can either be programmed as 1/2 or 1/3 bias, The dut y is also programma ble from 1/2, 1/3 or 1/4 duty. 5.7. PWM Output Internally, GPL15B1 has tw o se t PWMs (one for each channel). GPL15B1 uses Pulse Wid th Modulation could directly drive speaker or buzzer without any buffer or AMP circuit. © Generalplus Technology Inc. Proprietary & Confidential 4 MAR. 23, 2005 Version: 1.0
- ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition 2.4 - 3.6 V For 2-battery Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 400 - µA FCPU = 1.2MHz @ 3.0V, no load Standby Current ISTBY - - 1.0 µA VDD = 3.0V, 32768Hz OFF OSC Frequency FOSC2 - - 4.0 MHz VDD = 3.0V IOH - -16 - mA VDD = 3.0V Audio Output Current IOL - 24 - mA VDD = 3.0V Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output High I (I/O) IOH -200 - - µA VOH = 2.4V Output Sink I (I/O) IOL 500 - - µA VOL = 0.8V Input Resistor RIN - 50 - KΩ For input only OSC Resistor ROSC - 150 - KΩ FOSC = 1.2MHz @ 3.0V CPU Clock FCPU - - 2.0 MHz FCPU = FOSC/2 @ 3.0V 6.3. The Relationship between the ROSC and the FCPU 0.0 0.5 1.0 1.5 2.0 0 200 400 600 800 Rosc ( Kohms ) FCPU ( MHz ) 0.0 0.5 1.0 1.5 2.0 0 200 400 600 800 Rosc ( Kohms ) FCPU ( MHz ) © Generalplus Technology Inc. Proprietary & Confidential 5 MAR. 23, 2005 Version: 1.0
- APPLICATION CIRCUITS 7.1. Application Circuit GPL15B1 CUP2 CUP1 VDD1 VDD VDD2 COM0 COM1 COM2 COM3 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 IOEF5 IOEF4 IOEF3 IOEF2 IOEF1 IOEF0 IOCD0 IOCD1 IOCD2 IOCD3 IOAB0 IOAB1 SEG0 SEG1 SEG2 SEG3 AUDN VDD AUDP VSS RESET ROSC X32I X32O TEST SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 IO DEVICE LCD Module VDD Input I / O 20p 20p 32768Hz Rosc Common Segment Bias option 1/2 Bias VDD1 VDD2 CUP1 CUP2 0.1µF 1/3 Bias VDD1 VDD2 CUP1 CUP2 0.01µF VDD 0.01µF 0.01µF COMs [ 3:0 ] SEGs [ 23:0 ] VDD RESET 0.1µF 0.1µF Bias option VDD VDD 0.1µF100µF Note : The capacitors ( 0.1 µF , 100 µF ) between VDD and VSS should be placed with GPL15B's VDD and VSS as near as possible . © Generalplus Technology Inc. Proprietary & Confidential 6 MAR. 23, 2005 Version: 1.0
7.2. Audio Driver/Amplifier for PWM Mode AUDN AUDP LM386 Power AUDN AUDP 4.7K 2.7K 8050 47K 0.001µF 20K 0.1µF 220µF © Generalplus Technology Inc. Proprietary & Confidential 7 MAR. 23, 2005 Version: 1.0
- PACKAGE/PAD LOCATIONS 8.1. PAD Assignment This IC substrate should be connected to VSS Note1: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 8.2. Ordering Information Product Number Package Type GPL15B1-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). © Generalplus Technology Inc. Proprietary & Confidential 8 MAR. 23, 2005 Version: 1.0
8.3. PAD Assignment PAD No. PAD Name X Y PAD No. PAD Name X Y
1 IOEF5 -981 905 28 SEG15 569 -1061
2 IOEF4 -981 768 29 SEG16 699 -1061
3 IOEF3 -981 630 30 SEG17 837 -1060
4 IOEF2 -981 494 31 SEG18 975 -1060
5 IOEF1 -980 361 32 SEG19 974 -924
6 IOEF0 -981 235 33 SEG20 974 -787
7 IOCD0 -982 108 34 SEG21 974 -654
8 IOCD1 -980 -20 35 SEG22 973 -527
9 IOCD2 -980 -146 36 SEG23 974 -400
10 IOCD3 -980 -274 37 COM3 974 -273
11 IOAB0 -981 -401 38 COM2 974 -146
12 IOAB1 -981 -528 39 COM1 974 -19
13 SEG0 -980 -655 40 COM0 974 108
14 SEG1 -981 -787 41 VDD2 974 235
15 SEG2 -981 -923 42 VDD 974 361
16 SEG3 -981 -1060 43 VDD1 973 489
17 SEG4 -843 -1061 44 CUP1 974 614
18 SEG5 -706 -1060 45 CUP2 974 747
19 SEG6 -575 -1061 46 TEST 974 885
20 SEG7 -448 -1060 47 X32O 912 1052
21 SEG8 -320 -1060 48 X32I 705 1052
22 SEG9 -193 -1060 49 ROSC 498 1051
23 SEG10 -67 -1060 50 RESET 257 1052
24 SEG11 60 -1060 51 VSS 125 1051
25 SEG12 187 -1061 52 AUDP -170 1052
26 SEG13 315 -1061 53 VDD -564 1051
27 SEG14 441 -1060 54 AUDN -980 1052
© Generalplus Technology Inc. Proprietary & Confidential 9 MAR. 23, 2005 Version: 1.0
- DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuit s sold b y Generalplus Technology a re covered by the warranty a nd patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, e xpress, st atutory implied or b y descrip tion rega rding th e information in this publication or regarding the free dom of t he described chip(s) from p atent infringement. FUR THERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specification s and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet s and othe r information in thi s publication are current before placing orders. Products described her ein are intended fo r use in normal co mmercial applications. A pplications in volving unusual environment al or reliabil ity requirements, e.g. milit ary e quipment o r medical lif e su pport equipment, are s pecifically not re commended without additional proc essing by GENERALPLUS for such applicat ions. Please note that application circuits illustrated in this document are for reference purposes only. © Generalplus Technology Inc. Proprietary & Confidential 10 MAR. 23, 2005 Version: 1.0
- REVISION HISTORY Date Revision # Description Page MAR. 23, 2005 1.0 Original Note: The GPL15B1 data sheet v1.0 is a continued version of SPL15B1 data sheet v1.2. © Generalplus Technology Inc. Proprietary & Confidential 11 MAR. 23, 2005 Version: 1.0