GPL12A-NnnV-HL04x | DigiCamel IC Datasheet

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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENE RALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus. Jul. 27, 2011 Version 1.4 GGPPLL1122AA 88KK BByytteess MMiiccrroo--ccoonnttrroolllleerr wwiitthh LLCCDD DDrriivveerr

© Generalplus Technology Inc. Proprietary & Confidential 3 Jul. 27, 2011 Version: 1.4 8K BYTES MICRO-CONTROLLER WITH LCD DRIVER 1. GENERAL DESCRIPTION Generalplus GPL12A is the mask-version of GPL11B(OTP) which features a CMOS 8-bit single ch ip Micro-controller containing LCD drivers, 8K bytes ROM, SRAM, I/O, timer/counter, PLL/ROSC, audio/remote control out, and resistor to frequency converter (RFC) function, all in one chip. The GPL12A is designed to drive LCD directly and to perform sophisticated functions as well as complex arithmetic. With the on-chip crystal oscillator, the real-time clock can be easily approached. For power savings, several power-down modes are controllable by software. The GPL12A is widely used for low power electronic products, e.g. remote controller and general-purpose LCD controller. 2. FEATURES Built-in Generalplus 8-bit CPU - 128 bytes SRAM - 8K bytes ROM - Working Voltage: 1.9V - 5.5V - Maximum CPU speed: 4.0MHz @ 2.7V ~ 5.5V 2.5MHz @ 1.9V ~ 3.6V - CPU Clock can be switched between High-Speed clock (PLL / R-oscillator) divided by 2 / 4 / 8 / 16 or Low-speed clock (32768Hz Crystal-oscillator / 32768Hz R-oscillator) - Watchdog timer and illegal address reset circuit are always enabled and will reset CPU if these events occur. - Eight wake-up sources (37.9K/N, 32768/N, TMO, EXT1, EXT2, T2Hz, KEYC, NMI) - Eight interrupt sources Dual clock sources: - Dual clock sources controlled by two clock mask options - High-speed clock sources: PLL/R-oscillator - Low-speed clock sources: 32768 Crystal / 32768 R-oscillator - PLL clock = 4.85MHz - IR carrier frequency = 37.9KHz - Maximum system clock in PLL clock mode = 2.42MHz Programmable LCD driver - 48-byte Dual-port SRAM for LCD buffers - LCD has 1/2 bias, 1/3 bias, 1/4 bias selections - Maximum LCD 12x30 (360 dots), 11x30 (330 dots), 10x30 (300 dots), 9x32 (288 dots), 8x32 (256 dots), 5x32 (160 dots), 4x32 (128 dots), 3x32 (96 dots) A 16-bit re-loadable timer/counter Low voltage reset level is at 2.2V/1.9V and can be disable by Mask-option Four Operating modes: Operating / WAIT / HALT /STANDBY - Interrupt will wake CPU up - Wakeup from CPU reset or next instruction is programmable. Built-in RFC (Resistor to Frequency Converter) function I/O Port definition - 8 IOA, 4 shared pins with LCD Commons / Segments - 8 Inputs (INB) with key wakeup function 5 shared pins with LCD Commons / Segments / V3 / CUP3 / CUP4 Five Reset Flags: watchdog, error address, power-on, external reset, and low voltage reset. Low Power consumption: - Operating current < 1.0mA @ 3.0V, CPU runs at 1.2MHz, 4.85MHz. PLL on - Operating current < 500μA @ 3.0V, CPU runs at 1MHz, 2MHz ROSC on - Operating current < 20μA @ 3.0V, CPU runs at 32KHz, 32768 crystal on, PLL off - Halt current < 2.0μA @ 3.0V, 1/8 duty, no load, 32768 crystal & LCD on, PLL & CPU off 3. BLOCK DIAGRAM 8-BIT RISC PROCESSOR PLL / ROSC

32768 ROS C

/ 32768 CRYS TAL ONE 16-B IT AUT O REL OAD TIME R

32 SEGM ENT S( M AX)

12 COMMONS(MAX )

( Some I/O Pins shared with LCD Outputs ) MAX I/O P O R T 8K X 8 ROM

128 X 8

80 QFP 80 LQFP

SEG27 – 21 SEG20 – 6 SEG5 – 0 13 - 19 25 - 39 44 - 49 11 - 17 23 - 37 42 - 47 O LCD driver segment output. COM4_SEG31 9 7 O Shared pin for LCD common4 or segment31 COM5_SEG30 10 8 O Shared pin for LCD common5 or segment30 COM6_SEG29 11 9 O Shared pin for LCD common6 or segment29 COM7_SEG28 12 10 O Shared pin for LCD common7 or segment28 COM3 - 0 50 - 53 48 - 51 O LCD driver common output I Inputs for setting LCD bias CUP1 CUP2 I Inputs for setting LCD bias IOA7 72 70 I/O IOA port bit7, can be used to output IR carrier IOA6 73 71 I/O IOA port bit6, can be used to output tone IOA5 74 72 I/O IOA port bit5, shared pin with LCD common8 In RFC application, used as a pass-through (output) pin and connected to sensor. IOA4 75 73 I/O IOA port bit4, shared pin with LCD common11 In RFC application, used as a pass-through (output) pin and connected to sensor IOA3 76 74 I/O IOA port bit3, shared pin with LCD segment29 In RFC application, used as a pass-through (output) pin and connected to sensor. IOA2 77 75 I/O IOA port bit2, shared pin with LCD segment28. IOA1 78 76 I/O IOA port bit1, Timer external input 2, External Interrupt input 2. In RFC application, used as input-floating pin and connected to sensor & capacitor. IOA0 79 77 I/O IOA port bit0, Timer external input 1, External Interrupt input 1 CUP3_INB7 58 56 I Shared pin for (1) INB input port bi t7 with key-change detection (2) Input for setting LCD bias (CUP3). CUP4_INB6 59 57 I Shared pin for (1) INB input port bi t6 with key-change detection (2) Input for setting LCD bias (CUP4). V3_INB5 65 63 I Shared pin for (1) INB input port bi t5 with key-change detection (2) Input for setting LCD bias (V3). INB4 8 6 I/O Shared pin for (1) INB input port bit4 with key-change detection (2) LCD segment 31 (3) LCD common 10. INB3 7 5 I/O Shared pin for (1) INB input port bit3 with key-change detection (2) LCD segment 30 (3) LCD common 9. INB2 6 4 I INB input port bit2 with key-change detection INB1 5 3 I INB input port bit1 with key-change detection INB0 4 2 I INB input port bit0 with key-change detection X32I 67 65 I 32.768KHz Crystal/R-OSC Input (option) X32O 68 66 O 32.768KHz crystal output RESETB 66 64 I External reset input pin (Low active) VSS 69 67 P Ground input OSCPLL 70 68 I PLL Input/R-OSC Input (option) VDD 71 69 P Power input TEST 80 78 I Test input Legend: I = Input, O = Output, P = Power

© Generalplus Technology Inc. Proprietary & Confidential 5 Jul. 27, 2011 Version: 1.4 4.2. PAD Assignment 16 17 18 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INB0 INB1 INB2 INB3 INB4 COM4_SEG31 COM5_SEG30 COM6_SEG29 COM7_SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG20 SE G19 SE G18 SE G17 SE G16 SE G15 SE G14 SE G13 SE G12 SE G11 SE G10 SEG9 SEG8 SEG7 SEG6 CUP3_INB7 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 COM1 COM0 CUP4_INB6 CUP1 CUP2 TEST IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 VDD OSCPLL VS S X32O X32I RESETB V3 | INB 5 (0,0) X Y SEG2 1 SEG5 The IC substrate should be connected to VSS or floating. Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.

© Generalplus Technology Inc. Proprietary & Confidential 6 Jul. 27, 2011 Version: 1.4 4.3. PIN Map 4.3.1. 80 pin QFP Package (HQ05x) 1 2 3 4 5 6 7 8 9 INB1 INB0 INB3 INB2 COM4_SEG31 INB4 COM6_SEG29 COM5_SEG30 COM7_SEG28 SEG26 SEG27 SEG24 SEG25 SEG23 SEG21 SEG22 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 NC SEG3 SEG2 SEG5 SEG4 COM3 COM2 SEG1 SEG0 COM1 COM0 CU P1 CU P2 CU P4 _I N B6 CU P3 _I N B7 TEST IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 VDD OSCPLL VSS X32O X32I RESETB V3_INB5 SPL12A 80 pin QFP package NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GPL12A

© Generalplus Technology Inc. Proprietary & Confidential 7 Jul. 27, 2011 Version: 1.4 4.3.2. 80 pin LQFP Package (HL04x) 1 2 3 4 5 6 7 8 9 1 80 pin LQFP package TESTP IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 VDD OSCPLL VSS X32O X32I RESET P V3_INB5 SEG3 SEG2 SEG5 SEG4 COM3 COM2 SEG1 SEG0 COM1 COM0 CUP1 CUP2 CUP4_INB6 CUP3_INB7 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 INB1 INB0 INB3 INB2 COM4_SEG31 INB4 COM6_SEG29 COM5_SEG30 COM7_SEG28 SEG26 SEG27 SEG24 SEG25 SEG23 SEG21 SEG22 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

48 By te LCD RAM

128 Byte SRAM

$00 ~ $1F $80 ~ $FF $1E0 ~ $1FF $50 ~ $7F $E000 ~ $FFFF $200 ~ $3FF Reserv ed$400 ~ $DFFF Note: 1. 512 bytes testing program ROM: $400 ~ $5FF 2. $0080 ~ $00FF maps to the 128 bytes SRAM, and $01E0 ~ $01FF also maps to $E0 ~ $FF (maximum stack is 32 byte) 3. Illegal Address range: $0020 ~ $004F, $0100 ~ $01DF, $0200 ~ $03FF $0400 ~ $DFFF 5.2. Clock Sources Control There are two groups of clock sources controlled by two mask- options (HCKOPT / LCKOPT) (1) High-speed clock source: PLL / ROSC (2) Low-speed clock source: 32768Hz R-oscillator / Crystal oscillator 5.2.1. Clock sources combination HCKOPT LCKOPT ROSC/C32K 0 0 ROSC/R32K 0 1 PLL/C32K 1 X Note1 Note 1: No PLL/R32K combination, it is mapped to PLL/C32K mode. 5.2.2. Switching of CPU clock CPU clock is programmable as (1) high-speed clock / 2 / 4 / 8 / 16 or (2) 32768Hz. 5.3. Operation Modes There are four operation modes involved in GPL12A - standby, halt, wait and operating. The following figure is the GPL12A state diagram. OPERATING HALT STANDBY WAIT Wake-up or user reset Write $0F to stop High-Speed clock ( CPU clock=High-Speed clock ) Wake-up or user reset Write $0F to set WAIT mode Wake-up or user reset Write $0F to stop Low-Speed clock The following table summarizes the differences between these modes. Operating Wait Halt Standby CPU clock ON OFF OFF OFF PLL/Oscillator ON ON OFF OFF 32768 crystal / 32768 oscillator ON ON ON OFF 5.3.1. Operating mode In operating mode, all functions (CPU, PLL/R-oscillator, 32768Hz crystal /32768Hz oscillator, timer/counter, LCD driver…) are activated. In general, this mode consumes the highest power. 5.3.2. Wait mode In wait mode, CPU clock halts and waits for an event (key-change, timer overflow…) to wake up. In addition to CPU stop, all other resources are still working. This mode consumes less power than all other peripherals that are activated except CPU.

© Generalplus Technology Inc. Proprietary & Confidential 9 Jul. 27, 2011 Version: 1.4 5.3.3. Halt mode In halt mode, CPU clock halts and PLL/ROSC clock sources stop and wait for an event (key change, timer overflow…) to wake up. The 32768Hz relevant functions, su ch as timer/counter and LCD driver, may remain active in halt mode. 5.3.4. Standby mode The standby mode is a mode that the device is placed in its lowest current consumption state. In standby mode, all functions are turned off. In additi on, RAM and I/Os will remain in their previous states. 5.4. LCD Controller/Driver The GPL12A contains a 360-dot LCD controller/driver in which the configuration can be defined via setting up the LCD Control Register. Once the LCD configuration is completed, the desired patterns can be displayed by filling the LCD RAM with proper data. The LCD driver can also operate during sleep mode by keeping 32768Hz oscillator running. The LCD driver in GPL12A supports 1/3 ~ 1/12 duty and 1/2 ~ 1/4 bias. The LCD frame rate can be adjusted by programming Port_LCDCK_CTL($11) register in small step between 40 Hz ~ 100 Hz. 5.5. Watchdog Timer (WDT) An on-chip watchdog timer is also available in the GPL12A. The WDT is designed to recover system from abnormal operation. If WDT is not cleared within one second, the WDT generates reset signal to CPU. The WDT is recommended to be cleared via software programming in every 0.5 seconds to avoid accidental reset. Note that the WDT works only when 32768Hz clock is activated. 5.6. Wakeup/Interrupt Control There are eight wakeup sources: 37.9K/N, 32768/N, TMO, EXT1, EXT2, T2Hz, KEYC, and NMI. Interrupt sources can be used as (1) wake-up source only. (2) both wakeup source and interrupt CPU. 5.7. RFC Function The RFC (Resistor to Frequency Converter) circuit contains a RC oscillation circuit and a 16-bit ti mer/counter to calculate the resistance of temperature or humidity sensor relative to reference resistor. The circuit is shown below. RREF RTH RTEMP IOA3 PAD IOA4 PAD IOA5 PAD IOA1 PAD SMT 16 bit Timer/Counter 8-Bit data bus RFCEN IOA3 floating control IOA4 floating control IOA5 floating control

© Generalplus Technology Inc. Proprietary & Confidential 10 Jul. 27, 2011 Version: 1.4 5.8. IR Output Control In IR-application, we must use PLL/32768 Hz crystal combination of clock sources to get PLL Freq = 4.85MHz. Next, the 4.85MHz PLL Freq is sent to the duty controller to generate 37.9KHz and 1/8 duty resolution IR-output pulse. The 37.9KHz IR-output pulse is delivered to Port IOA7 and controlled by software or Timer-overflow. 5.9. Mask Options PIN Description Comment HCKOPT 0: ROSC; 1: PLL LCKOPT 0: 32768 Hz oscillator 1 32768 Hz crystal LVROFF 0: LVR enable 1: LVR disable LVRLVL 0: 1.9V 1: 2.2V 5.10. Default Status of PINs IOA (IOA0 ~ IOA7) => Input with pull-low INB (IOB0 ~ IOB7) => Input with pull-low LCD => OFF (Common = Low & Segment = Low) CUP3_INB6 = INB6 CUP4_INB7 = INB7 V3_INB5 = INB5 COM4_SEG31 = SEG31 COM5_SEG30 = SEG30 COM6_SEG29 = SEG29 COM7_SEG28 = SEG28 INB3 (SEG30/COM9) = INB3 INB4 (SEG31/COM10) = INB4 IOA4 (COM11) = IOA4 IOA5 (COM8) = IOA5 OSCPLL = ROSC (HCKOPT Mask-option=Low) X32I/R32I = X32K (LCKOPT Mask-option=Low)

© Generalplus Technology Inc. Proprietary & Confidential 11 Jul. 27, 2011 Version: 1.4 6. ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range V IN -0.5V to V + + 0.5V Operating Temperature T A 0℃ to + 60 ℃ Storage Temperature T STO -50℃ to + 150 ℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For no rmal operational conditions, see AC/DC Electrical Characteristics. 6.2. DC Characteristics(TA=25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Condition Operating Voltage VDD 2.7 - 5.5 V Maximum CPU speed = 4.0MHz Operating Voltage VDD 1.9 - 3.6 V Maximum CPU speed = 2.5MHz - - 1.0 mA VDD = 3.0V, CPU = 1.2MHz, PLL ON - - 500 μA VDD = 3.0V, CPU = 1.0MHz, 2MHz ROSC ON Operating Current IOP - - 20 μA VDD = 3.0V, CPU = 32768, 32768 ON, PLL OFF Standby Current I STBY - - 1.0 μA VDD = 3.0V, PLL & 32768 OFF Audio Output Current I AUD 8.0 - - mA VDD = 3.0V Input High Level V IH 2.0 - - V VDD = 3.0V Input Low Level V IL - - 0.8 V VDD = 3.0V Output High Current I OH1 5.0 - - mA VDD = 3.0V, VOH = 2.4V, IOA[7:0] Output Low Current I OL1 8.0 - - mA VDD = 3.0V, VOL = 0.8V, IOA[7:0] RPU1 - 120K - - VDD = 3.0V Pull-up Resistor RPU1 - 70K - - VDD = 4.5V RPD1 - 120K - - VDD = 3.0V Pull-down resistor RPD1 - 70K - - VDD = 4.5V

© Generalplus Technology Inc. Proprietary & Confidential 12 Jul. 27, 2011 Version: 1.4 6.3. The Relationships between the ROSC and the FOSC VDD=3V 0 100 200 300 Rosc(Kohms) Fosc(MHz) VDD=4.5V 0 100 200 300 Rosc(Kohms) Fosc(MHz) 6.4. The Relationships between the R32K and the F32K VDD=3V 450 550 650 750 850 R32K(Kohms) F32K(KHz) VDD=4.5V 450 550 650 750 850 R32K(Kohms) F32K(KHz)

© Generalplus Technology Inc. Proprietary & Confidential 13 Jul. 27, 2011 Version: 1.4 7. APPLICATION CIRCUITS 7.1. 360 Dots (12 x 30) LCD Driver, 1/4 Bias, PLL / 32768Hz Crystal INB1 INB0 INB3 INB2 COM 4_SEG31 INB4 COM 6_SEG29 COM 5_SEG30 COM 7_SEG28 SEG26 SEG27 SEG24 SEG25 SE G 2 3 SEG21 SEG22 TEST IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 VDD OSCPLL VSS X32O X32I RESETB V3_INB5 GPL12A COM[3:0 COM[7:4] COM[10:9] COM8 COM11 SEG[27:0] SEG29 SEG28 LCD SE G[29:0 ] COM[11:0 ] COM[11:0] SEG[29:0] IO Device I/O INPUTS V3_ INB5 CUP1 CUP2 CUP3_I NB7 CUP4_I NB6 1 / 4 Bias application circuit Bias cirucit 32768 Hz 20p 20p VDD VCO circuit RA2 4.7KCA1 5nF CA2 100nF LVROFF : VSS --> LVR enable HCKOPT : VDD --> PLL LCKOPT : VSS --> 32768 Hz crystal Mask Options RESET SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG3 SEG2 SEG5 SEG4 COM3 COM2 SEG1 SEG0 COM1 COM0 CUP1 CUP2 CUP4_ INB 6 CUP3_ INB 7 VCO circuit 0.1μF 0.1μF 0.1μF 0.1 μF0.1μF 0.1 μF 0.1 μF 100 μF

© Generalplus Technology Inc. Proprietary & Confidential 14 Jul. 27, 2011 Version: 1.4 7.2. 256 Dots (8 x 32) LCD Driver, 1/4 Bias, R-Oscillator / 32768Hz R-Oscillator INB1 INB0 INB3 INB2 COM4_SEG31 INB4 COM6_SEG29 COM5_SEG30 COM7_SEG28 SE G2 6 SE G2 7 SE G2 4 SE G2 5 SE G2 3 SE G2 1 SE G2 2 TEST IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 VDD OSCPLL VSS X32O X32I RESETB V3_INB5 GPL12A COM[3:0] SEG[31:0] LCD SEG[31 :0] CO M[7: 0] COM[7:4] SEG[31:0] IO Device I/O INPUTS VDD 100 μF LVROFF : VSS --> LVR enable HCKOPT : VSS --> R-oscillator LCKOPT : VDD --> 32768 Hz R-oscillator Mask Options RESET SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG3 SEG2 SEG5 SEG4 COM3 COM2 SEG1 SEG0 COM1 COM0 CUP1 CUP2 CUP4_INB6 CUP3_INB7 VDD SEG29 SEG28 Bias cirucit V3_INB5 CUP1 CUP2 CUP3_INB7 CUP4_INB6 1 / 4 Bias application circuit VDD 0.1μF0 . 1 μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1 μF

© Generalplus Technology Inc. Proprietary & Confidential 15 Jul. 27, 2011 Version: 1.4 7.3. 128 Dots (4 x 32) LCD Driver, 1/2 or 1/3 Bias, R-Oscillator / 32768Hz Crystal IN B1 IN B0 IN B3 IN B2 COM4_SEG31 IN B4 COM6_SEG29 COM5_SEG30 CO M7_S EG28 SEG26 SEG27 SEG24 SEG25 SEG23 SEG21 SEG22 TEST IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 VDD OSCPLL VSS X32O X32I RESETB V3_INB5 GPL12A COM[3:0] SEG[31:0] LCD SEG [29:0] COM[11:0] COM[3:0] SEG[31:0] IO Device I/O INPUTS CUP1 CUP2 1 / 3 Bias application circuit Bias cirucit 32768 Hz 20p 20p VDD 100μF LVROFF : VSS --> LVR enable HCKOPT : VSS --> R-oscillator LCKOPT : VSS --> 32768 Hz crystal Mask Options RESET SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG3 SEG2 SEG5 SEG4 COM3 COM2 SEG1 SEG0 COM1 COM0 CUP1 CUP2 CUP4_INB6 CUP3_INB7 INPUTS CUP1 CUP2 1 / 2 Bias application circuit VDD 0.1μF0.1μF 0.1 μF 0.1μF 0.1μF 0.1 μF 0.1 μF

© Generalplus Technology Inc. Proprietary & Confidential 16 Jul. 27, 2011 Version: 1.4 8. PACKAGE/PAD LOCATIONS 8.1. Ordering Information Product Number Package Type GPL12A - NnnV - C Chip form GPL12A - NnnV - HQ05x Green Package form - QFP 80 GPL12A - NnnV - HL04x Green Package form - LQFP 80 Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number). 8.2. Package Information 8.2.1. 80 pin QFP (HQ05x) c E1E e b D AA2 Symbol Min. Nom. Max. Unit A - - 3.40 Millimeter A1 0.25 - - Millimeter A2 2.50 2.72 2.90 Millimeter b 0.30 0.35 0.45 Millimeter c 0.11 0.15 0.23 Millimeter D 23.20 REF Millimeter D1 20.00 REF Millimeter E 17.20 REF Millimeter E1 14.00 REF Millimeter e 0.80 REF Millimeter L1 1.60 REF Millimeter

© Generalplus Technology Inc. Proprietary & Confidential 17 Jul. 27, 2011 Version: 1.4 8.2.2. 80 pin LQFP (HL04x) E1E e b D c AA2 Symbol Min. Nom. Max. Unit A - - 1.60 Millimeter A1 0.05 - 0.15 Millimeter A2 1.35 1.40 1.45 Millimeter b 0.17 0.20 0.27 Millimeter c 0.09 - 0.20 Millimeter D 14.00 REF Millimeter D1 12.00 REF Millimeter E 14.00 REF Millimeter E1 12.00 REF Millimeter e 0.50 REF Millimeter L1 1.00 REF Millimeter

© Generalplus Technology Inc. Proprietary & Confidential 18 Jul. 27, 2011 Version: 1.4 9. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provis ions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, st atutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) fr om patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are curr ent before placing orders. Products descr ibed herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirement s, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.

© Generalplus Technology Inc. Proprietary & Confidential 19 Jul. 27, 2011 Version: 1.4 10. REVISION HISTORY Date Revision # Description Page JUL. 27, 2011 1.4 1. Modify “Ordering Information” in section 8.1. 2. Package information change from QQ05 to HQ05. 3. Package information change from QL04 to HL04. 6, 16 7, 17 JAN. 13, 2011 1.3 1. Working voltage modified to “1.9V ～5.5V”; 3. Modified low voltage reset description; 4. Add “1.9V/2.2V LVR level” for mask option select; 5. Modified operation voltage at DC Characteristics AUG. 7, 2008 1.2 “IOA3” in RFC function diagram change to “IOA1”. 8 MAR.16, 2005 1.0 Original Note: The GPL12A data sheet v1.0 is a continued version of SPL12A data sheet v0.2.

Product Information

GPL12A-NnnV-HL04x specifications and overview.

Summary

8K Bytes Micro-controller with LCD Driver

Description

8K Bytes Micro-controller with LCD Driver

Source title GPL12A-NnnV-HL04x Datasheet(PDF) - Generalplus Technology Inc.

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