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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPLL1100AA55 7KB LCD CONTROLLER/DRIVER MAR. 11, 2010 Version 1.5 In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 MAR. 11, 2010 Version: 1.5 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 MAR. 11, 2010 Version: 1.5 7KB LCD CONTROLLER/DRIVER 1. GENERAL DESCRIPTION The GPL10A5 is a CMOS 8-bit si ngle chip micro-controller which contains LCD drivers, ROM, SRAM, I/O, timer/counter and audio output on a single chip. The GPL10A5 is designed to drive LCD directly and performs efficient controller function as well as arithmetic function. With the on chip crystal oscillator, the real time clock is easily realized. For power saving, a software controllable standby switch is also built-in. The GPL10A5 is widely used in electronic products requiring very low power consumption, e.g., multi-function watch, calendar, calculator, and thermometer or LCD game with audio output. 2. BLOCK DIAGRAM 8-BIT RISC PROCESSOR ROSC GEN TIME BASE INTERRUPT LOGIC 7K X 8 ROM
96 X 8
P O R T DA TONE
32 SEGMENTS X 4 COMMANDS LCD DRIVER
(I/O) IOCD3 - 0 (I/O) IOAB1 - 0 (I/O) SEG31 - 0 COM3 - 0 ROSC X32I X32O 3. FEATURES Built-in 8-bit CPU Operating voltage: 2.4V to 5.2V Max. CPU clock: 2.0MHz @ 3.0V ROM capacity: 7K x 8 bits RAM capacity: 96 x 8 bits Direct Driver for LCD: 4 Commons X 32 Segments Input Port: six input pins with key wakeup function with four different configurations (mask option) I/O Port: Two general purpose I/O pins and four special purpose I/O pins that can implement thermometer Timer/Counter: one 12-bit timer/counter Six Interrupt sources: . External Interrupt . Timer Interrupt . 2KHz Interrupt . LCD Service Interrupt (in LCD share mode) . 128Hz Interrupt . 2Hz Interrupt Dual Clock System: One built-in RC oscillator (only one resistor is needed) for CPU and one built-in crystal oscillator or RC oscillator (mask option) for LCD scanning. Audio or Tone Output: One 7-bit current DA for playing melody/ speech or Tone output for playing melody System Reset: External Reset, Watch Dog Reset and Low Voltage Reset are built-in Low Operating Current: Typical current < 3 μA @ 3.0V for timepiece products Note: Patent Circuitry Included. Taiwan Patent No. 68824.
© Generalplus Technology Inc. Proprietary & Confidential 4 MAR. 11, 2010 Version: 1.5 4. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description SEG31 - 0 8 - 39 O LCD driver segment output COM3 - 0 40 - 43 O LCD driver common output IOAB1 - 0 7 - 6 I/O I/O port IOEF5 - 1 IOEF0 5 - 1 I INPUT port (also for key wake-up input) IOCD3 - 0 56 - 53 I/O I/O port ROSC 58 I R-OSC input, connect to VDD through a resistor RESET 57 I External reset input AUD 49 O Current DA output /Tone output X32I 51 I 32.768KHz crystal input/R oscillator input X32O 52 O 32.768KHz crystal output TEST 59 I Test input VDD 50 I Power input VSS 44 I Ground input VDD1 45 I Inputs for setting LCD bias VDD2 46 I Inputs for setting LCD bias CUP1 47 I Input for maintaining 1/3 Bias LCD CUP2 48 I Input for maintaining 1/3 Bias LCD
© Generalplus Technology Inc. Proprietary & Confidential 5 MAR. 11, 2010 Version: 1.5 4.1. PAD Assignment This IC substrate should be connected to VSS Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc. Proprietary & Confidential 6 MAR. 11, 2010 Version: 1.5 4.2. PIN Map IOEF4 IOEF5 IOAB0 IOAB1 SEG31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IOEF1 IOEF2 IOEF3 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 COM0 COM1 COM2 COM3 SEG0 VDD2 VDD1 VSS SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 NC 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ROSC RESET IOCD3 IOCD2 IOCD1 IOCD0 X320 X321 VDD AUD CUP2 CUP1 NC TEST IOEF0 NC NC GPL10A5 64 pin LQFP package
© Generalplus Technology Inc. Proprietary & Confidential 7 MAR. 11, 2010 Version: 1.5 5. FUNCTIONAL DESCRIPTIONS 5.1. ROM The GPL10A5 provides 7.5K bytes ROM size of which 7K bytes for program and data. The other 0.5K bytes are for GENERALPLUS internal test use. The ROM address is from $0200 to $1FFF. 5.2. RAM The GPL10A5 provides 96 bytes RAM. The RAM is for both stack and data storage, ranged from $00A0 to $00FF. 5.3. Memory and I/O Map $0000 $001F $00A0 $00FF $0100 $01FF $0200 $03FF $0400 $1FFF GENERALPLUS TEST PROGRAM $05FF $0600 H/W REGISTER,I/Os USER RAM and STACK DUMMY for ICE DEBUG USER'S PROGRAM DATA AREA ROM USER'S PROGRAM DATA AREA ROM 5.4. Oscillators The GPL10A5 is a dual clock syst em. One clock is for the CPU and system and the other is for the LCD scanning and interrupt sources. 5.4.1. R Oscillator for the CPU and system clock 5.4.1.1. Normal case +VDD 5.4.1.2. Noisy environment +VDD Note: Length of the wiring for ROSC pin should be minimized because the oscillator frequency varies due to coupling from other signal lines. 1). 32768Hz crystal oscillator or R oscillator (mask option) for LCD scanning and interrupt sources (2KHz, LCDL for LCD service, 128Hz, 2Hz). It is suggested to enable 32768Hz crystal in strong mode for a few seconds and then switch to weak mode when reset occurs. X32I X32O 32768Hz 32768Hz Crystal Note: Since each crystal has its own characteristics, we recommend consulting the crystal vendor for appropriate C1/C2 values.
© Generalplus Technology Inc. Proprietary & Confidential 8 MAR. 11, 2010 Version: 1.5 +VDD X32I R Oscillator R Note: Length of the wiring for X32I and X32O should be as short as possible. 5.5. Stop Clock Mode The GPL10A5 supports the power saving mode for those applications needing very low standby current. The user can simply enable the wake-up sources and then stop the CPU clock by writing the STOP CLOCK register ($09). The CPU will enter standby and the RAM and I/O remain their previous states until wake-up. There are three sources of wake-up in this chip, PORT IOEF wake-up, TIMER 0 wake-up and 2Hz wake-up. After the chip is wakening up, the internal CPU will go to the RESET state and the RAM and I/O are not affected by the wake-up reset. The standby current of timepiece product typically is less than 3 μA @ 3.0V by using this mode and 32768Hz clock source in weak mode. For non-timepiece products, 32768Hz crystal driver or R oscillator (mask option) that generates the 32768Hz clock source also can be turned off to stop the chip operation. The standby current of the GPL10A5 is less than 1 μA @ 3.0V. In this mode, IOEF port can be used to wake up the chip. 5.6. Timer/Counter The GPL10A5 contains one 12-bit ti mer/counter, TM0. In timer mode, TM0 is reloadable up-counter. When timer overflows from $0FFF to $0000, the carry signal will generate the INTERRUPT signal if the corresponding bit is enabled in INT ENABLE register ($0D), and the timer will be auto reloaded to the user‘s setup value and count up again. If TM0 is be ing specified as a counter, the user may reset the counter by loading 0 into register $14 and $1C. After the counter being activated, the count value can also be read from above registers on-the-fly, the read instruction will not affect the counter's value or reset it. The clock source of the timer/counter are selectable as the following: Timer/Counter Addr. Clock Source
12 BIT TIMER $0014
$001C CPU CLOCK (T) or T/4 TM0
12 BIT COUNTER
$0014 $001C T/128, T/256, T/2048 or EXT CLK MODE SELECT REGISTER $000B Select TM0 timer or counter TIMER CLOCK SELECTOR $001C Select T or T/4 5.7. Interrupts The GPL10A5 has six interrupt sources - INT0 (interrupt from TIMER 0), 2KHz INT, LCDL INT (LCD service in share mode, due to LCD registers is shared with the TIMER/COUNTER), 128Hz INT, EXT INT (external INTERRUPT from IOCD1), 2Hz INT. The 2KHz INT, LCDL INT (256 Hz in 1/3, 1/4 duty; 128 Hz in 1/2 duty), 128Hz INT, 2Hz INT, all are derived from 32768Hz Crystal Oscillator by division. 5.8. Audio (Melody/Speech) / Tone Output The GPL10A5 provides both speech and single tone melody output in current DA type that can drive SPEAKER through transistor. Also, the GPL10A5 provides TONE output that can directly drive BUZZER. Current DA and TONE that the two modes are share the same AUD pin. In current DA mode, it should smoothly switch current DA output current to zero by using speech mode to reduce noise to turn off current DA. The current DA should be turned off when not used due to the current consumption. The TONE out put is a full-swing (VDD and VSS) signal and its frequency source is the frequency of TIMER Carry divided by 2. The block diagram is shown as below:
2 TONE
© Generalplus Technology Inc. Proprietary & Confidential 9 MAR. 11, 2010 Version: 1.5 5.9. Liquid Crystal Display The GPL10A5 can directly drive the liquid crystal display (LCD) panel of 1/2 duty, 1/3 duty, and 1/4 duty with 1/2 bias or 1/3 bias. It has 4 commons and 32 segments signal pins. In share mode (Timer/Counter is used), the LCD is refreshed by LCDL interrupt. The INT routine will read the number of common which is under serving, and send the next common's pattern to LCD port ($10 - $13) from RAM buffer. If the Timer/the counter is not used, hardware mechanism will auto re fresh the LCD after writing OPTION register ($1F). The power connections for LCD (1/2 bias, 1/3bias) are shown as below: VDD2 0.1μ 1 / 2 Bias VDD1 1 / 3 Bias VDD2 CUP2 CUP1 0.01μ VDD 0.01μ 0.01μ 5.10. Output Waveform of the LCD Driver VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VSS VDD VSS COM0 COM1 COM2 COM3 Normal operation 1/2 Bias , 1/2 duty lighting format At the initial clear ( reset ) COM3 - 0 LCD display ON mode LCD segments display ON LCD driver output: COM0 LCD segments display ON LCD driver output: COM1 LCD driver output:All the LCD segments display OFF LCD driver output:All the LCD segments display ON
© Generalplus Technology Inc. Proprietary & Confidential 10 MAR. 11, 2010 Version: 1.5 COM0 COM1 COM2 COM3 Normal operation VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS At the initial clear ( reset ) COM3 - 0 LCD display ON mode 1/2 Bias , 1/3 duty lighting format VDD VSS VDD VSS LCD segments display ON LCD driver output: COM0 LCD segments display ON LCD driver output: COM1 LCD segments display ON LCD driver output: COM2 LCD segments display ON LCD driver output:COM0 and COM1 LCD segments display ON LCD driver output:COM0 and COM2 LCD segments display ON LCD driver output:COM1 and COM2 LCD driver output:All the LCD segments display OFF LCD driver output:All the LCD segments display ON
© Generalplus Technology Inc. Proprietary & Confidential 11 MAR. 11, 2010 Version: 1.5 COM0 COM1 COM2 COM3 Normal operation VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS At the initial clear ( reset ) COM3 - 0 LCD display ON mode 1/2 Bias , 1/4 duty lighting format VDD VSS VDD VSS LCD driver output:All the LCD segments display OFF LCD segments display ON LCD driver output: COM0 LCD segments display ON LCD driver output: COM1 LCD segments display ON LCD driver output: COM2 LCD segments display ON LCD driver output: COM3 LCD segments display ON LCD driver output: COM0 and COM1 LCD segments display ON LCD driver output : COM0 and COM2 LCD segments display ON LCD driver output : COM1 and COM2 LCD segments display ON LCD driver output : COM1 and COM3
© Generalplus Technology Inc. Proprietary & Confidential 12 MAR. 11, 2010 Version: 1.5 1/3 Bias , 1/2 duty lighting format COM0 COM1 COM2 COM3 Normal operation At the initial clear ( reset ) COM3 - 0 LCD display ON mode VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD2 VDD1 VDD2 VDD1 VDD2 VDD1 VDD VSS VDD VSS VSS VDD LCD segments display ON LCD segments display ON LCD driver output: COM1 LCD driver output:All the LCD segments display ON LCD driver output: COM0 LCD driver output:All the LCD segments display OFF
© Generalplus Technology Inc. Proprietary & Confidential 13 MAR. 11, 2010 Version: 1.5 COM0 COM1 COM2 VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD2 VDD1 VDD2 VDD1 Normal operation At the initial clear ( reset ) 1/3 Bias , 1/3 duty lighting format COM3 - 0 LCD display ON mode VDD VSS VDD VSS COM3 LCD segments display ON LCD driver output: COM1 LCD segments display ON LCD driver output: COM2 LCD segments display ON LCD segments display ON LCD segments display ON LCD segments display ON LCD driver output: COM0 LCD driver output:All the LCD segments display OFF LCD driver output : COM1 and COM2 LCD driver output : COM0 and COM2 LCD driver output : COM0 and COM1
© Generalplus Technology Inc. Proprietary & Confidential 14 MAR. 11, 2010 Version: 1.5 COM0 Normal operation VDD VDD2 VDD1 VSS At the initial clear ( reset ) 1/3 Bias , 1/4 duty lighting format COM3 - 0 LCD display ON mode VDD VSS VDD VSS COM1 VDD VDD2 VDD1 VSS COM2 VDD VDD2 VDD1 VSS COM3 VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD2 VDD1 LCD segments display ON LCD driver output: COM1 LCD segments display ON LCD driver output: COM2 LCD segments display ON LCD driver output : COM0 and COM2 LCD segments display ON LCD driver output : COM1 and COM3 LCD segments display ON LCD driver output: COM0 LCD segments display ON LCD driver output: COM3 LCD driver output:All the LCD segments display OFF
© Generalplus Technology Inc. Proprietary & Confidential 15 MAR. 11, 2010 Version: 1.5 5.11. Reset Function The GPL10A5 can be reset by setting the RESET pin to ground voltage and its operation starts when this pin is set to power voltage. Also an automatic reset function (internal reset function) operates when power is turned on. 5.12. Watch Dog Function The GPL10A5 provides a watch dog timer. The watchdog timer must be reset when 2Hz wake-up by writing $0F, otherwise it will reset the system. 5.13. Mask Option The following type mask option is available. INPUT/OUTPUT) 1). Without Fixed Pull Low Resistor 200KΩ, with Feedback MOS 2). With Fixed Pull Low Resistor 200KΩ, without Feedback MOS 3). With Fixed Pull Low Resistor 200KΩ, with Feedback MOS 4). Without Fixed Pull Low Resistor 200K Ω, without Feedback MOS oscillator) 1). 32768Hz Crystal Oscillator 2). R Oscillator 6. I/O PORT CONFIGURATION 6.1. Input IOEF Port: IOEF0 to IOEF5 There are 4 different configurations in IOEF port. They are shown as following: EF PORT ( MASK OPTION ) : EF PORT WRITE GND PL GND TYPE A INPUT D Q 50K30K CK 30K D Q 200K GND GND TYPE B INPUT PL 200K 30K GND CK D Q 50K GND PL GND TYPE C INPUT CK GND 30K D Q CK TYPE D INPUT PL 6.2. Input/Output IOAB Port: IOAB0 and IOAB1 These two ports can be programmed to be INPUT or OUTPUT pins. The configurations are shown as below: D Q OUTPUT INPUT 100K GND input data CK : AB PORT WRITEAB PORT 6.3. Input/Output IOCD Port: IOCD0 to IOCD3 These four IOCD ports can be programmed to be INPUT or OUTPUT pins independently. These pins also can be used to implement a thermometer by sens e mode. Their configurations are shown as below: D Q OUTPUT INPUT 100K GND input data CK : CD PORT WRITECD PORT
© Generalplus Technology Inc. Proprietary & Confidential 16 MAR. 11, 2010 Version: 1.5 The application circuit for sense mode: Thermo-resistor IOCD1 IOCD2 IOCD3
© Generalplus Technology Inc. Proprietary & Confidential 17 MAR. 11, 2010 Version: 1.5 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating ta ble may cause operational errors or damage to the device. For no rmal operational conditions see AC/DC Electrical Characteristics. 7.2. DC Characteristics (VDD = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Condition Operating Voltage VDD 2.4 - 3.6 V For 2-battery Operating Current IOP - 350 - μA FCPU = 600KHz @ 3.0V, No load Standby Current ISTBY - - 1.0 μA VDD = 3.0V, 32768Hz OFF Audio Output Current IAUD - -1.0 - mA VDD = 3.0V Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output High I IOH -300 - - μA VDD = 3.0V, VOH = 2.4V Output Sink I IOL 600 - - μA VDD = 3.0V, VOL = 0.8V LCD Drive VDD 2.8 - 3.0 V VLCD = 3.0V, IO = - 6.0μA VDD2 1.8 - 2.2 V VLCD = 3.0V, IO = - 3.5μA VLCD = 3.0V, IO = + 3.5μA VDD1 0.8 - 1.2 V VLCD = 3.0V, IO = - 3.5μA VLCD = 3.0V, IO = + 3.5μA Output Voltage VSS 0 - 0.2 V VLCD = 3.0V, IO = + 6.0μA 7.3. DC Characteristics (VDD = 4.5V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Condition Operating Voltage VDD 3.6 - 5.2 V For 3-battery Operating Current IOP - 550 - μA FCPU = 600KHz @ 4.5V, no load Standby Current ISTBY - - 1.0 μA VDD = 4.5V, 32768Hz OFF Audio Output Current IAUD - -1.0 - mA VDD = 4.5V Input High Level VIH 3.0 - - V VDD = 4.5V Input Low Level VIL - - 0.8 V VDD = 4.5V Output High I IOH -300 - - μA VDD = 4.5V, VOH = 3.6V Output Sink I IOL 600 - - μA VDD = 4.5V, VOL = 0.9V
© Generalplus Technology Inc. Proprietary & Confidential 18 MAR. 11, 2010 Version: 1.5 7.4. The Relationships between the ROSC and the FCPU 0.5 1.5 0 200 400 600 800 Rosc(Kohms) Fcpu(MHz) 0.5 1.5 0 200 400 600 800 Rosc(Kohms) Fcpu(MHZ) 7.5. The Relationships between the FCPU and the VDD 0.5 1.5 2.5 2.5 3 3.5 4 4.5 VDD(Volts) FCPU(MHz) Rosc = 100 Kohms Rosc = 800 Kohms 7.6. The Relationships between the FCPU and the IOP 200 400 600 800 1000 0 0.5 1 1.5 2 FCPU(MHz) Iop(uA) VDD = 4.5V VDD = 3V
© Generalplus Technology Inc. Proprietary & Confidential 19 MAR. 11, 2010 Version: 1.5 7.7. AC Characteristics Limits Characteristics Symbol Min. Typ. Max. Unit Test condition OSC Frequency FOSC - - 4.0 MHz VDD = 3.0V CPU Clock FCPU - - 2.0 MHz FCPU = FOSC/2 @ 3.0V - 64 - Hz 1/2 duty - 85 - Hz 1/3 duty Frame Frequency of The LCD Drive FFM1 - 64 - Hz 1/4 duty Wake-up time TW 6T1 - - Sec. - T1 = 1 / (FOSC), Tw = 3 x T1, FCPU = FOSC/2 Sleep system clock CPU clock Wake-up TW
© Generalplus Technology Inc. Proprietary & Confidential 20 MAR. 11, 2010 Version: 1.5 8. APPLICATION CIRCUITS 8.1. GPL10A5 Application Circuit GPL10A5 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 IOEF1 IOEF2 IOEF3 IOEF4 IOEF5 IOAB0 IOAB1 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 CUP1 CUP2 AUD X32I X32O IOCD0 IOCD1 IOCD2 IOCD3 RESET ROSC TEST IOEF0 IO DEVICE LCD I/O Inputs Common Segment VDD1 CUP1 CUP2 CUP1 CUP2 0.01µF Bias option RESET COM[ 3:0] SEG[ 31:0] Audio CKT 100 µF SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG23 0.01µF 0.01µF 0.1µF VDD2 VDD1 VDD2 VDD VDD 0.1µF VDD VDD 1/2 Bias application circuit 1/3 Bias application circuit VDD1 VDD2 VSS 10-22pF* 10-22pF* 32768Hz 30pF Note*: These capacitor values are for design guidance only. Different capacitor values (10-22pF) may be required for different crystal/ resonator used.
© Generalplus Technology Inc. Proprietary & Confidential 21 MAR. 11, 2010 Version: 1.5 8.2. Audio Driver/Amplifier for DA Mode *AUD IN CURRENT DA MODE *AUD IN TONE MODE BUZZER AUD GND VDD 8050 AUD 200~2K0.1µF
© Generalplus Technology Inc. Proprietary & Confidential 22 MAR. 11, 2010 Version: 1.5 9. PACKAGE/PAD LOCATIONS 9.1. Ordering Information Product Number Package Type GPL10A5 - NnnV - C Chip form GPL10A5 - NnnV - QL02x Halogen Free Package - LQFP 64 GPL10A5 - NnnV - QL02x Halogen Free Package - LQFP 64 Lead free Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number).
© Generalplus Technology Inc. Proprietary & Confidential 23 MAR. 11, 2010 Version: 1.5 9.2. Package Information LQFP 64 Outline Dimensions Dimension in inch Symbol Min. Typ. Max. A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c1 0.09 - 0.16 D 12.00 D1 10.00 E 12.00 E1 10.00 e 0.50 BSC.
© Generalplus Technology Inc. Proprietary & Confidential 24 MAR. 11, 2010 Version: 1.5 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 25 MAR. 11, 2010 Version: 1.5 11. REVISION HISTORY Date Revision # Description Page MAR. 11, 2010 1.5 1. Modify 5.7. Interrupts. 2. Modify 5.10. Output Waveform of the LCD Driver. 3. Modify 9.1. Ordering Information. 9, 10, 12 AUG. 07, 2007 1.4 1. Modify 3. FEATURES. APR. 12, 2007 1.3 1. Modify 4.1. PIN Map. 2. Modify 9.2. Ordering Information. JUN. 23, 2006 1.2 2. Modify 8.1.Application Circuit. 3. Modify 8.2.Audio Driver/ Amplifier for DA Mode. 4. Remove 9.3. Pad Locations. 5. Add 9.3. Package Information. 6-7 MAR. 10, 2005 1.0 Original Note: The GPL10A5 data sheet v1.0 is a continued version of SPL10A3 data sheet v1.1.