GPF8F096A | DigiCamel IC Datasheet

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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the exp ress written approval of Generalplus. DATA SHEET Aug. 03, 2018 Version 1.1 GGPPFF88FF SSeerriieess 16-bit Sound Controller

1 GPF8F SERIES:

Product No. GPF8F096A GPF8F096A_0001 With voice recognition algorithm No Yes

2 GENERAL DESCRIPTION

GPF8F, a 16-bit architecture sound controller , features a Sunplus’s 16-bit ’nSP2.0™ (pronounced as micro-n-SP 2.0), microprocessor. High CPU operating speed ensures that GPF8F can handle complex digital signal processes efficiently and rapidly. GPF8F can be applied for digital sound processing and voice recogniti on. The operating voltage is from 2.2V t o 5.5V and clock speed is from 12MHz to 72MHz. The memory capacity includes embedded FLASH with a 6K-word working SRAM and 2K -word Cache RAM . Other feat ures includ e 32 programmable multi -function I/Os, five 16-bit timers/counters, 32768Hz Real Time Clock, Low Voltage Reset/Detection, eight channels 12 -bit ADC for line -in and one Codec 16 -bit ADC for microphone amplifier , 8 channel SPU(Sound Processing Unit) engine as midi -synthesizer, I2C control, CCPU(Compare , Capture and PWM Unit), capacitive touch sensor, one SPI FLASH controller, one 16-bit DAC with push -pull amplifier and many others.

3 FEATURES

 16-bit ’nSP2.0™ microprocessor  CPU Clock: 12MHz - 72MHz  Operating Voltage: 2.2V - 5.5V  Power regulator built-in with input voltage: 2.2~5.5V, output voltage:1.8V for core power, 3.1V for codec ADC ,3.3V for external device and 2.5V for touch module  IO PortA & B Operating Voltage: 2.2V - 5.5V  48K-word fast embedded flash memory  6K-word working SRAM  2K-word dedicated cache SRAM  Two 14-bit software channels with noise filter, mixer and scalar for high quality sound playback  Standby mode for power savings  Total five 16-bit timers available, including three general-purpose 16-bit timers/counters and two touch sensing timers (also for general-purpose).  8 channels SPU engine with 4/5 bit A3400Pro and 8/16 bit PCM format  One 14-bit DAC with push-pull amplifier, supporting cascade mode  32 general I/Os (bit programmable)  Key wakeup function (IOA0 - 15, IOB0-15)  Capacitor sensing touch hardware for 32 I/O and low power mode function  PLL feature for system clock  32768Hz Real Time Clock (RTC), crystal or internal resistor oscillator selected.  Eight channels of 12-bit AD converter for line-in  Codec 16-bit ADC for microphone amplifier and digital AGC circuit built-in  I2C control module  Comparison unit, Capturing unit and PWM Unit(CCPU)  Two-channel DMA controllers  UART interface  I2S input/output function to support 16-bit/24-bit data and left justified/1-bit shift format  Low voltage reset and low voltage detection  Watchdog (optional)  Two SPI serial interfaces: SPI FLASH controller (supporting one-I/O, two-I/O, four-I/O modes, and auto read/program mode), and normal SPI interface.  Specific products support voice recognition algorithm.

4 APPLICATION FIELD

 Voice Recognition Products  Intelligent Interactive Talking Toys  Advanced Educational Toys  Kids Learning Products  Kids Storybook  General Speech Synthesizer  Long Duration Audio Products  Recording/Playback Products

5 BLOCK DIAGRAM

6 SIGNAL DESCRIPTIONS

PORT A, Port B IOA [15:0] I/O IOA[15:0]: bi-direction I/O ports It is programmable as wakeup I/O pins. IOB [15:0] I/O IOB [15:0]: bi-directional I/O ports. It is programmable as wakeup I/O pins. Power & GND VDD_IOA1 P Power for IOA0~IOA9 VSS_IOA1 G Ground for IOA0~IOA9 VDD_IOA2 P Power for IOA10~IOA15 VSS_IOA2 G Ground for IOA10~IOA15 VDD_IOB1 P Power for IOB---5V domain VDD_IOB2 P Power for IOB---5V domain VSS_IOB G Ground for IOB V33ADC_REGO P 3.3V Power output from regulator for CODEC ADC (3.3V) VSS_ADC G Ground for CODEC ADC V33_REGO P 3.3V Power output from regulator V18_REGO P 1.8V Power output from regulator, for core power VDD_REGIN P Power supply for regulator (2.2V~5.5V) VSS_REG G Ground reference for regulator VDD_DAC P Positive 5V supply for push-pull DAC VSS_DAC G Ground reference for push-pull DAC VDD_PDAC P Positive 5V supply for push-pull DAC post driver VSS_PDAC G Ground reference for push-pull DAC post driver OPTION TEST I TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low) —3V domain DAC AUDP O Audio output of push pull DAC AUDN O Audio output of push pull DAC ACIN U Audio analog mixer in ADC MICIN I Microphone input—3V domain, pad power from V333ADC_REGO ADVCM I Common voltage(1/2*VDD) for amplifier and ADC —3V domain , pad power from V333ADC_REGO ICE ICE_CLK I ICE clock (with pull low)—3V domain, pad power from V33_REGO ICE_SDA I/O ICE serial data bus—3V domain, pad power from V33_REGO ICE_EN I ICE enable (high active , with pull low) —3V domain, pad power from V33_REGO Other Signal RESETB I System reset pin (active low) (internal 47Kohm pull high resistor) , pad power from VDD_IOB1 / VDD_IOB2

6.1 LQFP64 Package Pin Assignment

6.2 LQFP48 Package Pin Assignment

7 FUNCTION DESCRIPTIONS

7.1 CPU

GPF8F is equipped with a 16 -bit ’nS2.0P™ (pronounced as micro-n-SP) CPU. Sixteen registers are featured in ’nSP™ 2.0: R1 - R4 and R8 ~ R15 (General-purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) , SR (Segment Register) and eight extended registers . The interrupts include

30 FIQs (Fast Interrupt Request) and IRQs (Interrupt Request),

plus one software-interrupt, BREAK.

7.2 Memory

7.2.1 SRAM

There is 6K-word working SRAM and 2K-word dedicated cache RAM, working SRAM ranged from $0000 through $17FF.

7.2.2 Embedded Flash

GPF8F features a high-speed embedded FLASH with access speed of three CPU clock cycles.

7.3 PLL, Clock, Power Mode

7.3.1 PLL (Phase Lock Loop)

The purpose of PLL is to pump the frequency from 12MHz to 72MHz for system clock (F OSC). The default PLL frequ ency is 12MHz.

7.3.1.1 System clock

System clock is derived by PLL and programmed by register to supply operating clock for system. 7.3.1.2 32768Hz RTC The Real Time Clock (RTC) is normally used in watch, clock or other time related products. A 2Hz-RTC (0.5 seconds) function is loaded in GPF8F. The RTC counts the tim e as well as to wake CPU up whenever RTC occurs. Since the RTC is generated each 0.5 seconds, time can be traced by the number of RTC occurrences. In addition, GPF8F supports 32768Hz crystal oscillator in normal mode and auto-power-saving mode. In normal mode, 32768Hz OSC always runs at the highest power consumption.

7.4 Standby Mode

The GPF8F features a power savings mode (or called standby mode) for low power applications. In such mode, SRAM and I/Os remain in the previous states until CPU being awakened. After GPF8F is aw akened, CPU will continue to execute the program from where it slept.

7.5 Low Voltage Detection and Low Voltage Reset

7.5.1 Low voltage detection (LVD)

The Low Voltage Detect ion (LVD) reports the circumstance of present voltage. There are seven LVD levels to be selected :

7.5.2 Low voltage reset

In addition to the LVD, the GPF8F has another important function, Low Voltage Reset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below LVR level.

7.6 Interrupt

The GPF8F has 30 interrupt sources, grouped into two types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The priority of FIQ is higher than IRQ . User can refer programming guide for details.

7.7 I/O

The GPF8F has 32-bit programmable I/Os featuring wakeup capability. The following diagram is a n I/O schematic. Data Register Control Logic I/O Pad P_IOA/B_Buffer(R) P_IOA/B_Buffer(W) P_IOA/B_Dir(R/W) P_IOA/B_Attrib(R/W) P_IOA/B_Data(R) In addition to a general purpose I/O port function, IOA/B also shares/carries some special functions. A summary of IOA/B special functions is listed as follows:

7.8 Special Function in Port

7.9 Timer / Counter

The GPF8F has five 16-bit timer/counters. They are re-loadable up-counters. Wh en timer overflows from $ FFFF to $0000, the carry (overflow) signal will make the user’s preset value to be loaded into timer automatically and count up again. At the same time, the carry signal will generate an interrupt signal if the corresponding bit is enabled.

7.9.1 Compare, Capture and PWMIO

Eight independent channels are multi-function for Output Compare, Input capture and IO PWM generation.

7.9.2 I2C Control Module

Support master 10 bit/7 bit addressing and slave mode.

7.9.3 Timebase

Timebase, generated by 32768Hz crystal oscillator, is a combination of frequency selection. Furthermore, timebase generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt sources (FIQ6/IRQ6, FIQ7/IRQ7) for Real-Time-Clock, generated by 32768Hz crystal oscillator, is a combinat ion of frequency selection. Furthermore, timebase generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt sources (FIQ6/IRQ6, FIQ7/IRQ7) for Real-Time-Clock

7.10 Capacitance Touch Sensor (CTS) and CTS

GPF8F provides Capacitive Touch sensor. It provide s that the ability to perform capacitive sensing, decision making, responsive actions and other duties pertinent to the system as well.

7.11 Sleep Mode, Wakeup, Halt Mode, and Watchdog

7.11.1 Sleep and wakeup modes

1) Sleep, Halt : After power -on reset, IC s tarts running until a sleep command is issued . When a sleep command is accepted, IC will turn the system clock (PLL) off. It enters sleep mode if 32KHz Sleep Status bit is cleared or enters halt mode if 32KHz Sleep Status bit is set. 2) Wakeup: CPU awaking from sleep mode requires a wakeup signal to turn the system clock (PLL) on. The

© Generalplus Technology Inc. Proprietary & Confidential 11 Aug. 03, 2018 Version: 1.1 FIQ/IRQ signal makes CPU to complete the wakeup process and initialization. The CPU wakeup source is given in the following table. Wakeup up source include all FIQ source and all interrupt source.

7.11.2 Watchdog Reset

If the watchdog function is enabled, a reset signal is generated to reset system when watchdog counter is overflow.

7.12 ADC (Analog to Digital Converter)

7.12.1 ADC for Line-in

The GPF8F has eight channels 12-bit A DC (Analog to Digital Converter) to convert analog signal to digital signal. The eight channels of ADC can be eight channels of line-in from IOB [7:0].

7.12.2 ADC for microphone-in

Codec 16 -bit ADC for microphone amplifier and digital AGC circuit included.

7.13 SPU and Software Channel

The GPF8F uses a high performance SPU voice engine to archive 8-channel voice with ADPCM/PCM code. The SPU also supports automatic zero -crossing concatenating function. A hardware multip lier is also embed ded in this SPU for software usage. The fixed address es of RAM area $0000 - $008A is designed as address pointers and a data buffer for the 8-channel speech/ melody generation. Moreover, two 14-bit software channels with noise filter are also supported. There is one 14-bit DAC with push-pull amplifier for direct audio output.

7.14 UART Interface

The UART/ IrDA module built in GPF8F performs serial-to-parallel conversion on data received from a n external device and it also performs parallel-to-serial conversion on data transmitted to the external device.

7.15 SPIFC

A Serial Peripheral Interface FLASH controller (SPIFC) is built in GPF8F to facilitate communicating with other devices and components, especially for SPI FLASH. The SPIFC supports one-I/O, two-I/O, four-I/O mode of SPI FLASH. The SPIFC also supports auto mode which can access SPI FLASH data directly, therefore user’s program can be placed at external SPI FLASH. There are six control signals on SP I - SPICS (IO A12), SPICK (IOA13), SDI (IOA14), SDO (IOA15), SPIIO3 (IOA10, only for 4 I/O mode), and SPIIO2 (IOA11, only for 4 I/O mode).

7.15.1 SPI2

A Serial Peripheral Interface controller (SPI2) is built in GPF8F to facilitate communicating with other devices and components . There are four control signals on SPI2 - SPICS (IOB12), SPICK (IOB13), SDI (IOB14), and SDO (IOB15). D7 D6 D4D5 D2D3 D0D1 D7 D6 D5 D3D4 D2 D0D1 SPICK(POL=0) SPICK(POL=1) SDO SDI SPICS PHASE = 0

7.16 Audio Output

Two sets of 14-bit software channels with noise filter are supported. There is one 14 -bit DAC with push -pull amplifier for direct audio output.

8 ELECTRICAL SPECIFICATIONS

Characteristics Symbol Ratings DC Supply Voltage V+ < 4.0V Port A/B Pad Supply Voltage VIO < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +70℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Ra ting table may cause permanent damage to the device. For normal operational conditions see DC Electrical Characteristics. 8.1 DC Characteristics (VDD_REGIN = 4.5V, VDDIO = 4.5V (IOA & IOB ), TA = 25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD_REG 2.2 - 5.5 V - Operating Current IOP - 25 - mA FOSC = 72MHz, AD, DAC disable, no load Standby Current ISTB - - 10 A Disable 32KHz crystal 15 A Enable 32KHz,Disable PLL(FOSC) Input High Level VIH 0.7VDDIO - - V - Input Low Level VIL - - 0.3VDDIO V - Output High Current (IOA[9:0], IOB[11:0]) IOH 5 10 15 mA VOH = 0.7VDDIO Output High Current (IOA[15:10],IOB[15:12]) IOH 15 30 45 mA VOH = 0.7VDDIO, High driving current @16mA Output Low Current (IOA[9:8], IOB) IOL -9 -18 -27 mA VOL = 0.3VDDIO Output Low Current (IOA[15:10],IOB[15:12]) IOL -13 -26 -39 mA VOL = 0.3VDDIO, SPI interface @16mA Output Low Current (IOA[7:0]) IOL -18 -36 -54 mA VOL = 0.3VDDIO, High sink Input Pull-Low Resister (IOA, IOB) RPL 50 100 150 K VIN = VDDIO Input Pull-High Resister (IOA, IOB) RPH 50 100 150 K VIN = VSS Internal ROSC f requency deviation ⊿F/F -3% 12M +3% HZ V33_REG = 3.3V 8.2 DC Characteristics (VDD_REGIN = 3.3V, VDDIO = 3.3V (IOA & IOB), TA = 25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD_REG 2.2 - 5.5 V - Operating Current IOP - 25 - mA FOSC = 72MHz, AD, DAC disable, no load Standby Current ISTB - - 10 A Disable 32KHz crystal 15 A Enable 32KHz,Disable PLL(FOSC) Input High Level VIH 0.7VDDIO - - V -

© Generalplus Technology Inc. Proprietary & Confidential 14 Aug. 03, 2018 Version: 1.1 Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Input Low Level VIL - - 0.3VDDIO V - Output High Current (IOA[9:0], IOB[11:0]) IOH 3 6 9 mA VOH = 0.7VDDIO Output High Current (IOA[15:10],IOB[15:12]) IOH 9 18 27 mA VOH = 0.7VDDIO, High driving current @16mA Output Low Current (IOA[9:8], IOB) IOL -6 -12 -18 mA VOL = 0.3VDDIO Output Low Current (IOA[15:10],IOB[15:12]) IOL -8 -16 -24 mA VOL = 0.3VDDIO, SPI interface @16mA Output Low Current (IOA[7:0]) IOL -12 -24 -36 mA VOL = 0.3VDDIO, High sink Input Pull-Low Resister (IOA, IOB) RPL 50 100 150 K VIN = VDDIO Input Pull-High Resister (IOA, IOB) RPH 50 100 150 K VIN = VSS Internal ROSC f requency deviation ⊿F/F -3% 12M +3% HZ V33_REG = 3.3V 8.3 SAR ADC Characteristics (VDD_IOB = 3.3V, TA = 25℃) Characteristics Symbol Limit Unit Min. Typ. Max. ADC LINE_IN Input Voltage Range from IOB[7:0] VINL (Note 1) VSS-0.3 - VDD_IOB+0.3 V Resolution of ADC RESO - - 12 bits Signal-to-Noise Plus Distortion of ADC from Line in SINAD (Note 3) - 60 - dB Effective Number of Bit ENOB (Note 4) - 9.5 - bits Integral Non-Linearity of ADC INL - ±3.0 - LSB (Note 2) Differential Non-Linearity of ADC DNL - ±1.0 - LSB AD Conversion Rate FCONV - - 62.5K Hz Note1: Internal protection diodes clamp the analog input to V DD_IOB and VSS. These diodes allow the analog input to swing from (VSS -0.3V) to (V33_ADC+0.3V) without causing damage to the devices. Note3: The SINAD testing condition at VINLp -p = 0.8*V 33_ADC, FCONV = Fcpu/512 = 49MHz/256 = 192KHz, Fin=1.0KHz Sine waves at V 33_ADC = 3.0V from the IOB [7:0] input. Note4: ENOB = (SINAD-1.76)/6.02. 8.4 Audio ADC Characteristics (VDD_ADC = 3.0V, TA = 25℃) Characteristics Symbol Limit Unit Min. Typ. Max. ADC Microphone Input Voltage Range VINM VSS-0.3 - VDD_ADC+0.3 V Resolution of ADC RESO - - 16 bits Signal to noise ratio( SNR ) Boost gain = 0dB, PGA = 0 dB SINAD - 86 - dB

© Generalplus Technology Inc. Proprietary & Confidential 15 Aug. 03, 2018 Version: 1.1 Characteristics Symbol Limit Unit Min. Typ. Max. Dynamic range Boost gain = 0 dB, PGA = 0 dB DR - 86 - dB Total harmonic distortion + noise Boost gain = 0 dB, PGA = 0 dB THD+N - -63 - dB Total harmonic distortion + noise Boost gain = 21 dB, PGA = 0 dB THD+N - -63 - dB 8.5 DAC Characteristics (VDD_DAC = 5.0V, TA = 25℃) Characteristics Symbol Limit Unit Min. Typ. Max. DAC Resolution RESO - - 16 bit THD+n (4.5V @0.7W) THD+N - 1 - % Noise at No Signal SNR - -92 - dBr A Dynamic Range(-60dB) DR - -93 - dBr A

8.6 Regulator Characteristics (TA = 25℃)

Min. Typ. Max. Input Voltage VREGI 2.2 - 5.5 V Maximum Current Output (V18_REGO) IREGO - - 40 mA VDD_REGIN (Regulator in )= 4.5V, VDD (Regulator out ) <100mV Output Voltage(V18_REGO) VREGO 1.62 1.8 1.98 V Maximum Current Output (V33_REGO) IREGO - - 40 mA VDD_REGIN (Regulator in )= 4.5V, VDD (Regulator out ) <100mV Output Voltage(V33_REGO) VREGO 2.97 3.3 3.46 V Maximum Current Output (V33ADC_REGO) IREGO - - 10 mA VDD_REGIN (Regulator in )= 4.5V, VDD (Regulator out ) <100mV Output Voltage (V33ADC_REGO) VREGO 2.79 3.1 3.25 V Standby Current IRGES - 5 - uA

8.7 IOH vs VDD(VDD_IOA or VDD_IOB)

8.8 IOL vs VDD(VDD_IOA or VDD_IOB)

8.9 RPH/RPL vs VDD(VDD_IOA or VDD_IOB)

8.10 Freq_IOSC12M vs VDD

9 APPLICATION CIRCUITS

9.1 Application Circuit with Regulator and Internal 12M Oscillator

9.2 Application Circuit with Regulator and External 12M Crystal

Note1: These capacitor values are for design guidance only. The recommended 32K XTA L features are ESR=11.2~60K and CL1=CL2 =26~36pF (including PCB parasitic loading; for example, user should apply additional 20~30pF on X32I and X32O if PCB parasitic loading is 6pF)

10 PACKAGE/PAD LOCATIONS

10.1 Ordering Information

Product Number Package Type GPF8F096A-NnnV-C Chip form GPF8F096A-NnnV-QL02x Green Package – LQFP64 GPF8F096A_0001-NnnV-QL02x Green Package – LQFP64 GPF8F096A-NnnV-QL23x Green Package – LQFP48 GPF8F096A_0001-NnnV-QL23x Green Package – LQFP48 Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number).

10.2 Package Information

LQFP 64 Outline Dimensions

11 DISCLAIMER

The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnificati on provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURT HERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.

12 REVISION HISTORY

Date Revision # Description Page Aug. 03, 2018 1.1 updated signal description 6 Jun. 13, 2018 1.0 Original 24

Product Information

GPF8F096A specifications and overview.

Summary

16-bit Sound Controller

Description

16-bit Sound Controller

Source title GPF8F096A Datasheet(PDF) - Generalplus Technology Inc.

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