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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GG NOV. 17, 2010 Version 1.2 PPCCHH88AA2244AA 8--CChhaannnneell SSoouunndd CCoonnttrroolllleerr In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 NOV. 17, 2010 Version: 1.2 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 NOV. 17, 2010 Version: 1.2 8-BIT SOUND CONTROLLER 1. GENERAL DESCRIPTION The GPCH8A24A embedded with an 8-bit processor, 1M bytes ROM chip, 512 bytes working SRAM, 3 set of 12-bit timers, 32 general I/Os, and 2 set of 12-bit DAC. The microprocessor can implement software based on audio processing, functional control and others. For audio processing, melody and speech can be mixed into one output. The GPCH8A24A implement a high performance SPU voice engine to achieve 8 channel voice with ADPCM/PCM. It operates over a wide voltage range of 2.4V - 5.5V and includes Low Voltage Reset function. In addition, GPCH8A24A provide sleep mode fo r power savings. It can be awakened up from sleep mode by external interrupt source or by IOA’s state change. 2. FEATURES Working Voltage: 2.4V - 5.5V CPU Speed: 7.159MHz. F OSC = 14.318MHz (2 x CPU clock) ROM Size: 1M bytes RAM Size: 512 bytes. (programmable RAM 384 bytes) Three 12-bit timers/counters, TMA/TMB/TMC (programmable and auto-reloadable) Sleep mode to reduce power Key change wake-up function 10 IRQs & 6 NMI Interrupts Watchdog Function Low Voltage Reset: 2.2V 32 general I/Os, including 8 gener al/special I/Os (All bits are programmable) 8 bits I/O with high sink current(20mA) for LED application IOA with 1M pull low function to prevent current leakage from error key touch Two 12-bit DAC outputs (D/A output: 4mA/channel) SPU(Sound Processing Unit) engine can output audio data of 15-bit resolution with 12-bit DAC to perform high quality sound IR PWM Output 8-channel SPU engine with ADPCM/PCM wave table Tone color (Speech) with ADPCM algorithm to save memory usage 3. APPLICATION FIELD Talking Instrument Controller General Music Synthesizer Industrial Controller High-end Toy Controller Intelligent Education Toys And more
© Generalplus Technology Inc. Proprietary & Confidential 4 NOV. 17, 2010 Version: 1.2 4. BLOCK DIAGRAM 8-BIT CONTROLLER 512- bytes SRAM LVR / RESET 12-bit Timer/Counter A 12-bit Timer/Counter B 12-bit Timer/Counter C
8 Channel SPU
32 PIN GENERAL I/O PORT A,B,C, D
(IOB with SPECIAL FUNCTION) XI XO RESET IOA 0~7 IOB 0~7 IOC 0~7 DACOR 1M bytes ROM DACOL IOD 0~7
© Generalplus Technology Inc. Proprietary & Confidential 5 NOV. 17, 2010 Version: 1.2 5. SIGNAL DESCRIPTIONS Name PIN No. LQFP 128 PIN No. Type Description Pull High/Low/Float IO PORT IOA0-IOA7 49-42 90-83 I/O Bi-directional IO ports, can be wakeup pins - IOB0-IOB7 41-38, 34-31 82-79, 75-72 I/O Bi-directional IO ports - IOC0-IOC7 11-14, 6-9 41-44, 23-26 I/O Bi-directional IO ports - IOD0-IOD7 30-27, 1-4 71-68, 16-19 I/O Bi-directional IO ports - Clock Related XO 24 58 O Oscillator Crystal output - XI 23 57 I Oscillator crystal input/ROSC input Pull-low Power Pad VDD 35 76 I Positive supply for logic (from VDD3O) - VSS 10, 37 37, 78 I Ground reference for logic and I/O pins - VDD5_4, VDD5 15, 36 47, 77 I Positive supply for I/O pins(2.4~5.5 V) - VDDDAC3 16 48 I Positive supply for DAC - VSSDAC 19 51 I Ground reference for DAC - VDDREG 21 53 I Positive supply for regulator(2.4~5.5 V) - VSSREG 22 54 I Ground reference for regulator - VDD3O 20 52 O 3V power output from regulator - Others RESETB 25 65 I External reset pin(active low) Pull-high TEST 26 66 I Test mode Pull-low DACOL 18 50 O Left DAC output - DACOR 17 49 O Right DAC output - SLEEP 5 20 O Sleep indicator -
© Generalplus Technology Inc. Proprietary & Confidential 6 NOV. 17, 2010 Version: 1.2 5.1. PAD Assignment VSS VDD5_4 RESETB TEST IOC4 IOC5 IOC6 IOC7 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 IOA0 IOB1 IOB2 IOB3 IOB4 IOB5 IOB6 IOB7 IOB0 IOC1 IOC2 IOC3 IOC0 VDDDAC3 VSSDAC DACOL VSS VDD5 VDD XO XI VDDREG VDD3O VSSREG SLEEP GPCH8A24A IOD5 IOD6 IOD7 IOD4 1 DACOR IOD1 IOD2 IOD3 IOD0
© Generalplus Technology Inc. Proprietary & Confidential 7 NOV. 17, 2010 Version: 1.2 5.2. PIN Map - LQFP 128 NC NC NC NC NC 1234567891011121314151617 NC NC NC NC NC NC NC NC NC NC NC 1819202122232425 IOC0 IOC1 IOC2 IOC3 NC NC VDD5_4 IOB3 VSS VDD5 VDD IOB4 IOB5 IOB6 IOB7 VDDDAC3 81807978777675747372 NC NC NC NC NC NC NC NC NC NC NC NC IOA3 82 83 84 NC NC NC NC IOD4 IOD5 IOD7 DACOR DACOL VSSDAC VDD3O VDDREG VSSREG NC NC NC NC NC NC NC NC 92888786 89 90 91 9693 94 95 NC NC NC NC NC NC NC NC NC 128 127 126 125 124 123 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 104 105 106 IOD6 NC NC NC NC NC NC IOD0 IOD1 IOD2 IOD3 NC TEST RESETB 71706968676665 NC NC NC NC NC NC NC 100 101 102 103 26272829303132 NC NC NC NC NC SLEEP NC NC IOC4 IOC5 IOC6 IOC7 NC NC NC NC VSS NC NC NC XI XO IOB2 IOB1 IOB0 IOA7 IOA6 IOA5 IOA4 IOA1 IOA2 IOA0 GPCH8A24A LQFP128
© Generalplus Technology Inc. Proprietary & Confidential 8 NOV. 17, 2010 Version: 1.2 6. FUNCTIONAL DESCRIPTIONS 6.1. SRAM The 512-byte SRAM (including Stack) area is located in $000000~$0002FF. 6.2. ROM GPCH8A24A can be selected to use internal ROM with 1M bytes. 6.3. Low Voltage Reset The GPCH8A24A provides another significant feature, Low Voltage Reset (LVR). Without LVR, the CPU becomes unstable and malfunctions when the operating voltage drops below 2.2V. It will reset all functions to the initial operational (stable) states when the voltage drops below 2.2V by LVR. 6.4. Interrupt The GPCH8A24A has two interrupt (INT) modes: IRQ (interrupt Request) and NMI (Non-Mask Interrupt Request). The interrupt controller controls 10 IRQs an d 6 NMIs. A NMI cannot be interrupted by any other IRQs. An IRQ can be interrupted by a NMI and by a high priority IRQ. Interrupt Source Interrupt Name Priority Timer A NMI_TIMER_A NMI Timer B NMI_TIMER_B NMI Timer C NMI_TIMER_C NMI CPU_CLOCK/1024 NMI_D1024 NMI KEY NMI_KEY NMI EXT NMI_EXT NMI TIMER A IRQ_TIMER_A IRQ1 TIMER B IRQ_TIMER_B IRQ2 TIMER C IRQ_TIMER_C IRQ3 CPU_CLOCK/1024 IRQ_D1024 IRQ4 CPU_CLOCK/4096 IRQ_D4096 IRQ5 CPU_CLOCK/262144 IRQ_D262144 IRQ6 CPU_CLOCK/2097152 IRQ_D2097152 IRQ7 Interrupt Source Interrupt Name Priority KEY IRQ_KEY IRQ8 EXT IRQ_EXT IRQ9 SPU IRQ_SPU IRQ10 6.5. I/O The purpose of input and output ports is to communicate with other devices. Four programmable I/O ports are built-in, including Port A, B, and C. The PortA is a general I/O with programmable wake-up capability. In addition to general I/O function, PortB also provide some special functions in certain pins. Please refer to Special Function in PortB for more information . PortC0~7 has large sink current (20mA) for LED application. 6.5.1. I/O Configuration The following diagram represents the I/O schematic. I/O A, B, C Schematic: Register Control logic pull high pull low Pin pad Buffer(R) Data(R) Port_Data(W) Port_Buffer(W) Port_DIR(R/W) Port_ATTR(R/W) Port_Data and Port_Buffer are written into the same register but read from different node. The IOA [7:0] is the key wakeup port. To activate key wakeup function, first latch data on IOA_Data and enable the key wakeup function. Wakeup is triggered when the PortA state is different from first latched data. In addition to a general I/O port, PortB can be assigned to some special functions. A summary of PortB special functions is listed as follows. Special Function in PortB PortB Special Function Function Description Note IOB5 PWMO IR IR carrier frequency output Refer to Timer/Counter section EXT External interrupt source Negative edge trigger INT(default) IOB6 Feedback Output Works with IOB7 by adding a RC circuit between them to get an OSC to EXT interrupt IOB7 Feedback Input Schmitt Inverter Input -
© Generalplus Technology Inc. Proprietary & Confidential 9 NOV. 17, 2010 Version: 1.2 6.6. Timer/Counter (Timer A/Timer B/Timer C) Three timers are embedded in GPCH8A24A. They are Timer A, B and C. All three timers have the same behavior which includes 12-bit up-counter and a preload r egister and programmable clock source. Timer A can also be the clock source of the software channel. The clock source of each timer can be set individually. Two clock sources, including CPU clock and external clock, can be either individual or combinative to be timer’s clock source. 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 1'b0 1'b0 1'b1 1'b1 1'b1 1'b1 1'b1 1'b0 1'b0 Fcpu Fcpu 1'b1 1'b1 IOB6 1'b0 1'b0 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 TMX_SEL[2:0] TMX_CNT[11:0] TMX_DATA[11:0] Write to P_TMX_CNTL/H or TMX_CNT : FFF => 000 X = A or B or C Select Input 1 Input 2 Function Comment 000 ‘1’ ‘0’ Disable Disable 001 ‘1’ ‘0’ Disable Disable
010 FCPU IOB6 Duration count by FCPU Duration count by FCPU
011 FCPU ‘1’ Timer by FCPU Timer by FCPU
100 ‘1’ ‘0’ Disable Disable 101 ‘1’ ‘0’ Disable Disable 110 ‘1’ ‘0’ Disable Disable 111 ‘1’ ‘0’ Disable Disable 6.7. Sleep, Wakeup and Watchdog 6.7.1. Sleep and Wakeup Sleep mode is to save power by stopping clock while device is not in use. When sleep acts, the device runs from operating mode to standby mode. Waking from sleep mode will return to operating mode. 1). Sleep: After power on reset, IC starts working until a sleep command is given. When a sleep signal is accepted, IC will turn off system clock and enter sleep mode. 2). Wake-up: While an IRQ/NMI interrupt signal is generated, GPCH8A24A is waking up from sleep mode. While wake-up procedure is completed, program counter will continue to execute the next command where it left from sleep mode. 6.7.2. Watchdog The purpose of watchdog is to monitor system’s operation normally. Within a certain period of time, watchdog must be cleared. If the watchdog is not cleared, CPU assumes the program has been running into an abnormal condition and therefore, CPU will reset the system to the initial state and start running the program all over again from the beginning. It protects the system from incorrect code execution by generating a system reset when the watchdog timer overflows as a result of failure of software to clear the timer within 0.75 seconds. Watchdog function can be removed by option. 6.8. Speech and DAC The GPCH8A24A uses a high performance SPU voice engine to achieve 8-channel voice with ADPCM/PCM. The SPU also supports automatic zero-crossing concatenate function. A hardware multiplier is also embedded in this SPU for software usage. The fixed address of RAM area $0000 - $007F is designed as address pointers and a data buffer for the 8 channel speech/melody generation. There are two 12-bit D/As with 4mA driving current for audio output.
© Generalplus Technology Inc. Proprietary & Confidential 10 NOV. 17, 2010 Version: 1.2 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating ta ble may cause operational errors or damage to the device. For no rmal operational conditions see DC Electrical Characteristics. 7.2. DC Characteristics (VDD5 = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 2.4 - 3.6 V For 2-battery Operating Current IOP - 12 - mA FCPU = 7.0MHz @ 3.0V, no load, midi playing with inner Rom, DAC enabled Standby Current ISTB B - - 4.0 μA VDD = 3.0V OSC Frequency FOSC - - 15 MHZ VDD = 3.0V Input High Level VIH 0.7 VDD - VDD V - Input Low Level VIL VSS - 0.3VDD V - Audio Output Current IAUD - -3 - mA - Output High Current IOH - -5 - mA VDD = 3.0V, VOH = 2.7V Output Low Current (IOA7:0, IOB7:0, IOD7:0) IOL1 - 5 - mA VDD = 3.0V, VOL = 0.3V Output Low Current (IOC7:0) IOL2 - 13 - mA VDD = 3.0V, VOL = 0.3V Input Pull-Low Resister (IOA7:0) RPL - 1400 - KΩ VIN = VDD Input Pull-Low Resister (IOB7:0, IOC7:0, IOD7:0) RPL - 180 - KΩ VIN = VSS Input Pull-High Resister (IOA7:0, IOB7:0, IOC7:0, IOD7:0) RPH - 180 - KΩ VIN = VSS 7.3. DC Characteristics (VDD5 = 5.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 17 - mA FCPU = 7.0MHz@3.0V, no load, midi playing with inner Rom, DAC enabled Standby Current ISTB B - - 5.0 μA VDD = 5.0V OSC Frequency FOSC - - 15 MHz VDD = 5.0V Input High Level VIH 0.7 VDD - VDD V - Input Low Level VIL VSS - 0.3VDD V - Audio Output Current IAUD - -5 - mA - Output High Current IOH - -12 - mA VDD = 5.0V, VOH = 4.5V
© Generalplus Technology Inc. Proprietary & Confidential 11 NOV. 17, 2010 Version: 1.2 Limit Characteristics Symbol Min. Typ. Max. Test Condition Unit Output Low Current (IOA7:0, IOB7:0, IOD7:0) IOL1 - 13 - mA VDD = 5.0V, VOL = 0.5V Output Low Current (IOC7:0) IOL2 - 28 - mA VDD = 5.0V, VOL = 0.5V Input Pull-Low Resister (IOA7:0) RPL - 800 - KΩ VIN = VDD Input Pull-Low Resister (IOB7:0, IOC7:0, IOD7:0) RPL - 100 - KΩ VIN = VSS Input Pull-High Resister (IOA7:0,IOB7:0,IOC7:0, IOD7:0) RPH - 100 - KΩ VIN = VSS 7.4. DAC Characteristics (VDD5 = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Resolution of DAC RESO - - 12 bit THD+N (f=1kHz) SNR - 0.1 - % Noise at no signal - - -84 - dBr A Dynamic Range(-60dB) - - -75 - dBr A Sample Rate FS - - 400K Hz 7.5. Regulator Characteristics ( TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Input Voltage VREGI 2.4 4.5 5.5 V Maximum Current Output IREGO - - 30 mA Output Voltage VREGO 2.4 3 3.3 V Standby Current IRGES - 2.5 - uA 7.6. The Relationships between the ROSC and the FCPU 7.7. The Relationships between the FCPU and the IOP Fosc VS. Iop 8.00 10.00 12.00 14.00 16.00 18.00 468 1 0 1 2 1 4 Fosc (MHz) Iop (mA) 3.0V 5.0V Rosc VS. Fosc 130K, 4.29M 91K, 6.07M 68K, 8.15M 56K, 9.22M 47K, 11.52M 39K, 13.60M 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 30 50 70 90 110 130 150 Rosc (KΩ) Fosc (MHz)
© Generalplus Technology Inc. Proprietary & Confidential 12 NOV. 17, 2010 Version: 1.2 7.8. The Relationships between the IOP and the VDD 0123456 VDD(V) Iop(mA) 7.9. The Relationships between the IOH and the VDD 7.9.1. VOH = 0.9VDD 0123456 VDD(V) IOH(mA) 7.10. The Relationships between the IOL and the VDD 7.10.1. VOL = 0.1VDD 0123456 VDD(V) IOL(mA) IOA/B/D IOC
© Generalplus Technology Inc. Proprietary & Confidential 13 NOV. 17, 2010 Version: 1.2 8. APPLICATION CIRCUITS 8.1. GPCH8A24A Application Circuit with ROSC Option GPCH8A24A application circuit with Rosc option GPCH8A24A Reset RESETB VSSB 0.1u VSS VSS VSSREG VDD5 VDD5_4 VDDREG VDDB VDD3O VDD VDDDAC3 DACOL 0.22u VSSB 0.01u 470 VSSDAC 47u 10u XO XI 47K VSSB GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB 0.1u VDDB IOx IOA0~7 IOA0~7 IOB0~7 IOB0~7 IOC0~7 IOC0~7 (Battery Power)(Common Ground)(Regulator Power 3V) IOD0~7 IOD0~7 0.1u C8 * VDDB GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB C11 0.1u C12 IOx DACOR 0.22u C10 VSSB 0.01u 470 Note*: This capacitor can be removed if is is good power line layout on PCB that has no harm to the sound quality. Note: Important note to power connection: (a) Battery or Power supply connects to VDDB (including VDDREG, VDD5 and VDD5_4, 2.4V ~ 5.5V) (b) VDD3O is internal regulator output that supplies power to VDD, VDDDAC3, etc. Connect VDD3O, VDD and VDDDAC3 all together. (c) VDDB should NOT be connected to VDD3O, VDD, VDDDAC3, etc. (d) The built-in regulator can NOT be disabled, so that user should NOT bypass this regulator. (e) Recommended capacitor placement for power distribution on PCB: C1 close to battery, C2 close to VDD3O pad and C8 close to VDDDAC3 pad.
© Generalplus Technology Inc. Proprietary & Confidential 14 NOV. 17, 2010 Version: 1.2 8.2. GPCH8A24A Application Circuit with Crystal Option GPCH8A24A application circuit with XTAL option GPCH8A24A Reset RESETB VSSB 0.1u VSS VSS VSSREG VDD5 VDD5_4 VDDREG VDDB VDD3O VDD VDDDAC3 DACOL 0.22u VSSB 0.01u 470 VSSDAC 47u 10u VSSB GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB 0.1u VDDB IOx IOA0~7 IOA0~7 IOB0~7 IOB0~7 IOC0~7 IOC0~7 (Battery Power)(Common Ground)(Regulator Power 3V) IOD0~7 IOD0~7 0.1u C10 ** VDDB GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB C14 0.1u C13 20p 20p 14.318MHz XI XO DACOR 0.22u C12 VSSB C11 0.01u 470 IOx C9* C8* VSSB Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note**: This capacitor can be removed if it is good power line layout on PCB that has no harm to the sound quality. Note: Important note to power connection: (a) Battery or Power supply connects to VDDB (including VDDREG, VDD5 and VDD5_4, 2.4V ~ 5.5V) (b) VDD3O is internal regulator output that supplies power to VDD, VDDDAC3, etc. Connect VDD3O, VDD and VDDDAC3 all together. (c) VDDB should NOT be connected to VDD3O, VDD, VDDDAC3, etc. (d) The built-in regulator can NOT be disabled, so that user should NOT bypass this regulator. (e) Recommended capacitor placement for power distribution on PCB: C1 close to battery, C2 close to VDD3O pad and C10 close to VDDDAC3 pad.
© Generalplus Technology Inc. Proprietary & Confidential 16 NOV. 17, 2010 Version: 1.2 9. PACKAGE/PAD LOCATIONS 9.1. Ordering Information Product Number Package Type GPCH8A24A-NnnV-C Chip form GPCH8A24A-NnnV-QL09x Halogen Free Package Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number). 9.2. Package Information 9.2.1. LQFP 128 Dimension in Millimeter Symbol Min. Typ. Max. A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 b 0.13 0.16 0.23 c 0.09 - 0.20 D 16.00 BSC. D1 14.00 BSC. E 16.00 BSC.
© Generalplus Technology Inc. Proprietary & Confidential 17 NOV. 17, 2010 Version: 1.2 Dimension in Millimeter Symbol Min. Typ. Max. E1 14.00 BSC. e 0.40 BSC. L 0.45 0.60 0.75 L1 1.00 REF θ 0∘ 3.5∘ 7∘
© Generalplus Technology Inc. Proprietary & Confidential 18 NOV. 17, 2010 Version: 1.2 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 19 NOV. 17, 2010 Version: 1.2 11. REVISION HISTORY Date Revision # Description Page Nov. 17, 2010 1.2 Modify 7.2 & 7.3 DC Characteristics 10 2. Modify 6.3 Low voltage reset. 3. Modify 7.4 DAC Characteristics. 4. Add 7.5 Regulator Characteristics. 5. Add note in section 8.1 Application circuits. 6. Add note in section 8.2 Application circuits. 7. Modify section 8.3 Current Mode DAC Speaker Driver. 2. Add section 7. ELECTRICAL SPECIFICATIONS. Mar. 12, 2008 0.1 Original 17