DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 22
Technical content
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GG AUG. 18, 2009 Version 1.1 PPCCHH88000011BB 8--CChhaannnneell SSoouunndd CCoonnttrroolllleerr wwiitthh
51122 KKBB OOTTPP
In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 AUG. 18, 2009 Version: 1.1 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 AUG. 18, 2009 Version: 1.1 88--CChhaannnneell SSoouunndd CCoonnttrroolllleerr wwiitthh
551122 KKBB OOTTPP
- GENERAL DESCRIPTION The GPCH8001B embedded with an 8-bit processor, 512K bytes OTP ROM (or External 4M bytes maximal program ROM), 512 bytes working SRAM, 3 sets of 12-bit timer, 32 general I/Os, 1 set of 12-bit ADC with 4 channels input and 2 sets of 12-bit DAC. The microprocessor can implement software based on audio processing, functional control and others. For audio processing, melody and speech can be mixed into one output. The GPCH8001B is implemented with a high performance SPU voice engine to achieve 8-channel voice with ADPCM/PCM data. It operates over a wide voltage range from 2.2V through 5.5V, and it includes a Low Voltage Reset to assure system operating appropriately under low voltage condition. In addition, GPCH8001B provides sleep mode fo r power savings. It can be awakened from sleep mode by interrupt sources or by IOA’s state change. There is a Serial Peri pheral Interface (SPI) controller built in GPCH8001B to facilitate communicating with other devices and components. Also a SIO (Serial interface I/O) controller is featured which offers a one-bit se rial interface to communicate with other devices. 2. FEATURES Working Voltage: 2.4V - 5.5V CPU Speed: 7.159MHz. F OSC = 14.318MHz (2 x CPU clock) ROM Size: 512K bytes OTP ROM (or can connect External ROM Max. 4M bytes) RAM Size: 512 bytes (Programmable RAM 384 bytes) Three 12-bit timers/counters, TMA/TMB/TMC (Programmable and Auto Reload) Sleep mode to reduce power Key change wake-up function 13 IRQs & 7 NMI Interrupts Watchdog Function Low Voltage Reset: 2.2V 32 general I/Os, including 8 general/special I/Os (Bit Programmable) 4-bit I/O with high sink current(20mA) for LED application IOA with 1M pull low function to prevent current leakage from error key touch Two 12-bit DAC outputs (D/A output: 4mA/channel) SPU(Sound Processing Unit) engine can output audio data of 15-bit resolution with 12-bit DAC to perform high quality sound IR PWM Output 8-channel SPU engine with ADPCM/PCM wave table Generalplus ICE_CORE embedded, new Application can be developed using SunMidiar Development tools Tone color (Speech) with ADPCM algorithm to save memory usage 4-channel input of 12 bit ADC One Generalplus Serial I/O interface One SPI serial I/O interface 3. APPLICATION FIELD Talking Instrument Controller General Music Synthesizer Industrial Controller High End Toy Controller Intelligent Education Toys and more
© Generalplus Technology Inc. Proprietary & Confidential 4 AUG. 18, 2009 Version: 1.1 4. BLOCK DIAGRAM 8-BIT CONTROLLER 512- bytes SRAM LVR / RESET 12-bit Timer/Counter A 12-bit Timer/Counter B 12-bit Timer/Counter C
8 Channel SPU
32 PIN GENERAL I/O PORT A,B,C,D
(IOB with SPECIAL FUNCTION) XI XO RESET IOA 0~7 IOB 0~7 IOC 0~7 IOD 0~7 DACOL DACOR 512K bytes OTP ROM 12-bit ADC SPI SIO IOC 4~7
© Generalplus Technology Inc. Proprietary & Confidential 5 AUG. 18, 2009 Version: 1.1 5. SIGNAL DESCRIPTIONS Name Pin. No. LQFP 128 Pin No. Type Description Pull hi/low/float IO PORT IOA0~IOA7 79~72 83~90 I/O Bi-directional IO ports, can be wakeup pins - IOB0~IOB7 71~68,64~61 82~79,75~72 I/O Bi-directional IO ports - IOC0~IOC7 36~39,23~26 41~44,23~26 I/O Bi-directional IO ports - IOD0~IOD7 60~57,16~19 71~68,23~26 I/O Bi-directional IO ports - ROM/OTP Address & Data Bus interface XA0~XA21 105~94,89~80 122~111,106~97 O Address of 4M byte external rom - XD0~XD8 2~9 2~9 I/O Data bus of 4M byte external rom - ROMCSB 10 10 O Rom chip select enable(active low) - ROMWEB 11 11 O Rom write enable(active low) - ROMOEB 12 12 O Rom output enable(active low) - IROMEN 21 21 I Enable OTP(1) or external rom(0) Floating ICE related ICE_EN 28 33 I ICE enable Pull-low ICE_CLK 29 34 I ICE clock Pull-low ICE_SDA 30 35 I/O ICE serial data bus - OTP related OTP_SCK 35 40 I Serial clock for 512K byte OTP Pull-low OTP_SDA 34 39 I/O Serial data bus for 512K byte OTP - SIFEN 41 46 I Internal OTP controller enable (with serial interface) Pull-hi Clock related XO 53 58 O Oscillator Crystal output - XI 52 57 I Oscillator crystal input./ROSC input Floating R1XO 56 67 I ROSC mode(1) or Crystal mode(0) Floating in Crystal mode POWER PAD VDD 65,91,15 76,108,15 I Positive supply for logic (from VDD3O) - VSS 67,93,13,32 78,110,13,37 I Ground reference for logic and I/O pins - VDDICE 31 36 I Positive supply for logic ICE pads - VDD5, VDD5_4 66,92,14,42 77,109,14,47 I Positive supply for I/O pins(2.4~5.5 V) - VDDADC5 22 22 I Positive supply for ADC - VSSADC 27 27 I Ground reference for ADC - VDDDAC3 43 48 I Positive supply for DAC - VSSDAC 46 51 I Ground reference for DAC - VDDREG 48 53 I Positive supply for REGULATOR(2.4~5.5 V) - VSSREG 49 54 I Ground reference for REGULATOR - VDD3O 47 52 O 3V/2.5V power output from regulator - VDDOSC 51 56 I Positive supply for oscillator - VSSOSC 50 55 I Ground reference for oscillator - VPP 90 107 I OTP high voltage source for program - VPP_t 1 1 I OTP high voltage source for program in test mode
© Generalplus Technology Inc. Proprietary & Confidential 6 AUG. 18, 2009 Version: 1.1 Name Pin. No. LQFP 128 Pin No. Type Description Pull hi/low/float Others REGSEL 33 38 I Always connect to VDD5 Floating HMCUEN 40 45 I Always connect to VSS Floating RESETB 54 65 I External reset pin(active low) Pull-hi TEST 55 66 I Test pin reserved for Generalplus testing Pull-low DACOR 44 49 O Right DAC output - DACOL 45 50 O Left DAC output - SLEEP 20 20 O Sleep indicator - Total 105 pads
© Generalplus Technology Inc. Proprietary & Confidential 7 AUG. 18, 2009 Version: 1.1 5.1. PAD Assignment GPCH8001A 105 104 103 102 101 100 VPP XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 ROMCSB ROMWEB ROMOEB VSS VDD5 VDD IOD4 IOD5 IOD6 IOD7 SLEEP IROMEN VDDADC5 IOC4 IOC5 IOC6 IOC7 VSSADC ICE_EN ICE_CLK ICE_SDA VDD VSS REGSEL OTP_SDA OTP_SCK IOC0 IOC1 IOC2 IOC3 HMCUEN SIFEN VDD5_4 VDDDAC3 DACOR DACOL VSSDAC VDD3O VDDREG VSSREG VSSOSC VDDOSC XI XO IOB5 XA21 XA20 XA19 XA18 XA17 XA16 XA15 XA14 XA13 XA12 VPP VDD VDD5 VSS XA11 XA10 XA9 XA8 XA7 XA6 XA5 XA4 XA3 XA2 XA1 XA0 IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 IOB0 IOB1 IOB2 IOB3 VSS VDD5 VDD IOB4 IOB6 IOB7 IOD0 IOD1 IOD2 IOD3 R1XO TEST RESETB GPCH8001A
© Generalplus Technology Inc. Proprietary & Confidential 8 AUG. 18, 2009 Version: 1.1 5.2. PIN Map XD1 XD2 XD3 XD4 XD5 1234567891011121314151617 VPP_t XD0 XD6 XD7 ROMCSB ROMWEB ROMOEB VSS VDD5 VDD ICE_EN 1819202122232425 ICE_CLK ICE_SDA VDDICE VSS REGSEL OTP_SDA OTP_SCK IOC0 IOC1 IOC2 IOC3 HMCUEN SIFEN VDD5_4 IOA7 IOB0 IOB1 IOB2 IOB3 IOA4 IOA5 IOA6 VSS VDD5 VDD IOB4 IOB5 IOB6 IOB7 VDDDAC3 81807978777675747372 NC NC XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 IOA3 82 83 84 NC NC NC NC SLEEP IROMEN VDDADC5 IOC4 IOC5 IOD4 IOD5 IOD7 IOC6 DACOR DACOL VSSDAC VDD3O VDDREG VSSREG VSSOSC VDDOSC XI NC NC IOA1 IOA0 IOA2 NC NC NC NC 92888786 89 90 91 9693 94 95 XA11 VSS VDD5 VDD VPP XA12 XA13 XA14 XA10 128 127 126 125 124 123 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 104 105 106 IOD6 XO NC NC NC NC NC NC IOD0 IOD1 IOD2 IOD3 R1XO TEST RESETB 71706968676665 XA15 XA16 XA17 XA18 XA19 XA20 XA21 100 101 102 103 26272829303132 VSSADC NC NC NC NC IOC7 NC GPCH8001B LQFP 128
© Generalplus Technology Inc. Proprietary & Confidential 9 AUG. 18, 2009 Version: 1.1 6. FUNCTIONAL DESCRIPTIONS 6.1. SRAM The 512-byte SRAM (including Stack) area is located in $000000~$0002FF. 6.2. ROM GPCH8001B can be selected to use internal OTP ROM with 512k bytes or external ROM with maximum 4M bytes. 6.3. Low Voltage Reset The GPCH8001B provides another important feature, Low Voltage Reset (LVR). Without LVR, the CPU may become unstable and malfunctioning-when operating voltage drops below 2.2V. It will reset all functions to the initial operational (stable) states when the voltage drops below 2.2V by LVR. 6.4. Interrupt The GPCH8001B has two interrupt (INT) modes: IRQ (interrupt Request) and NMI (Non-Mask Interrupt Request). The interrupt controller controls 13 IRQs and 7 NMIs. A NMI cannot be interrupted by any other IRQs. An IRQ can be interrupted by a NMI and by a high priority IRQ. Interrupt Source Interrupt Name Priority Timer A NMI_TIMER_A NMI Timer B NMI_TIMER_B NMI Timer C NMI_TIMER_C NMI CPU_CLOCK/1024 NMI_D1024 NMI KEY NMI_KEY NMI EXT NMI_EXT NMI ADC NMI_ADC NMI TIMER A IRQ_TIMER_A IRQ1 TIMER B IRQ_TIMER_B IRQ2 TIMER C IRQ_TIMER_C IRQ3 CPU_CLOCK/1024 IRQ_D1024 IRQ4 CPU_CLOCK/4096 IRQ_D4096 IRQ5 CPU_CLOCK/262144 IRQ_D262144 IRQ6 CPU_CLOCK/2097152 IRQ_D2097152 IRQ7 KEY IRQ_KEY IRQ8 Interrupt Source Interrupt Name Priority EXT IRQ_EXT IRQ9 ADC IRQ_ADC IRQ10 SPU IRQ_SPU IRQ11 SPI IRQ_SPI IRQ12 SIO IRQ_SIO IRQ13 6.5. I/O The purpose of input and output ports is to communicate with other devices. Four programmable I/O ports are built-in, including Port A, B, C, and D. The PortA is a general I/O with programmable wake-up capability. In addition to general I/O function, PortB also offers some s pecial functions in certain pins. Refer to Special Function in PortB . PortC0~3 provides large sink current (20mA) for LED application. The Port C and Port D are sharing other module’s function such as ADC, SPI, SIO, etc. Refer to IO Share. 6.5.1. I/O configuration The following diagram represents the I/O schematic. I/O A, B, C, D Schematic: Register Control logic pull high pull low Pin pad Buffer(R) Data(R) Port_Data(W) Port_Buffer(W) Port_DIR(R/W) Port_ATTR(R/W) Port_Data and Port_Buffer are written into the same register but read from different nodes. The IOA [7:0] is the key wakeup port. To activate key wakeup function, first latch data on IOA_Data and enable the key wakeup function. Wakeup is triggered when the PortA state is different from first latched data. In addition to a general I/O port, PortB can be assigned to some special functions. A summary of PortB special functions is listed as follows. The next table lists IO sharing pins with ADC, SPI, SIO and etc. Special function in PortB PortB Special Function Function Description Note IOB5 PWMO IR IR carrier frequency output Refer to Timer/Counter section EXT External interrupt source Negative edge trigger INT(default) IOB6 Feedback Output Works with IOB7 by adding a RC circuit between them to get an OSC to EXT interrupt
© Generalplus Technology Inc. Proprietary & Confidential 10 AUG. 18, 2009 Version: 1.1 PortB Special Function Function Description Note IOB7 Feedback Input Schmitt Inverter Input - IO Share IO Pin Share IOC4 Linein 0 IOC5 Linein 1 IOC6 Linein 2 IOC7 Linein 3 IOD0 SPICSN IOD1 SPICK IOD2 SPIDO IOD3 SPIDI IOD4 SIO_SCK IOD5 SIO_SDA 6.6. Timer/Counter (Timer A/Timer B/Timer C) Three timers are embedded in GPCH8001B, Timer A, B and C. There three timers all have the same behavior which includes a 12-bit up counter and a preload r egister and programmable clock source. Timer A can also be the clock source of the software channel. The clock source of each timer can be set individually. Two clock sources including CPU clock and external clock can be selected individually or combined together for timer’s clock source. Select Input 1 Input 2 Function Comment 000 ‘1’ ‘0’ Disable Disable 001 ‘1’ ‘0’ Disable Disable
010 FCPU IOB6 Duration count by FCPU Duration count by FCPU
011 FCPU ‘1’ Timer by FCPU Timer by FCPU
100 ‘1’ ‘0’ Disable Disable 101 ‘1’ ‘0’ Disable Disable 110 ‘1’ ‘0’ Disable Disable 111 ‘1’ ‘0’ Disable Disable
© Generalplus Technology Inc. Proprietary & Confidential 11 AUG. 18, 2009 Version: 1.1 6.7. Sleep, Wakeup and Watchdog 6.7.1. Sleep and Wakeup Sleep mode is to save power by stopping clock running while device is not in use. When sl eep acts, the device runs from operating mode to standby mode. Wake-up from sleep mode means turning back to operating mode. 1). Sleep: After power on reset, IC starts working until a sleep command is given. When a sleep signal is accepted, IC will turn off system clock and enter sleep mode. 2). Wake-up: While an IRQ/NMI interrupt signal is generated, GPCH8001B is waking up from sleep mode. While wake-up completed, program counter will continue to execute the next command. 6.7.2. Watchdog The purpose of watchdog is to monitor system’s operation normally. Within a certain period, watchdog must be cleared; otherwise, CPU assumes the program has been running in an abnormal condition and therefore, CPU will reset the system to the initial state and start running the program from program’s beginning. It protects the system from incorrect code execution by generating a system reset when the watchdog timer overflows as a result of failure of software to clear the timer within 0.75 seconds. Watchdog function c an be removed by option. 6.8. Speech and DAC The GPCH8001B uses a high performance SPU voice engine to archive 8-channel voice with ADPCM/PCM. The SPU also supports automatic zero-crossing concatenating function. A hardware multiplier is also embedded in this SPU for software usage. The fixed address of RAM area $0000 - $007F is designed as address pointers and a data buffer for 8-channel speech/melody generation. There are two 12-bit D/As with 4mA driving current for DAC1 and DAC2. 6.9. Analog/Digital Converter The 12-bit general purpose anal og/digital converter (ADC) is embedded in GPCH8001B. The ADC with 4-channel input which can be selected by software programming with maximum 100KHz sampling rate. Key press interrupt generation is supported. 6.10. SPI Controller A Serial Peripheral Interface (SPI) controller is built in GPCH8001B to facilitate communicating with other devices and components. There are four control signals on SPI including SPICSN, SPICLK (SCK), SPIRX (SDI), and SPITX (SDO); the four signals are shared with PortD0, PortD1, PortD2 and PortD3. While SPI module is enabled by corresponding control bit. These four pins cannot be GPIOs and any setting on corresponding GPIO control register will have no effect. Four types of timing are supported as follows: MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX MSB MSB Master Mode, SPO = 0, SPH=0 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX Q Q Master Mode, SPO = 0, SPH=1 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX Q Master Mode, SPO = 1, SPH=0
© Generalplus Technology Inc. Proprietary & Confidential 12 AUG. 18, 2009 Version: 1.1 MSB LSB SPICLK SPICSN SPITX SPIOE 8b i t s MSB LSBSPIRX Q Q Master Mode, SPO = 1, SPH=1 6.11. Generalplus Serial IO Controller SIO (Serial interface I/O) controller is Generalplus’ serial interface, which offers a one-bit serial interface that communicates with other devices from Generalplus. This serial interface is capable of transmitting or receiving data via two I/O pins, SCK and SDA. The SCK and SDA are shared with IOD4 and IOD5 respectively.
© Generalplus Technology Inc. Proprietary & Confidential 13 AUG. 18, 2009 Version: 1.1 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating ta ble may cause operational errors or damage to the device. For no rmal operational conditions see DC Electrical Characteristics. 7.2. DC Characteristics (VDD5/VDD5_4 = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 2.2 - 3.6 V For 2-battery FCPU = 7.0MHz, no load, playing midi with inner OTP ROM, DAC enabled Operating Current IOP - - mA FCPU = 7.0MHz, no load, playing midi with AMIC flash (model: A29L040-70), DAC enabled Standby Current ISTB B - - 10.0 μA VDD5/VDD5_4 = 3.0V OSC Frequency FOSC - - 15 MHZ VDD5/VDD5_4 = 3.0V Input High Level VIH 0.7 VDD - VDD V - Input Low Level VIL VSS - 0.3VDD V - Audio Output Current IAUD - -4.3 - mA - Output High Current IOH -2.6 - - mA VDD5/VDD5_4 = 3.0V, VOH = 2.7V Output Low Current (IOA7:0, IOB7:0, IOC7:4, IOD7:0) IOL1 2.8 - - mA VDD5/VDD5_4 = 3.0V, VOL = 0.3V Output Low Current (IOC3:0) IOL2 12 - - mA VDD5/VDD5_4 = 3.0V, VOL = 0.3V Input Pull-Low Resister (PA7:0) RPL - 1800 - KΩ VIN = VDD5/VDD5_4 Input Pull-High Resister (PA7:0, PB7:0, PC7:0) RPH - 170 - KΩ VIN = VSS 7.3. DC Characteristics (VDD5/VDD5_4 = 5.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 3.6 - 5.5 V For 3-battery FCPU = 7.0MHz , no load, playing midi with inner OTP ROM, DAC enabled Operating Current IOP - - mA FCPU = 7.0MHz , no load, playing midi with AMIC flash (model:A29L040-70), DAC enabled Standby Current ISTB B - - 15.0 μA VDD5/VDD5_4 = 5.0V OSC Frequency FOSC - - 15 MHz VDD5/VDD5_4 = 5.0V
© Generalplus Technology Inc. Proprietary & Confidential 14 AUG. 18, 2009 Version: 1.1 Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Input High Level VIH 0.7 VDD - VDD V - Input Low Level VIL VSS - 0.3VDD V - Audio Output Current IAUD - -7.2 - mA - Output High Current IOH -6.0 - - mA VDD5/VDD5_4 = 5.0V, VOH = 4.5V Output Low Current (IOA7:0, IOB7:0, IOC7:4, IOD7:0) IOL1 6.0 - - mA VDD5/VDD5_4 = 5.0V, VOL = 0.5V Output Low Current (IOC3:0) IOL2 27 - - mA VDD5/VDD5_4 = 5.0V, VOL = 0.5V Input Pull-Low Resister (PA7:0) RPL - 900 - KΩ VIN = VDD5/VDD5_4 Input Pull-High Resister (PA7:0, PB7:0, PC7:0, PD7:0) RPH - 60 - KΩ VIN = VSS 7.4. DAC Characteristics (VDD5 = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Resolution of DAC RESO - - 12 bit THD+N (f=1kHz) SNR - 0.1 - % Noise at no signal - - -80 - dBr A Dynamic range(-60dB) - - -75.9 - dBr A Sample Rate FS - - 400K Hz 7.5. Regulator Characteristics ( TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Input Voltage VREGI 2.4 4.5 5.5 V Maximum Current Output IREGO - - 60 mA Output Voltage VREGO 2.4 3 3.3 V Standby Current IRGES - 7.2 - uA 7.6. ADC Characteristics (VDD5 = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Resolution of ADC RESO - - 12 bits Signal-to-Noise Plus Distortion of ADC from Line in SINAD - 58 - dB Effective Number of Bit ENOB - 9.3 - bits Integral Non-Linearity of ADC INL - ±1.0 - LSB Differential Non-Linearity of ADC DNL - ±0.6 - LSB No Missing Code - - 11 - bits AD Conversion Rate FCONV - - 100K Hz Supply Voltage VADC 2.2 5 5.5 V
© Generalplus Technology Inc. Proprietary & Confidential 15 AUG. 18, 2009 Version: 1.1 7.7. The Relationships between the ROSC and the FCPU 0 50 100 150 200 250 300 ROSC (KΩ) FCPU (MHz) 7.8. The Relationships between the FCPU and the IOP 12345678 FCPU (MHz) IOP (mA) 7.9. The Relationships between the IOP and the VDD 10.000 11.000 12.000 13.000 14.000 15.000 VDD5_4 (V) IOP (mA) 7.10. The Relationships between the I OH and the VDD 7.10.1. VOH = 0.9VDD VDD (V) IOH (mA) 7.11. The Relationships between the I OL and the VDD 7.11.1. VOL = 0.1VDD V DD (V) IOL (mA) IOA0~7 IOC0~3
© Generalplus Technology Inc. Proprietary & Confidential 16 AUG. 18, 2009 Version: 1.1 8. APPLICATION CIRCUITS 8.1. GPCH8001B Application Circuit with ROSC Option GPCH8001B application circuit with Rosc option GPCH8001B Reset RESETB VSSB 0.1u VSS VSS VSSREG VDD5 VDD5_4 VDDREG VDDB VDD3O VDD DACOL 0.22u VSSB 0.01u 470 VSSDAC 47u 10u XO XI 47K VSSB GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB 0.1u VDDB IOx IOA0~7 IOA0~7 IOB0~7 IOB0~7 IOC0~7 IOC0~7 VDDADC5 VDD5 VDD5 XA0~21 XD0~7 ROMOEB ROMCSB Address Data /OE /CE EPROM (Battery Power)(Common Ground)(Regulator Power 3V) VSS VSS IOD0~7 IOD0~7 VSSADC 0.1u C8 * GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB C12 0.1u C11 VDDB DACOR 0.22u C10 VSSB 0.01u 470 IOx VDD VDD VDDDAC3 VDDOSC REGSEL R1X0 IROMEN HMCUEN VDDB VSSB Note*: This capacitor can be removed if there is good power line layout on PCB that no harm to sound quality. Note: Important note to power connection: (a) Battery or Power supply connects to VDDB (including VDDREG, VDD5 , VDD5_4 and VDDADC5, 2.4V~5.5V) (b) VDD3O is internal regulator output that supplies power to V DD, VDDDAC3, VDDOSC, etc. Connect VDD3O, VDD, VDDDAC3 and VDDOS C all together. (c) VDDB should NOT be connected to VDD3O, VDD, VDDDAC3, VDDOSC, etc. (d) The built-in regulator can NOT be disabled, so user should NOT bypass this regulator. (e) Recommended capacitor placement for power distribution on PCB: C1 close to battery, C2 close to VDD3O pad and C8 close to VDDDAC3 pad.
© Generalplus Technology Inc. Proprietary & Confidential 17 AUG. 18, 2009 Version: 1.1 8.2. GPCH8001B Application Circuit with Crystal Option GPCH8001B application circuit with XTAL option Reset RESETB VSSB 0.1u VSS VSS VSSREG VDD5 VDD5_4 VDDREG VDDB VDD3O VDD DACOL 0.22u VSSB 0.01u 470 VSSDAC 47u 10u VSSB GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB 0.1u VDDB IOx IOA0~7 IOA0~7 IOB0~7 IOB0~7 IOC0~7 IOC0~7 IOD0~7 IOD0~7 GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB C14 0.1u C13 VDDB DACOR 0.22u C12 VSSB C11 0.01u 470 IOx XA0~21 XD0~7 ROMOEB ROMCSB Address Data /OE /CE EPROM VDDADC5 VDD5 VDD5 VSS VSS VSSADC VDD VDD VDDDAC3 VDDOSC REGSEL R1X0 IROMEN HMCUEN VDDB VSSB 20p 20p 14.318MHz XI XO VSSB C9* C8* 0.1u C10 ** Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note**: This capacitor can be removed if there is good power line layout on PCB that no harm to sound quality. Note: Important note to power connection: (a) Battery or Power supply connects to VDDB (including VDDREG, VDD5 , VDD5_4 and VDDADC5, 2.4V~5.5V) (b) VDD3O is internal regulator output that supplies power to V DD, VDDDAC3, VDDOSC, etc. Connect VDD3O, VDD, VDDDAC3 and VDDOS C all together. (c) VDDB should NOT be connected to VDD3O, VDD, VDDDAC3, VDDOSC, etc. (d) The built-in regulator can NOT be disabled, so user should NOT bypass this regulator. (e) Recommended capacitor placement for power distribution on PCB: C1 close to battery, C2 close to VDD3O pad and C10 close to VDDDAC3 pad.
© Generalplus Technology Inc. Proprietary & Confidential 19 AUG. 18, 2009 Version: 1.1 9. PACKAGE/PAD LOCATIONS 9.1. Ordering Information Product Number Package Type GPCH8001B-NnnV-C Chip form GPCH8001B-NnnV-QL09x Halogen Free Package Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number). 9.2. Package Information LQFP 128 Millimeter Symbol Min. Nom. Max. A - - 1.60 A1 0.05 - 0.15
© Generalplus Technology Inc. Proprietary & Confidential 20 AUG. 18, 2009 Version: 1.1 Millimeter Symbol Min. Nom. Max. A2 1.35 1.40 1.45 D 16.00 BCS. D1 14.00 BCS. E 16.00 BCS. E1 14.00 BCS. e 0.40 BCS. θ 0° 3.5° 7° b 0.13 0.16 0.23 c 0.09 - 0.20 L 0.45 0.60 0.75 L1 1.00 REF
© Generalplus Technology Inc. Proprietary & Confidential 21 AUG. 18, 2009 Version: 1.1 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 22 AUG. 18, 2009 Version: 1.1 11. REVISION HISTORY Date Revision # Description Page 2. Modify 7.3 DC Characteristics (VDD5 = 5.0V, TA = 25℃) JUN. 02, 2009 1.0 Original 22