GPCH4256B GENERALPLUS | Alldatasheet
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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. JAN. 19, 2009 Version 1.0 GGPPCCHH44225566BB 44--cchhaannnneell SSoouunndd CCoonnttrroolllleerr In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 JAN. 19, 2009 Version: 1.0 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 JAN. 19, 2009 Version: 1.0 4-channel Sound Controller 1. GENERAL DESCRIPTION The GPCH4256B embedded with 8-bit processor, 256K bytes ROM chip, 512 bytes working SRAM, three set of 12-bit timers, 24 general I/Os, and one 12-bit DAC. The microprocessor can implement software based on audio processing, functional control and others. For audio processing, melody and speech can be mixed into one output. The GPCH4256B implement a high performance SPU voice engine to achieve 4 channel voice with ADPCM/PCM. It operates over a wide voltage range from 2.4V through 5.5V, and it includes a low voltage reset to assure system operating appropriately under low voltage condition. In addition, GPCH4256B provides sleep mode fo r power savings. It can be awakened from sleep mode by external interrupt sources or IOA status changes. 2. FEATURES Working Voltage: 2.4V - 5.5V CPU speed: 7.159MHz F OSC = 14.318MHz (2 x CPU clock) ROM size: 256K bytes RAM size: 512 bytes. (Programmable RAM 384 bytes) Three 12-bit timers/counters, TMA/TMB/TMC (Programmable and Auto Reload) Sleep mode to save power Key change wakeup function 10 IRQs & 6 NMI Interrupts Watchdog function Low Voltage Reset Function 24 general I/Os, including 8 general/special I/Os (All bit programmable) 8-bit I/O with high sink current(20mA), especially for LED
applications
IOA with 1M pull low function to prevent current leakage from error key touch One 12-bit DAC outputs (D/A output: 4mA/channel) SPU(Sound Processing Unit) engine exports 15-bit resolution audio data with 12-bit DAC to produce high quality sound IR PWM Output 4-channel SPU engine with ADPCM/PCM wave table Tone color (Speech) with ADPCM algorithm to save memory usage 3. APPLICATION FIELD Talking instrument controller General Music synthesizer Industrial controller High end toy controller Intelligent education toys And more
© Generalplus Technology Inc. Proprietary & Confidential 4 JAN. 19, 2009 Version: 1.0 4. BLOCK DIAGRAM 8-BIT CONTROLLER 512- bytes SRAM LVR / RESET 12-bit Timer/Counter A 12-bit Timer/Counter B 12-bit Timer/Counter C
4 Channel SPU
24 PIN GENERAL I/O PORT A,B,C
(IOB with SPECIAL FUNCTION) XI XO RESET IOA 0~7 IOB 0~7 IOC 0~7 DACOL 256K bytes ROM
© Generalplus Technology Inc. Proprietary & Confidential 5 JAN. 19, 2009 Version: 1.0 5. SIGNAL DESCRIPTIONS Name PIN No. LQFP 128 PIN No. LQFP 44 PIN No. Type Description Pull hi/low/float IO PORT IOA0~IOA7 40~33 90~83 34~31, - I/O Bi-directional IO ports, can be wakeup pins - IOB0~IOB7 32~29, 25~22 82~79, 75~72 30~29, - I/O Bi-directional IO ports - IOC0~IOC7 7~10, 2~5 41~44, 23~26 6~9, - I/O Bi-directional IO ports - Clock Related XO 19 58 22 O Oscillator Crystal output - XI 18 57 21 I Oscillator crystal input/ROSC input Pull-low Power Pad VDD 26 76 26 I Positive supply for logic (from VDD3O) - VSS 6, 28 37, 78 28 I Ground reference for logic and I/O pins - VDD5_4, VDD5 11, 27 47, 77 12, 27 I Positive supply for I/O pins(2.4~5.5 V) - VDDDAC3 12 48 13 I Positive supply for DAC(from VDD3O) - VSSDAC 14 51 15 I Ground reference for DAC - VDDREG 16 53 17 I Positive supply for REGULATOR(2.4~5.5 V) - VSSREG 17 54 18 I Ground reference for regulator - VDD3O 15 52 16 O 3V power output from regulator - Others RESETB 20 65 23 I External reset pin(active low) Pull-hi TEST 21 66 24 I Test mode Pull-low DACOL 13 50 14 O Left DAC output - SLEEP 1 20 5 O Sleep indicator -
© Generalplus Technology Inc. Proprietary & Confidential 6 JAN. 19, 2009 Version: 1.0 5.1. PAD Assignment SLEEP IOC4 IOC5 IOC6 IOB5 IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 IOB0 IOB1 IOB2 IOB3 VSS VDD5 VDD IOB4 IOB6 IOB7 TEST RESETB
© Generalplus Technology Inc. Proprietary & Confidential 7 JAN. 19, 2009 Version: 1.0 5.2. PIN Map - LQFP 128 NC NC NC NC NC 1234567891011121314151617 NC NC NC NC NC NC NC NC NC NC NC 1819202122 232425 IOC0 IOC1 IOC2 IOC3 NC NC VDD5_4 IOB3 VSS VDD5 VDD IOB4 IOB5 IOB6 IOB7 VDDDAC3 81807978777675747372 NC NC NC NC NC NC NC NC NC NC NC NC IOA3 82 83 84 NC NC NC NC NC NC NC NC DACOL VSSDAC VDD3O VDDREG VSSREG NC NC NC NC NC NC NC NC 92888786 89 90 91 9693 94 95 NC NC NC NC NC NC NC NC NC 128 127 126 125 124 123 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 104 105 106 NC NC NC NC NC NC NC NC NC NC NC NC TEST RESETB 71706968676665 NC NC NC NC NC NC NC 100 101 102 103 26272829303132 NC NC NC NC NC SLEEP NC NC IOC4 IOC5 IOC6 IOC7 NC NC NC NC VSS NC NC NC XI XO IOB2 IOB1 IOB0 IOA7 IOA6 IOA5 IOA4 IOA1 IOA2 IOA0 LQFP 128
© Generalplus Technology Inc. Proprietary & Confidential 8 JAN. 19, 2009 Version: 1.0 5.3. PIN Map - LQFP 44 NC SLEEP IOC4 IOC5 IOC6 1234567891011 NC NC NC IOC7 NC NC VDD5_4 VDDDAC3 DACOL VSSDAC VDD3O VDDREG VSSREG NC NC XI XO IOB1 VSS VDD5 VDD NC IOA2 IOA3 IOB0 TEST RESETB 32313029282726252423 NC NC NC NC NC NC IOA0 IOA1 NC NC NC NC GPCH4256B LQFP 44
© Generalplus Technology Inc. Proprietary & Confidential 9 JAN. 19, 2009 Version: 1.0 6. FUNCTIONAL DESCRIPTIONS 6.1. SRAM Interrupt Source Interrupt Name Priority The 512-byte SRAM (including Stack) area is allocated in the area of $000000~$0002FF. KEY IRQ_KEY IRQ8 EXT IRQ_EXT IRQ9 SPU IRQ_SPU IRQ10 6.2. ROM 6.5. I/O Internal ROM with 256k bytes can be selected. The purpose of input and output ports is to communicate with other devices. Three programmable I/O ports are built-in: Port A, B, and C. PortA is a general I/O with programmable wakeup capability. In addition to general I/O function, PortB also offers some special functions in ce rtain pins. Please refer to Special Function in PortB. PortC[0~7] provides high sink current (20mA) for LED application. 6.3. Low Voltage Reset The GPCH4256B provides another important feature, Low Voltage Reset (LVR). Without LVR, the CPU may become unstable and malfunctioning when operating voltage drops too low. It will reset all functions to the initial operational (stable) states when the voltage drops too low by LVR. The GPCH4256B has two interrupt (INT) modes: IRQ (interrupt Request) and NMI (Non-Mask Interrupt Request). The interrupt controller controls 10 IRQs an d 6 NMIs. A NMI cannot be interrupted by any IRQs. An IRQ can be interrupted by a NMI or by a higher priority IRQ. The following diagram represents the I/O schematic. I/O A, B, C Schematic: Interrupt Source Interrupt Name Priority Timer A NMI_TIMER_A NMI Timer B NMI_TIMER_B NMI Timer C NMI_TIMER_C NMI CPU_CLOCK/1024 NMI_D1024 NMI KEY NMI_KEY NMI Register Control logic pull high pull low Pin pad Buffer(R) Data(R) Port_Data(W) Port_Buffer(W) Port_DIR(R/W) Port_ATTR(R/W) EXT NMI_EXT NMI TIMER A IRQ_TIMER_A IRQ1 Port_Data and Port_Buffer are written into the same register but read from different nodes. The IOA [7:0] is the key wakeup port. To activate key wakeup function, first latch data on IOA_Data and enable the key wakeup function. Wakeup is triggered when the PortA state is different from first latched data. In addition to a general I/O port, PortB can be assigned to some special functions. A summary of PortB special functions is listed as follows. TIMER B IRQ_TIMER_B IRQ2 TIMER C IRQ_TIMER_C IRQ3 CPU_CLOCK/1024 IRQ_D1024 IRQ4 CPU_CLOCK/4096 IRQ_D4096 IRQ5 CPU_CLOCK/262144 IRQ_D262144 IRQ6 CPU_CLOCK/2097152 IRQ_D2097152 IRQ7 Special function in PortB PortB Special Function Function Description Note IOB5 PWMO IR IR carrier frequency output Refer to Timer/Counter section EXT External interrupt source Negative edge trigger INT(default) IOB6 Feedback Output Works with IOB7 by adding a RC circuit between them to get an OSC to EXT interrupt IOB7 Feedback Input Schmitt Inverter Input -
© Generalplus Technology Inc. Proprietary & Confidential 10 JAN. 19, 2009 Version: 1.0 6.6. Timer/Counter (Timer A/Timer B/Timer C) Three timers are embedded in GPCH4256B, TimerA, B and C. All three timers have the same behavior which includes 12-bit up counter and a preload register and programmable clock source. Timer A can also be the clock source of the software channel. The clock source of each timer can be set individually. Two clock sources including CPU clock and external clock can be selected individually or combined together for timer’s clock source. Select Input 1 Input 2 Function Comment 000 ‘1’ ‘0’ Disable Disable 001 ‘1’ ‘0’ Disable Disable
010 FCPU IOB6 Duration count by FCPU Duration count by FCPU
011 FCPU ‘1’ Timer by FCPU Timer by FCPU
100 ‘1’ ‘0’ Disable Disable 101 ‘1’ ‘0’ Disable Disable 110 ‘1’ ‘0’ Disable Disable 111 ‘1’ ‘0’ Disable Disable 6.7. Sleep, Wakeup and Watchdog 6.7.1. Sleep and Wakeup Sleep mode is to save power by stopping clock running while device is not in use. When sleep mode acts, the device runs from operating mode to standby mode. Wake-up from sleep means turning back to operating mode. 1). Sleep: After power on reset, IC starts working until a sleep command is given. When a sleep signal is accepted, IC will turn off system clock and enter sleep mode. 2). Wake-up: While an IRQ/NMI interrupt signal is generated, GPCH4256B is awaking from sleep mode. While wake-up completed, program counter will continue to execute the next command. 6.7.2. Watchdog The purpose of watchdog is to monitor system’s operation normally. Within a certain period, watchdog must be cleared; otherwise, CPU assumes the program has been running in an abnormal condition and therefore, CPU will reset the system to the initial state and start running the program from the beginning. It protects the system from incorrect code execution by generating a system reset when the watchdog timer overflows as a result of failure of software to clear the timer within 0.75 seconds. Watchdog function can be removed by option. 6.8. Speech and DAC The GPCH4256B uses a high performance SPU voice engine to archive 4-channel voice with ADPCM/PCM. The SPU also supports automatic zero-crossing concatenating function. A hardware multiplier is also embedded in this SPU for software use. The fixed address of RAM area $0000 - $007F is designed as address pointers and a data buffer for the 8 channel speech/melody generation. There is one 12-bit D/A with 4mA driving current for audio output.
© Generalplus Technology Inc. Proprietary & Confidential 11 JAN. 19, 2009 Version: 1.0 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating ta ble may cause operational errors or damage to the device. For no rmal operational conditions see DC Electrical Characteristics. 7.2. DC Characteristics (VDD5/VDD5_4 = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 2.4 - 3.6 V For 2-battery Operating Current IOP - 9 - mA FCPU = 7.0MHz , no load, midi playing with inner ROM Standby Current ISTB B - - 4.0 μA VDD5/VDD5_4 = 3.0V OSC Frequency FOSC - - 15 MHZ VDD5/VDD5_4 = 3.0V Input High Level VIH 0.7 VDD - VDD V - Input Low Level VIL VSS - 0.3VDD V - Audio Output Current IAUD - -5.0 - mA - Output High Current IOH -4.3 - - mA VDD5/VDD5_4 = 3.0V, VOH = 2.7V Output Low Current (IOA7:0, IOB7:0) IOL1 4.8 - - mA VDD5/VDD5_4 = 3.0V, VOL = 0.3V Output Low Current (IOC7:0) IOL2 10 - - mA VDD5/VDD5_4 = 3.0V, VOL = 0.3V Input Pull-Low Resister (PA7:0) RPL - 1500 - KΩ VIN = VDD5/VDD5_4 Input Pull-High Resister (PA7:0, PB7:0, PC7:0) RPH - 180 - KΩ VIN = VSS 7.3. DC Characteristics (VDD5/VDD5_4 = 5.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 10 - mA FCPU = 7.0MHz, no load, midi playing with inner ROM Standby Current ISTB B - - 5.0 μA VDD5/VDD5_4 = 5.0V OSC Frequency FOSC - - 15 MHz VDD5/VDD5_4 = 5.0V Input High Level VIH 0.7 VDD - VDD V - Input Low Level VIL VSS - 0.3VDD V - Audio Output Current IAUD - -8 - mA - Output High Current IOH -10.0 - - mA VDD5/VDD5_4 = 5.0V, VOH = 4.5V Output Low Current (IOA7:0, IOB7:0) IOL1 11 - - mA VDD5/VDD5_4 = 5.0V, VOL = 0.5V
© Generalplus Technology Inc. Proprietary & Confidential 12 JAN. 19, 2009 Version: 1.0 Limit Characteristics Symbol Min. Typ. Max. Test Condition Unit Output Low Current (IOC7:0) IOL2 24 - - mA VDD5/VDD5_4 = 5.0V, VOL = 0.5V Input Pull-Low Resister (PA7:0) RPL - 810 - KΩ VIN = VDD5/VDD5_4 Input Pull-High Resister (PA7:0, PB7:0, PC7:0) RPH - 105 - KΩ VIN = VSS 7.4. DAC Characteristics (VDD5 = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Resolution of DAC RESO - - 12 bit THD+N (f=1kHz) SNR - 0.1 - % Noise at no signal - -84 - dBr A Dynamic Range(-60dB) - -75 - dBr A Sample Rate FS - - 400K Hz 7.5. Regulator Characteristics ( TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Input Voltage VREGI 2.4 4.5 5.5 V Maximum Current Output IREGO - - 30 mA Output Voltage VREGO 2.4 3 3.3 V Standby Current IRGES - 2.5 - uA 7.6. The Relationships between the ROSC and the FCPU Rosc VS. Fosc 39K, 14.22M 47K, 11.77M 56K, 9.92M 68K, 8.17M 91K, 6.16M 130K, 4.36M 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 30 50 70 90 110 130 150 Rosc (K Ω) Fosc (MHz) 7.7. The Relationships between the FCPU and the IOP Fosc VS. Iop 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 468 1 0 1 2 1 4 Fosc (MHz) Iop (mA) 3.0V 5.0V
© Generalplus Technology Inc. Proprietary & Confidential 13 JAN. 19, 2009 Version: 1.0 7.8. The Relationships between the IOP and the VDD 0123456 VDD(V) IOP(mA) 7.9. The Relationships between the IOH and the VDD 7.9.1. VOH = 0.9VDD 0123456 VDD(V) IOH(mA) IOA0~7 7.10. The Relationships between the I OL and the VDD 7.10.1. V OL = 0.1VDD 0123456 VDD(V) IOL(mA) IOA0~7 IOC0~7
© Generalplus Technology Inc. Proprietary & Confidential 14 JAN. 19, 2009 Version: 1.0 8. APPLICATION CIRCUITS 8.1. GPCH4256B Application Circuit with ROSC Option GPCH4256A application circuit with Rosc option GPCH4256A Reset RESETB VSSB 0.1u VSS VSS VSSREG VDD5 VDD5_4 VDDREG VDDB VDD3O VDD VDDDAC3 DACOL 0.22u VSSB 0.01u 470 (Battery Power)(Common Ground)(Regulator Power 3V) VSSDAC IOA0~7 IOA0~7 47u IOB0~7 IOB0~7 IOC0~7 IOC0~7 VSSB 10u XO XI 47K GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB 0.1u VDDB IOx 0.1u C8 * GPCH4256B GPCH4256B Note*: This capacitor can be removed if there is good power line layout on PCB that no harm to sound quality. Note: Important note to power connection: (a) Battery or Power supply connects to VDDB (including VDDREG, VDD5 and VDD5_4, 2.4V ~ 5.5V) (b) VDD3O is internal regulator output that supplies power to VDD, VDDDAC3, etc. Connect VDD30, VDD and VDDDAC3 all together. (c) VDDB should NOT be connected to VDD3O, VDD, VDDDAC3, etc. (d) The built-in regulator can NOT be disabled, so user should NOT bypass this regulator. (e) Recommended capacitor placement for power distribution on PCB: C1 close to battery, C2 close to VDD3O pad and C8 close to VDDDAC3 pad.
© Generalplus Technology Inc. Proprietary & Confidential 15 JAN. 19, 2009 Version: 1.0 8.2. GPCH4256B Application Circuit with Crystal Option GPCH4256A application circuit with XTAL option GPCH4256A Reset RESETB VSSB 0.1u VSS VSS VSSREG VDD5 VDD5_4 VDDREG VDDB VDD3O VDD VDDDAC3 DACOL 0.22u VSSB 0.01u 470 (Battery Power) (Common Ground) (Regulator Power 3V) VSSDAC IOA0~7 IOA0~7 47u IOB0~7 IOB0~7 IOC0~7 IOC0~7 VSSB 10u GPY0030B SPN SPP VSS INN VDD CE VREF ACIN 47u Speaker VSSB 0.1u VDDB IOx 20p 20p 14.318MHz XI XO VSSB C9* C8* 0.1u C10 ** GPCH4256B GPCH4256B Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note**: This capacitor can be removed if there is good power line layout on PCB that no harm to sound quality. Note: Important note to power connection: (a) Battery or Power supply connects to VDDB (including VDDREG, VDD5 and VDD5_4, 2.4V ~ 5.5V) (b) VDD3O is internal regulator output that supplies power to VDD, VDDDAC3, etc. Connect VDD30, VDD and VDDDAC3 all together. (c) VDDB should NOT be connected to VDD3O, VDD, VDDDAC3, etc. (d) The built-in regulator can NOT be disabled, so user should NOT bypass this regulator. (e) Recommended capacitor placement for power distribution on PCB: C1 close to battery, C2 close to VDD3O pad and C10 close to VDDDAC3 pad.
© Generalplus Technology Inc. Proprietary & Confidential 17 JAN. 19, 2009 Version: 1.0 9. PACKAGE/PAD LOCATIONS 9.1. Ordering Information Product Number Package Type GPCH4256B-NnnV-C Chip form GPCH4256B-NnnV-QL09x Halogen Free Package GPCH4256B-NnnV-QL01x Halogen Free Package Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number). Note4: LQFP44 only bonds 10 IO pads, so IR carrier/External interrupt/RC Feedback function is not supported. 9.2. Package Information 9.2.1. LQFP 128-QL09 Dimension in Millimeter Symbol Min. Typ. Max. A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 b 0.13 0.16 0.23 c 0.09 - 0.20 D 16.00 BSC.
© Generalplus Technology Inc. Proprietary & Confidential 18 JAN. 19, 2009 Version: 1.0 Dimension in Millimeter Symbol Min. Typ. Max. D1 14.00 BSC. E 16.00 BSC. E1 14.00 BSC. e 0.40 BSC. L 0.45 0.60 0.75 L1 1.00 REF θ 0∘ 3.5∘ 7∘ 9.2.2. LQFP 44-QL01 Dimension in Millimeter Symbol Min. Nom. Max. A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 c1 0.09 - 0.16 D 12.00 BSC D1 10.00 BSC E 12.00 BSC E1 10.00 BSC e 0.80 BSC b 0.30 0.37 0.45 L 0.45 0.60 0.75 L1 1.00 REF θ° 0° 3.5° 7°
© Generalplus Technology Inc. Proprietary & Confidential 19 JAN. 19, 2009 Version: 1.0 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 20 JAN. 19, 2009 Version: 1.0 11. REVISION HISTORY Date Revision # Description Page Jan. 19, 2009 1.0 Original 20