GPCE4096A-NnnV-QL02x | DigiCamel IC Datasheet

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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authoriz ed for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the exp ress written approval of Generalplus. DATA SHEET Jun. 26, 2017 Version 1.1 GGPPCCEE44XXXXXXXX 16-bit Sound Controller

1 GENERAL DESCRIPTION

GPCE4xxxx, a 16-bit architecture sound controller with USB interface, features the newest 16-bit microprocessor, ’nSP2.0™ (pronounced as micro-n-SP 2.0). This high processing speed assures the ’nSP2.0™ is capable of handling complex digital signal processes easily and rapidly. Therefore, GPCE4xxxx is applicable for the areas of digital sound process and voice recognition. The operating voltage of 2.4V through 5.5V and speed up to 48MHz yield the GPCE4xxxx to be easily used in varieties of application s. The memory capacity includes ROM (or OTP) plus a 4K-word working SRAM and 2K -word Cache RAM (also can be working RAM) . Other feat ures includ ing 48 programmable multi -functional I/Os, five 16-bit timers/counters, 32768Hz Real Time Clock, Low Voltage Res et/Detection, eight channels 12-bit ADC (one channel built-in MIC amplifier with auto gain controller), capacitive touch sensor, one SPI flash controller, one 16-bit DAC with push-pull amplifier and many others.

2 FEATURES

 16-bit ’nSP2.0™ microprocessor  CPU Clock: max. 48MHz  Operating Voltage: 2.4V - 5.5V  Power regulator built-in with input voltage: 2.4~5.5V, output voltage: 2.4~3.3V  IO PortA & B & C Operating Voltage: 2.4V - 5.5V  Fast speed OTP or ROM (by body)  4K-word working SRAM  2K-word cache SRAM (also can be released to working-RAM)  Total 384-byte buffer RAM  Software-based audio processing  Two sets of 14-bit software channel with noise filter, mixer and scalar to play high quality sound  Standby mode for power saving  Total five 16-bit timers, including three general-purpose 16-bit timers/counters, two touch-sensing timers (also can released for general-purpose use).  One 14-bit DAC with push-pull amplifier. Supports cascade mode as well as stereo mode  48 general I/Os (bit programmable)  Key wakeup function (IOA0 - 15, IOB0-15, IOC0-15)  Capacitor touch-sensing hardware for 48 I/O  PLL feature for system clock  32768Hz Real Time Clock (RTC), crystal or internal resistor oscillator selected.  Eight channels 12-bit AD converter, Built-in microphone amplifier and AGC or PGA function selected  Low voltage reset and low voltage detection  Watchdog Enable (option)  Two SPI serial interface I/Os. One is SPI flash controller which supports one-I/O, two-I/O, four-I/O modes and support auto read/program mode. The other is normal SPI interface.  Supports USB 2.0 full speed (12MHz) compliant device with built-in transceiver (by body option)

3 APPLICATION FIELD

 Voice Recognition Products  Intelligent Interactive Talking Toys  Advanced Educational Toys  Kids Learning Products  Kids Storybook  General Speech Synthesizer  Long Duration Audio Products  Recording / Playback Products

4 BLOCK DIAGRAM

un'SP 16-bits CPU AD Converter MIC 16-bits Counter/Timer / Interrupt General I/O Port 4K(word) Working SRAM PLL / System clock / Reset Function Memory Mapping & Control X32I X32O IOA[15:0] IOB[15:0] MICIP MICIN RESETB OTP/ROM / GPIO Special Function TimeBase/WatchDog / PWMIO output SPI flash controller MICO OPI AGC VMIC VADREF Push Pull DAC AUDP Regulator AUDN ACIN IOC[15:0] Touch sensing 2K(word) Cache SRAM SPI2 USB Device Controller (by body) USB_DN (by body) USB_DP (by body)

5 GPCE4XXXX SERIES AND DIFFERENT FEATURES LIST

Body GPCE4P096UA GPCE4096UA GPCE4096A GPCE4064A Max. CPU clock 48MHz 48MHz 48MHz 48MHz RAM Size 6K-Word (include cache) 6K-Word (include cache) 6K-Word (include cache) 6K-Word (include cache) Cache Size 2K-Word 2K-Word 2K-Word 2K-Word ROM/OTP type OTP ROM ROM ROM ROM/OTP Size 48K-Word 48K-Word 48K-Word 32K-Word IO Port 48 (IOA/B/C) 48 (IOA/B/C) 48 (IOA/B/C) 48 (IOA/B/C) SPI 2 2 2 2 USB Device Controller Yes Yes No No

6 SIGNAL DESCRIPTIONS

6.1 GPCE4P096UA

6.1.1 Pin descriptions

PORT A, Port B IOA [15:0] I/O IOA[15:0]: bi-directional I/O ports It can be programmed as wakeup I/O pins. IOB [15:0] I/O IOB [15:0]: bi-directional I/O ports. IOB[15] is shared with serial data port of OTP controller IOB[14] is shared with serial clock input port of OTP controller It can be programmed as wakeup I/O pins. IOB[11] is shared with ADC OP AMP output IOB[10] is shared with ( OPI) ADC MIC amplifier output (refer to application circuit) IOB[9] is shared with ADC OPI Audio amplifier negative input (refer to application circuit) IOB[8] is shared with ADC AGC by pass filter (refer to application circuit) IOC [15:0] I/O IOC [15:0]: bi-directional I/O ports. It can be programmed as wakeup I/O pins. Power & GND VDD_IOA P Power VDD for Port A VSS_IOA G Power GND for Port A VDD_IOB P Power VDD for Port B VSS_IOB G Power GND for Port B VDD_IOC P Power VDD for Port C VSS_IOC G Power GND for Port C V33_ADC P Power VDD for AD (3.3V) VSS_ADC G Power GND for AD V33_REG P 3V Power output from regulator V27_REG P 2.7V Power output from regulator VDD_REG P Power supply for regulator (2.4V~5.5V) VSS_REG G Ground reference for regulator VDD_DAC P Positive 5V supply for push-pull DAC VDD_PDAC P Positive 5V supply for push-pull DAC post driver VSS_PDAC G Ground reference for push-pull DAC post driver VDD_USB P Power for USB VSS_USB G Ground for USB CLK SYSTEM/ ICE INTERFACE X32KI I 32K Oscillator crystal input/ R32K OSCI X32KO O 32K Oscillator crystal output OPTION TEST I TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low) DAC AUDP O Audio output of push pull DAC AUDN O Audio output of push pull DAC ACIN U Audio analog mixer in ADC

© Generalplus Technology Inc. Proprietary & Confidential 8 Jun. 26, 2017 Version: 1.1 Mnemonic Type Description MICP I MIC amplifier input positive (Internal Floating) MICN I MIC amplifier input negative (refer to application circuit) VMIC O Microphone power supply VADREF O AVREF_DA reference pin PLL VCOIN I PLL6M low pass filter input Other Signal RESETB I System reset pin (active low) (internal 47Kohm pull high resistor) VPP I OTP program VPP pin EPM I Program enable pin USB USB_DP I/O USB DP pin of USBPHY USB_DM I/O USB DM pin of USBPHY Auto Trim FUSE VFSOURCE I Trimming Power PAD for IROSC6M

6.1.2 LQFP128 Package Pin Assignment

IOB [0] IOB [1] 1234567891011121314151617 NC NC IOB [2] IOC [3] 1819202122232425 IOC[8] VDD_DAC AUDP VSS_ PDAC ACIN 81807978777675747372 82 83 84 92888786 89 90 91 9693 94 95 128 127 126 125 124 123 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 104 105 106 71706968676665 100 101 102 103 26272829303132 IOB [3] IOB [4] IOB [5] IOB [6] IOB [7] IOB [8] IOB [9] IOB [10] IOB [11] VDD_IOB VSS_IOB IOB [12] IOB [13] IOB [14] IOB [15] IOC [0] IOC [1] IOC [2] IOC[9] IOC[4] IOC[5] IOC[6] IOC[7] VSS_IOC VDD_IOC IOC[13] IOC[10] IOC[11] IOC[12] IOC[14] USB_DM VSS_USB IOC[15] USB_DP VFSOURCE IOA[0] VDD_USB IOA[5] IOA[6] IOA[7] IOA[1] IOA[3] IOA[2] IOA[4] IOA[8] NC NC NC IOA[9] NC NC NC NC VDD_IOA NC NC VSS_IOA IOA[11] IOA[12] IOA[10] IOA[13] IOA[15] IOA[14] VDD_PDAC NC VSS_ PDAC AUDN NC NC NC NC NC NC NC NC NC NC NC VDD_REG V33_REG VSS_REG V27_REG EPM VCOIN RESETB X32KO X32KI TEST VSS_ADC V33_ADC VMIC VADREF MICN MICP NC NC NC NC NC NC NC NC NC NC NC NC NC VPP NC NC NC NC NC GPCE4P096UA LQFP128 NC

6.1.3 LQFP80 Package Pin Assignment

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 IOB[10] IOB[11] VFSOURCE VDD_USB USB_DP USB_DM IOC[6] IOC[5] IOC[4] IOB[15] IOB[2] IOB[3] IOB[8] IOB[9] VDD_IOB VSS_IOB IOB[14] IOB[13] IOB[12] IOC[7] IOB[4] IOB[5] IOB[6] IOB[7] VDD_IOC IOC[8] IOC[9] VSS_USB GPCE4P096UA LQFP80 VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN EPM V27_REG V33_REG VSS_REG 20IOB[1] IOB[0] 37 38 39 IOC[3] IOC[1] IOC[0] IOA[2] IOA[1] IOA[0]

56 IOA[3]

IOA[6] IOA[5] IOA[4]

60 IOA[7]

72 71 70 69 68 67 66 65 64 63 62 61 IOA[8] IOA[10] VSS_IOA VDD_IOA IOA[9] IOA[11] IOA[12] IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC 76 737475 AUDP VDD_DAC VDD_PDAC AUDN 80 777879 VSS_PDAC VPP IOC[2] NC NC NC NC

6.1.4 LQFP64 Package Pin Assignment

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IOB[8] IOB[9] IOA[5] IOA[4] IOA[3] IOA[2] IOA[8] IOA[7] IOA[6] USB_DM VSS_USB IOB[15] IOB[14] 60 59 58 57 56 55 54 53 52 51 50 49

48 IOA[9]

VDD_IOA IOA[12] IOA[11] IOA[10] VSS_IOA IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC AUDP VDD_DAC VDD_PDAC AUDN VSS_PDAC VPPIOB[0] IOB[1] IOB[6] IOB[7] IOB[10] IOB[11] VDD_IOB IOB[12] IOB[13] USB_DP IOB[2] IOB[3] IOB[4] IOB[5] VDD_USB VFSOURCE IOA[0] IOA[1] GPCE4P096UA LQFP64 VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN EPM V27_REG V33_REG VSS_REG

6.1.5 QFN64 Package Pin Assignment

VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN EPM V27_REG V33_REG VSS_REG 17 18 19 20 21 22 24 25 27 28 29 30 31 IOB[8] IOB[9] IOA[5] IOA[4] IOA[3] IOA[2] IOA[8] IOA[7] IOA[6] USB_DM VSS_USB IOB[15] IOB[14] 60 59 58 57 56 55 54 53 52 51 50 49 VDD_IOA IOA[12] IOA[11] IOA[10] VSS_IOA IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC AUDP VDD_DAC VDD_PDAC AUDN VSS_PDAC VPPIOB[0] IOB[1] IOB[6] IOB[7] IOB[10] IOB[11] VDD_IOB IOB[12] IOB[13] USB_DP IOB[2] IOB[3] IOB[4] IOB[5] VDD_USB VFSOURCE IOA[0] IOA[1] GPCE4P096UA QFN64 23 26

6.1.6 LQFP48 Package Pin Assignment

2VDD_REG 3V33_REG 4VSS_REG 5EPM 6VCOIN6M 7RESETB 8X32KO 9X32KI 10TEST 11IOB[0] 12IOB[1] 13IOB[2] 14IOB[3] 15IOB[4] 16IOB[5] 17IOB[6] 18IOB[8] 19IOB[9] 20IOB[10] 21VDD_IOB 22IOB[12] 23IOB[13] 24IOB[14]

25 IOB[15]

26 MICP

27 MICN

28 VADREF

29 VMIC

30 V33_ADC

31 V27_REG

32 VFSOURCE

33 IOA[0]

34 IOA[1]

35 IOA[8]

36 VDD_IOA

37 VSS_IOA

38 IOA[10]

39 IOA[11]

40 IOA[12]

41 IOA[13]

42 IOA[14]

43 IOA[15]

44 VSS_PDAC

45 AUDP

46 VDD_DAC

47 VDD_PDAC

48 AUDN

13 14 15 16 17 18 19 20 21 22 23 24 GPCE4P096UA LQFP48

6.2 GPCE4096UA

6.2.1 Pin descriptions

PORT A, Port B IOA [15:0] I/O IOA[15:0]: bi-directional I/O ports It can be programmed as wakeup I/O pins. IOB [15:0] I/O IOB [15:0]: bi-directional I/O ports. It can be programmed as wakeup I/O pins. IOB[11] is shared with ADC OP AMP output IOB[10] is shared with ( OPI) ADC MIC amplifier output (refer to application circuit) IOB[9] is shared with ADC OPI Audio amplifier negative input (refer to application circuit) IOB[8] is shared with ADC AGC by pass filter (refer to application circuit) IOC [15:0] I/O IOC [15:0]: bi-directional I/O ports. It can be programmed as wakeup I/O pins. Power & GND VDD_IOA P Power VDD for Port A VSS_IOA G Power GND for Port A VDD_IOB P Power VDD for Port B VSS_IOB G Power GND for Port B VDD_IOC P Power VDD for Port C VSS_IOC G Power GND for Port C V33_ADC P Power VDD for AD (3.3V) VSS_ADC G Power GND for AD V33_REG P 3V Power output from regulator V27_REG P 2.7V Power output from regulator VDD_REG P Power supply for regulator (2.4V~5.5V) VSS_REG G Ground reference for regulator VDD_DAC P Positive 5V supply for push-pull DAC VDD_PDAC P Positive 5V supply for push-pull DAC post driver VSS_PDAC G Ground reference for push-pull DAC post driver VDD_USB P Power for USB VSS_USB G Ground for USB CLK SYSTEM/ ICE INTERFACE X32KI I 32K Oscillator crystal input/ R32K OSCI X32KO O 32K Oscillator crystal output OPTION TEST I TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low) DAC AUDP O Audio output of push pull DAC AUDN O Audio output of push pull DAC ACIN U Audio analog mixer in ADC MICP I MIC amplifier input positive (Internal Floating) MICN I MIC amplifier input negative (refer to application circuit) VMIC O Microphone power supply

© Generalplus Technology Inc. Proprietary & Confidential 15 Jun. 26, 2017 Version: 1.1 Mnemonic Type Description VADREF O AVREF_DA reference pin PLL VCOIN I PLL6M low pass filter input Other Signal RESETB I System reset pin (active low) (internal 47Kohm pull high resistor) USB USB_DP I/O USB DP pin of USBPHY USB_DM I/O USB DM pin of USBPHY Auto Trim FUSE VFSOURCE I Trimming Power PAD for IROSC6M

6.2.2 LQFP128 Package Pin Assignment

IOB[0] IOB[1] 1234567891011121314151617 NC NC IOB[2] IOC[3] AUDN 1819202122232425 IOC[8] VDD_DAC AUDP VSS_PDAC ACIN 81807978777675747372 82 83 84 92888786 89 90 91 9693 94 95 128 127 126 125 124 123 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 104 105 106 71706968676665 100 101 102 103 26272829303132 IOB[3] IOB[4] IOB[5] IOB[6] IOB[7] IOB[8] IOB[9] IOB [10] IOB [11] VDD_IOB VSS_IOB IOB [12] IOB [13] IOB [14] IOB [15] IOC[0] IOC[1] IOC[2] IOC[9] IOC[4] IOC[5] IOC[6] IOC[7] VSS_IOC VDD_IOC IOC[13] IOC[10] IOC[11] IOC[12] IOC[14] USB_DM VSS_USB IOC[15] USB_DP NC IOA[0] VDD_USB IOA[5] IOA[6] IOA[7] IOA[1] IOA[3] IOA[2] IOA[4] IOA[8] NC NC NC IOA[9] NC NC NC NC VDD_IOA NC NC VSS_IOA IOA[11] IOA[12] IOA[10] IOA [13] IOA[15] IOA[14] VDD_PDAC NC VSS_PDAC AUDN NC NC NC NC NC NC NC NC NC NC NC VDD_REG V33_REG VSS_REG V27_REG EPM VCOIN RESETB X32KO X32KI TEST VSS_ADC V33_ADC VMIC VADREF MICN MICP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GPCE4096UA LQFP128 NC VFSOURCE

6.2.3 LQFP80 Package Pin Assignment

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 IOB[10] IOB[11] VFSOURCE VDD_USB USB_DP USB_DM IOC[6] IOC[5] IOC[4] IOB[15] IOB[2] IOB[3] IOB[8] IOB[9] VDD_IOB VSS_IOB IOB[14] IOB[13] IOB[12] IOC[7] IOB[4] IOB[5] IOB[6] IOB[7] VDD_IOC IOC[8] IOC[9] VSS_USB GPCE4096UA LQFP80 VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN NC V27_REG V33_REG VSS_REG 20IOB[1] IOB[0] 37 38 39 IOC[3] IOC[1] IOC[0] IOA[2] IOA[1] IOA[0] IOA[6] IOA[5] IOA[4] 72 71 70 69 68 67 66 65 64 63 62 61 IOA[8] IOA[10] VSS_IOA VDD_IOA IOA[9] IOA[11] IOA[12] IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC 76 737475 AUDP VDD_DAC VDD_PDAC AUDN 80 777879 VSS_PDAC NC IOC[2] NC NC NC NC

6.2.4 LQFP64 Package Pin Assignment

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IOB[8] IOB[9] IOA[5] IOA[4] IOA[3] IOA[2] IOA[8] IOA[7] IOA[6] USB_DM VSS_USB IOB[15] IOB[14] 60 59 58 57 56 55 54 53 52 51 50 49 VDD_IOA IOA[12] IOA[11] IOA[10] VSS_IOA IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC AUDP VDD_DAC VDD_PDAC AUDN VSS_PDAC NCIOB[0] IOB[1] IOB[6] IOB[7] IOB[10] IOB[11] VDD_IOB IOB[12] IOB[13] USB_DP IOB[2] IOB[3] IOB[4] IOB[5] VDD_USB VFSOURCE IOA[0] IOA[1] GPCE4096UA LQFP64 VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN NC V27_REG V33_REG VSS_REG

6.2.5 QFN64 Package Pin Assignment

VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN NC V27_REG V33_REG VSS_REG 17 18 19 20 21 22 24 25 27 28 29 30 31 IOB[8] IOB[9] IOA[5] IOA[4] IOA[3] IOA[2] IOA[8] IOA[7] IOA[6] USB_DM VSS_USB IOB[15] IOB[14] 60 59 58 57 56 55 54 53 52 51 50 49 VDD_IOA IOA[12] IOA[11] IOA[10] VSS_IOA IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC AUDP VDD_DAC VDD_PDAC AUDN VSS_PDAC NCIOB[0] IOB[1] IOB[6] IOB[7] IOB[10] IOB[11] VDD_IOB IOB[12] IOB[13] USB_DP IOB[2] IOB[3] IOB[4] IOB[5] VDD_USB VFSOURCE IOA[0] IOA[1] GPCE4096UA QFN64 23 26

6.2.6 LQFP48 Package Pin Assignment

2VDD_REG 3V33_REG 4VSS_REG 5EPM 6VCOIN6M 7RESETB 8X32KO 9X32KI 10TEST 11IOB[0] 12IOB[1] 13IOB[2] 14IOB[3] 15IOB[4] 16IOB[5] 17IOB[6] 18IOB[8] 19IOB[9] 20IOB[10] 21VDD_IOB 22IOB[12] 23IOB[13] 24IOB[14] 13 14 15 16 17 18 19 20 21 22 23 24 GPCE4096UA LQFP48

6.3 GPCE4096A/GPCE4064A

6.3.1 Pin descriptions

PORT A, Port B IOA [15:0] I/O IOA[15:0]: bi-directional I/O ports It can be programmed as wakeup I/O pins. IOB [15:0] I/O IOB [15:0]: bi-directional I/O ports. It can be programmed as wakeup I/O pins. IOB[11] is shared with ADC OP AMP output IOB[10] is shared with ( OPI) ADC MIC amplifier output (refer to application circuit) IOB[9] is shared with ADC OPI Audio amplifier negative input (refer to application circuit) IOB[8] is shared with ADC AGC by pass filter (refer to application circuit) IOC [15:0] I/O IOC [15:0]: bi-directional I/O ports. It can be programmed as wakeup I/O pins. Power & GND VDD_IOA P Power VDD for Port A VSS_IOA G Power GND for Port A VDD_IOB P Power VDD for Port B VSS_IOB G Power GND for Port B VDD_IOC P Power VDD for Port C VSS_IOC G Power GND for Port C V33_ADC P Power VDD for AD (3.3V) VSS_ADC G Power GND for AD V33_REG P 3V Power output from regulator V27_REG P 2.7V Power output from regulator VDD_REG P Power supply for regulator (2.4V~5.5V) VSS_REG G Ground reference for regulator VDD_DAC P Positive 5V supply for push-pull DAC VDD_PDAC P Positive 5V supply for push-pull DAC post driver VSS_PDAC G Ground reference for push-pull DAC post driver VDD_INT P Power for internal block VSS_INT G Ground for internal block CLK SYSTEM/ ICE INTERFACE X32KI I 32KHz Oscillator crystal input/ R32K OSCI X32KO O 32KHz Oscillator crystal output OPTION TEST I TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low) DAC AUDP O Audio output of push pull DAC AUDN O Audio output of push pull DAC ACIN U Audio analog mixer in ADC MICP I MIC amplifier input positive (Internal Floating) MICN I MIC amplifier input negative (refer to application circuit) VMIC O Microphone power supply

© Generalplus Technology Inc. Proprietary & Confidential 22 Jun. 26, 2017 Version: 1.1 Mnemonic Type Description VADREF O AVREF_DA reference pin PLL VCOIN I PLL6M low pass filter input Other Signal RESETB I System reset pin (active low) (internal 47Kohm pull high resistor) Auto Trim FUSE VFSOURCE I Trimming Power PAD for IROSC6M

6.3.2 LQFP128 Package Pin Assignment

IOB[0] IOB[1] 1234567891011121314151617 NC NC IOB[2] IOC[3] 1819202122232425 IOC[8] VDD_DAC AUDP VSS_ PDAC ACIN 81807978777675747372 82 83 84 92888786 89 90 91 9693 94 95 128 127 126 125 124 123 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 104 105 106 71706968676665 100 101 102 103 26272829303132 IOB[3] IOB[4] IOB[5] IOB[6] IOB[7] IOB[8] IOB[9] IOB[10] IOB[11] VDD_IOB VSS_IOB IOB [12] IOB [13] IOB [14] IOB [15] IOC[0] IOC[1] IOC[2] IOC[9] IOC[4] IOC[5] IOC[6] IOC[7] VSS_IOC VDD_IOC IOC[13] IOC[10] IOC[11] IOC[12] IOC[14] NC VSS_INT IOC[15] NC VFSOURCE IOA[0] VDD_INT IOA[5] IOA[6] IOA[7] IOA[1] IOA[3] IOA[2] IOA[4] IOA[8] NC NC NC IOA[9] NC NC NC NC VDD_IOA NC NC VSS_IOA IOA[11] IOA[12] IOA[10] IOA[13] IOA[15] IOA[14] VDD_ PDAC NC VSS_ PDAC AUDN NC NC NC NC NC NC NC NC NC NC NC VDD_REG V33_REG VSS_REG V27_REG EPM VCOIN RESETB X32KO X32KI TEST VSS_ADC V33_ADC VMIC VADREF MICN MICP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GPCE4096A/GPCE4064A LQFP128 NC

6.3.3 LQFP80 Package Pin Assignment

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 IOB[10] IOB[11] VFSOURCE VDD_INT NC NC IOC[6] IOC[5] IOC[4] IOB[15] IOB[2] IOB[3] IOB[8] IOB[9] VDD_IOB VSS_IOB IOB[14] IOB[13] IOB[12] IOC[7] IOB[4] IOB[5] IOB[6] IOB[7] VDD_IOC IOC[8] IOC[9] VSS_INT GPCE4096A/GPCE4064A LQFP80 VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN NC V27_REG V33_REG VSS_REG 20IOB[1] IOB[0] 37 38 39 IOC[3] IOC[1] IOC[0] IOA[2] IOA[1] IOA[0] IOA[6] IOA[5] IOA[4] 72 71 70 69 68 67 66 65 64 63 62 61 IOA[8] IOA[10] VSS_IOA VDD_IOA IOA[9] IOA[11] IOA[12] IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC 76 737475 AUDP VDD_DAC VDD_PDAC AUDN 80 777879 VSS_PDAC NC IOC[2] NC NC NC NC

6.3.4 LQFP64 Package Pin Assignment

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IOB[8] IOB[9] IOA[5] IOA[4] IOA[3] IOA[2] IOA[8] IOA[7] IOA[6] NC VSS_INT IOB[15] IOB[14] 60 59 58 57 56 55 54 53 52 51 50 49 VDD_IOA IOA[12] IOA[11] IOA[10] VSS_IOA IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC AUDP VDD_DAC VDD_PDAC AUDN VSS_PDAC NCIOB[0] IOB[1] IOB[6] IOB[7] IOB[10] IOB[11] VDD_IOB IOB[12] IOB[13] NC IOB[2] IOB[3] IOB[4] IOB[5] VDD_INT VFSOURCE IOA[0] IOA[1] GPCE4096A/GPCE4064A LQFP64 VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN NC V27_REG V33_REG VSS_REG

6.3.5 QFN64 Package Pin Assignment

VDD_REG MICN VADREF VMIC V33_ADC VSS_ADC TEST MICP X32KI X32KO RESETB VCOIN NC V27_REG V33_REG VSS_REG 17 18 19 20 21 22 24 25 27 28 29 30 31 IOB[8] IOB[9] IOA[5] IOA[4] IOA[3] IOA[2] IOA[8] IOA[7] IOA[6] NC VSS_INT IOB[15] IOB[14] 60 59 58 57 56 55 54 53 52 51 50 49 VDD_IOA IOA[12] IOA[11] IOA[10] VSS_IOA IOA[13] IOA[14] IOA[15] ACIN VSS_PDAC AUDP VDD_DAC VDD_PDAC AUDN VSS_PDAC NCIOB[0] IOB[1] IOB[6] IOB[7] IOB[10] IOB[11] VDD_IOB IOB[12] IOB[13] NC IOB[2] IOB[3] IOB[4] IOB[5] VDD_INT VFSOURCE IOA[0] IOA[1] GPCE4096A/GPCE4064A QFN64 23 26

6.3.6 LQFP48 Package Pin Assignment

2VDD_REG 3V33_REG 4VSS_REG 5EPM 6VCOIN6M 7RESETB 8X32KO 9X32KI 10TEST 11IOB[0] 12IOB[1] 13IOB[2] 14IOB[3] 15IOB[4] 16IOB[5] 17IOB[6] 18IOB[8] 19IOB[9] 20IOB[10] 21VDD_IOB 22IOB[12] 23IOB[13] 24IOB[14] 13 14 15 16 17 18 19 20 21 22 23 24 GPCE4096A/GPCE4064A LQFP48

7 FUNCTION DESCRIPTIONS

7.1 CPU

The GPCE4xxxx is equipped with a 16 -bit ’nS2.0P™ (pronounced as micro -n-SP). Sixteen registers are featured in ’nSP™ 2.0: R1 - R4 and R8 ~ R15 (General- purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) , SR (Segment Register) and eight extended registers . The interrupts include 23 FIQs (Fast Interrupt Request) and IRQs (Interrupt Request), plus one software-interrupt, BREAK.

7.2 Memory

7.2.1 SRAM

There are 4 K-word working SRAM and 2K -word Cache RAM (also can be working RAM), ranged from $0000 through $17FF.

7.2.2 OTP

GPCE4xxxx features a high-speed memory with access speed of three CPU clock cycles.

7.3 PLL, Clock, Power Mode

7.3.1 PLL (Phase Lock Loop)

The purpose of PLL is to provide a base frequency (32768Hz) and to pump the frequency from 6MHz to 48MHz for system clock (FOSC). The default PLL frequency is 12MHz.

7.3.1.1 System clock

Basically, the system clock i s provided by PLL and programmed by the Port_SystemClock (R/W) to determine the clock frequency for system. 7.3.1.2 32768Hz RTC The Real Time Clock (RTC) is normally used in watch, clock or other time related products. A 2Hz -RTC (0.5 seconds) function is loaded in GPCE4xxxx. The RTC counts the time as well as to wake CPU up whenever RTC occurs. Since the RTC is generated each 0.5 seconds, time can be tracked by the total number of RTC occurrences. In addition, GPCE4xxxx supports 32768Hz crystal oscillator in normal mode and auto-power-saving mode. In normal mode, 32768Hz OSC always run s at the highest power consumption. In auto-power-saving mode, however, it runs at normal mode for the first 7.5 seconds and switches back to power-saving mode automatically t o save powers.

7.4 Standby Mode

The GPCE4xxxx features a power savings mode (or called standby mode ) for low power applications. In such mode, SRAM and I/Os remain in the previous states until CPU being awakened. After GPCE4xxxx wakes up , CPU will continue to execute the program from where it slept.

7.5 Low Voltage Detection and Low Voltage Reset

7.5.1 Low voltage detection (LVD)

The Low Voltage Detect ion (LVD) reports the circumstance of present voltage. There are seven LVD levels to be selected :

7.5.2 Low voltage reset

In addition to the LVD, GPCE4xxxx has another important function, Low Voltage Reset (LVR). With LVR function, a reset signal is generated to reset system when the operating voltage drops below LVR level.

7.6 Interrupt

The GPCE4xxxx has 25 interrupt sources, grouped into two types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The pr iority of FIQ is higher than IRQ. User can refer programming guide for details.

7.7 I/O

The GPCE4xxxx has 48 bit-programmable I/Os . with programmable wakeup capability . The following diagram is a n I/O schematic. Data Register Control Logic I/O Pad P_IOA/B/C_Buffer(R) P_IOA/B/C_Buffer(W) P_IOA/B/C_Dir(R/W) P_IOA/B/C_Attrib(R/W) P_IOA/B/C_Data(R) In addition to a general purpose I/O port function, IOA/B/C also shares/carries some special functions. A summary of IOA/B/C special functions is listed as follows:

7.8 Special Function in Port

Port Special Function Function Description Note IOA0 IO_PWM/ High driving I/O IO_PWM Output Refer to Timer section IOA1 IO_PWM/ High driving I/O IO_PWM Output Refer to Timer section IOA2 IO_PWM/ High driving I/O IO_PWM Output Refer to Timer section IOA3 IO_PWM/ High driving I/O IO_PWM Output Refer to Timer section IOA4 IROUT IR Output - IOA5 - - - IOA6 Feedback Input2 - - EXT2 External interrupt source 2 (negative edge triggered) Set IOA6 as floating input mode IOA7 Feedback Output2 Work with IOA6 by adding a RC circuit between them to get an OSC to EXT2 interrupts Set IOA7 as inverted output IOA8 Feedback Input1 - - EXT1 External interrupt source 1 (negative edge triggered) Set IOA8 as floating input mode IOA9 Feedback Output1 Work with IOA8 by adding a RC circuit between them to get an OSC to EXT1 interrupt Set IOA9 as inverted output IOA10 SPI IO3/ Fast driving I/O SPI IO3 Refer to SPIFC section IOA11 SPI IO2/ Fast driving I/O SPI IO2 Refer to SPIFC section IOA12 SPI CS/ Fast driving I/O SPI chip select Refer to SPIFC section IOA13 SPI CK/ Fast driving I/O SPI clock Refer to SPIFC section IOA14 SPI RX/ Fast driving I/O SPI data input Refer to SPIFC section IOA15 SPI TX/ Fast driving I/O SPI data output Refer to SPIFC section IOB0 AN0 ADC Channel 0 Refer to ADC section IOB1 AN1 ADC Channel 1 Refer to ADC section IOB2 AN2 ADC Channel 2 Refer to ADC section IOB3 AN3 ADC Channel 3 Refer to ADC section IOB4 AN4 ADC Channel 4 Refer to ADC section IOB5 AN5 ADC Channel 5 Refer to ADC section IOB6 AN6 ADC Channel 6 Refer to ADC section IOB7 AN7 ADC Channel 7 Refer to ADC section IOB8 AGC ADC AGC Refer to ADC section IOB9 OPI ADC OPI Refer to ADC section IOB10 MICOUT ADC MICOUT Refer to ADC section IOB11 OPO ADC OPO Refer to ADC section IOB12 SPI2 CS SPI2 chip select Refer to SPI2 section IOB13 SPI2 CK SPI2 clock Refer to SPI2 section IOB14 SPI2 RX SPI2 data input Refer to SPI2 section IOB15 SPI2 TX SPI2 data output Refer to SPI2 section IOA[15:0], IOB[15:0] IOC[15:0] Touch sensing input Touch sensing input Refer to CTS section

7.9 Timer / Counter

The GPCE4xxxx has five 16-bit timer/counters . They are re-loaded up -counters. When timer overflows from $ FFFF to $0000, the carry (overflow) signal will make the user’s preset value to be loaded into timer automatically and count up again. At the same time, the carry signal will generate an interrupt signal if the corresponding bit is enabled.

7.9.1 IO PWM

One IO PWMs w hich duty is selected from 1/ 256 to 254/256. These PWM signals can be applied for controlling the speed of motor or other device.

7.9.2 Timebase

Timebase, generated by 32768Hz crystal oscillator, is a combination of frequency selection , generating 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt sources (FIQ6/IRQ6, FIQ7/IRQ7) for real-time-clock.

7.10 Capacitance Touch Sensor(CTS) and CTS

GPCE4xxxx provides Capacitive Touch sensor. It is able to perform capacitive sensing, decision making, responsive actions and other duties pertinent to the system as well.

7.11 Sleep Mode, Wakeup, Halt Mode, and Watchdog

7.11.1 Sleep and wakeup modes

1) Sleep, Halt : After power -on reset, IC starts running until a sleep command is issued . When a sleep command is accepted, IC will turn the system clock (PLL) off. It enters sleep mode if 32KHz Sleep Status bit is cleared or enters halt mode if 32KHz Sleep Status bit is set. 2) Wakeup: CPU awaking from sleep mode requires a wakeup signal to turn the system clock (PLL) on. The FIQ/IRQ signal makes CPU to complete the wakeup process and initialization. The CPU wakeup source is given in the following table. Wakeup up source include all FIQ source and all interrupt source.

7.11.2 Watchdog Reset

If the watchdog function is enabled, a reset signal is generated to reset system when watchdog counter is overflow.

7.12 ADC (Analog to Digital Converter) / DAC

The GPCE4xxxx has eight channels 12-bit ADC (Analog to Digital Converter) to convert analog signal to digital signal. The eight channels of ADC can be eight c hannels of line-in from IOB [7:0] or one channel microphone (MIC) input through amplifier PGA controller, and AGC controller. The MIC amplifier circuit is capable of reducing common mode noise by transmitting signals through differential MIC Inputs (MICN, MICP). Moreover, an external resistor can be applied to adjust microphone gain and operating time of AGC.

7.13 USB Device Function (by body)

Some of t he GPCE4xxxx series provide device function which is compatible with USB 2.0 full -speed standard. An USB transceiver is also built-in.

7.14 SPIFC

A Serial Peripheral Interface flash controller (SPIFC) is featured to facilitate communicati on between GPCE4xxxx with other devices and components , especially for SPI FLASH. The SPIFC supports one- I/O, two-I/O, four-I/O mode of SPI flash. The SPIFC also supports auto mode which can access SPI flash data directly, therefore user ’s program can be placed at external SPI flash. There are six control signals on SPI - SPICS (IOA12), SPICK (IOA13), SDI (IOA14), SDO (IOA15), SPIIO3 (IOA10, only for 4 I/O mode), and SPIIO2 (IOA11, only for 4 I/O mode).

7.14.1 SPI2

A Serial Peripheral Interface controller (SPI2) is built in GPCE4xxxx to facilitate communicating with other devices and components. There are four control signals on SPI 2 - SPICS (IOB12), SPICK (IOB13), SDI (IOB14), and SDO (IOB15). D7 D6 D4D5 D2D3 D0D1 D7 D6 D5 D3D4 D2 D0D1 SPICK(POL=0) SPICK(POL=1) SDO SDI SPICS PHASE = 0

7.15 Audio output

Two sets of 1 6-bit software channel with noise filter is supported. There is one 14 -bit DAC with push-pull amplifier for direct audio output which can mix the analog input signal (ACIN) and the two software channels.

8 ELECTRICAL SPECIFICATIONS

8.1 Absolute Maximum Ratings

Characteristics Symbol Ratings DC Supply Voltage V+ < 4.0V PortA/B/C Pad Supply Voltage VIO < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions see DC Electrical Characteristics. 8.2 DC Characteristics (VDD_REG = 3.3V, VDDIO = 4.5V (IOA & IOB & IOC), TA = 25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD_REG 2.4 - 5.5 V - Operating Current IOP - 23 29 mA FOSC = 48MHz, AD, DAC disable, no load Standby Current ISTB - - 10 A Disable 32KHz crystal 15 A Enable 32KHz,Disable PLL(FOSC) Input High Level VIH 0.7VDD_IO - VDD_IO V - Input Low Level VIL 0 - 0.3VDD_IO V - Output High Current (IOA[9:0], IOB, IOC) IOH 7 14 21 mA VOH = 0.7VDD_IO Output High Current (IOA[15:10]) IOH 14 27 41 mA VOH = 0.7VDD_IO Output Low Current (IOA[9:4], IOB, IOC) IOL 13 23 36 mA VOL = 0.3VDD_IO Output Low Current (IOA[3:0]) IOL 22 44 66 mA VOL = 0.3VDD_IO Output Low Current (IOA[15:10]) IOL 7 13 20 mA VOL = 0.3VDD_IO, high drive disable Output Low Current (IOA[15:10]) IOL 13 25 37 mA VOL = 0.3VDD_IO, high drive enable Input Pull-Low Resister (IOA, IOB, IOC) RPL 80 120 160 K VIN = VDD_IO Input Pull-High Resister (IOA, IOB, IOC) RPH 80 120 160 K VIN = VSS_IO Internal ROSC f requency deviation ⊿F/F -3% 32768 +3% HZ V33_REG = 3.3V Internal 6M ROSC frequency deviation ⊿F/F -3% 6000000 +3% HZ V33_REG = 3.3V 8.3 DC Characteristics (VDD_REG = 3.3V, VDDIO = 3.3V (IOA & IOB & IOC), TA = 25℃) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Operating Voltage VDD_REG 2.4 - 5.5 V - Operating Current IOP - 23 29 mA FOSC = 48MHz, AD, DAC disable, no load

© Generalplus Technology Inc. Proprietary & Confidential 33 Jun. 26, 2017 Version: 1.1 Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. Standby Current ISTB - - 10 A Disable 32KHz crystal 15 A Enable 32KHz,Disable PLL(FOSC) Input High Level VIH 0.7VDD_IO - VDD_IO V - Input Low Level VIL - - 0.3VDD_IO V - Output High Current (IOA[9:0], IOB, IOC) IOH 4 8 12 mA VOH = 0.7VDD_IO Output High Current (IOA[15:10]) IOH 8 15 22 mA VOH = 0.7VDD_IO Output Low Current (IOA[9:4], IOB, IOC) IOL 7 14 21 mA VOL = 0.3VDD_IO Output Low Current (IOA[3:0]) IOL 13 26 39 mA VOL = 0.3VDD_IO Output Low Current (IOA[15:10]) IOL 4 7 10 mA VOL = 0.3VDD_IO, high drive disable Output Low Current (IOA[15:10]) IOL 7 14 21 mA VOL = 0.3VDD_IO, high drive enable Input Pull-Low Resister (IOA, IOB, IOC) RPL 80 120 160 K VIN = VDD_IO Input Pull-High Resister (IOA, IOB, IOC) RPH 80 120 160 K VIN = VSS_IO Internal ROSC f requency deviation ⊿F/F -3% 32768 +3% HZ V33_REG = 3.3V Internal 6M ROSC frequency deviation ⊿F/F -3% 6000000 +3% HZ V33_REG = 3.3V 8.4 ADC Characteristics (V33_ADC = 3.3V, TA = 25℃) Characteristics Symbol Limit Unit Min. Typ. Max. ADC LINE_IN Input Voltage Range from IOB[7:0] VINL (Note 1) VSS-0.3 - V33_ADC+0.3 V ADC Microphone Input Voltage Range VINM VSS-0.3 - V33_ADC+0.3 V Resolution of ADC RESO - - 12 bits Signal-to-Noise Plus Distortion of ADC from Line in SINAD (Note 3) - 50 - dB Effective Number of Bit ENOB (Note 4) 7.0 8.0 - bits Integral Non-Linearity of ADC INL - ±5.0 - LSB (Note 2) Differential Non-Linearity of ADC DNL (Note 6) - ±1.0 - LSB AD Conversion Rate FCONV - - FCPU/256 Hz Microphone Amplifier Gain A MIC - - 42(Note 5) dB Note1: Internal protection diodes clamp the analog input to V 33_ADC and VSS. These diodes allow the analog input to swing from (VSS -0.3V) to (V33_ADC+0.3V) without causing damage to the devices. Note3: The SINAD testing condition at VINLp -p = 0.8*V 33_ADC, FCONV = Fcpu/512 = 49MHz/256 = 192KHz, Fin=1.0KHz Sine waves at V33_ADC = 3.0V from the IOB [7:0] input. Note4: ENOB = (SINAD-1.76)/6.02. Note5: The microphone amplifier maximum gain = 15 * (60K/(1.5K+REXT) V/V. The REXT is external resistor between OPI and MICOUT. The gain is 132V/V (=42dB) when REXT is 5.1K.

© Generalplus Technology Inc. Proprietary & Confidential 34 Jun. 26, 2017 Version: 1.1 8.5 DAC Characteristics (VDD_DAC = 5.0V, TA = 25℃) Characteristics Symbol Limit Unit Min. Typ. Max. DAC Resolution RESO - - 16 bit Noise at No Signal - - -87 - dBr A Dynamic Range(-60dB) - - -86 - dBr A

8.6 Regulator Characteristics (TA = 25℃)

Min. Typ. Max. Input Voltage VREGI 2.4 - 5.5 V Maximum Current Output IREGO - - 60 mA VDD_REG (Regulator in )= 4.5V, VDD (Regulator out ) <100mV Output Voltage VREGO 2.4 3.3 3.3 V Standby Current IRGES - 5 - uA

8.7 Pull High Resistance and VDD(VDD_IO)

8.8 Pull Low Resistance and VDD(VDD_IO)

8.9 IO Output High Current and VDD(VDD_IO)

Test Condition : VOH = 0.7 * VDDIO (Normal PAD)

8.10 IO Output High Current and VDD(VDD_IO)

Test Condition: VOH = 0.7 * VDDIO (SPI PAD – IOA [15:10] ) High Driving Disable

8.11 IO Output Low Current and VDD(VDD_IO)

Test Condition : VOL = 0.3 * VDDIO ( Normal PAD )

8.12 IO Output Low Current and VDD(VDD_IO)

Test Condition : VOL = 0.3 * VDDIO ( High Sink PAD - IOA[3:0] ) Test Condition : V OL = 0.3 * VDDIO ( SPI PAD – IOA [15:10] ) High Driving Disable Test Condition : V OL = 0.3 * VDDIO ( SPI PAD – IOA [15:10] ) High Driving Enable

8.13 Internal ROSC 6M and VDD(VDD_IO)

8.14 Internal ROSC 32K and VDD(VDD_IO)

9 APPLICATION CIRCUITS

9.1 Application Circuit with Regulator, PLL6M and XTAL32K Selected

IOA[15:0] IOA[15:0] IOB[15:0] IOB[15:0] 0.1uF VMIC MICP MICN IOB[8]/AGC 0.1uF VADREF IOB[9]/OPI IOB[10]/MICOUT X32I X32O 32768Hz 25 pF *1 VCOIN 7.5K 3300pF 47nF 25 pF*1 10uF 470K 0.22uF 0.22uF MIC 4.7uF 5.1K 0.22uF 5000 pF RESETB AUDN AUDP 8Ω SPEAKER 0. 1 uF 10uF VSS_REG (2.4V~5.5V) 0.1uF10uF V33_REGVDD(3.3V) 0.1uF10uF V33_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IOB VSS_IOA VDD_PDAC VDD_DAC Application Circuit(MIC_IN ) VSS_PDAC VDD_REG IOC[15:0] IOC[15:0] VDD_IOC VSS_IOC V27_REG 2.2uF VSS_USB VSS_INT VDD_USB VDD_INT 3.3V Note1: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~60K and CL1=CL2 =26~36pF (including PCB parasitic loading; for example, user should apply additional 20~30pF on X32I and X32O if PCB parasitic loading is 6pF) Note2: V33_REG is output of built-in regulator with maximum current 60mA. It is recommended that only use it for internal power pad. Note3: VSS_USB and VDD_USB are supported by body (ref. to “6 SIGNAL DESCRIPTIONS ”). It is recommended that the supplied power of VDD_USB uses external power instead of V33_REG. Note4: VSS_INT and VDD_INT are supported by body (ref. to “6 SIGNAL DESCRIPTIONS”).

9.2 Application Circuit with Regulator, PLL6M and ROSC32K Selected

IOA[15:0] IOA[15:0] IOB[15:0] IOB[15:0] 0.1uF VMIC MICP MICN IOB[7:0] 0.1uF VADREF VCOIN 7.5K 3300pF 47nF RESETB AUDN AUDP 8Ω SPEAKER 0. 1 uF 10uF VSS_REG 0.1uF10uF V33_REGVDD(3.3V) 0.1uF10uF V33_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IOB VSS_IOA VDD_PDAC VDD_DAC Application Circuit(LINE_IN) VSS_PDAC VDD_REG IOC[15:0] IOC[15:0] VDD_IOC VSS_IOC V27_REG 2.2uF VSS_USB VSS_INT VDD_USB VDD_INT 3.3V IOB[7:0] (8-Channel Line_In) (2.4V~5.5V) Note1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used. Note2: V33_REG is output of built-in regulator with maximum current 60mA. It is recommended that only use it for internal power pad. Note3: VSS_USB and VDD_USB are supported by body (ref. to “6 SIGNAL DESCRIPTIONS ”). It is recommended that the supplied power of VDD_USB uses external power instead of V33_REG. Note4: VSS_INT and VDD_INT are supported by body (ref. to “6 SIGNAL DESCRIPTIONS”).

9.3 Application Circuit with Regulator, ROSC6M and ROSC32K Selected

IOA[15:0] IOA[15:0] IOB[15:0] IOB[15:0] 0.1uF VMIC MICP MICN IOB[7:0] 0.1uF VADREF RESETB AUDN AUDP 8Ω SPEAKER 0. 1 uF 10uF VSS_REG 0.1uF10uF V33_REGVDD(3.3V) 0.1uF10uF V33_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IOB VSS_IOA VDD_PDAC VDD_DAC Application Circuit(LINE_IN) VSS_PDAC VDD_REG IOC[15:0] IOC[15:0] VDD_IOC VSS_IOC V27_REG 2.2uF VSS_USB VSS_INT VDD_USB VDD_INT 3.3V IOB[7:0] (8-Channel Line_In) (2.4V~5.5V) Note1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resona tor used. Note2: V33_REG is output of built-in regulator with maximum current 60mA. It is recommended that only use it for internal power pad. Note3: VSS_USB and VDD_USB are supported by body (ref. to “6 SIGNAL DESCRIPTIONS ”). It is recommended that the supplied power of VDD_USB uses external power instead of V33_REG. Note4: VSS_INT and VDD_INT are supported by body (ref. to “6 SIGNAL DESCRIPTIONS”).

9.4 Application Circuit without Regulator, PLL6M and XTAL32K Selected

IOA[15:0] IOA[15:0] IOB[15:0] 0.1uF VMIC MICP MICN 0.1uF VADREF X32I X32O 32768Hz 25 pF *1 VCOIN 7.5K 3300pF 47nF 25 pF*1 RESETB AUDN AUDP 8Ω SPEAKER 0. 1 uF 10uF VSS_REG V33_REG 0.1uF10uF V33_ADC VSS_ADC VDD_IOB VDD_IOA VSS_IOB VSS_IOA VDD_PDAC VDD_DAC Application Circuit(LINE_IN ) VSS_PDAC VDD_REG IOC[15:0] VDD_IOC VSS_IOC V27_REG 2.2uF VSS_USB VSS_INT VDD_USB VDD_INT IOB[7:0] IOB[7:0] (8-Channel Line_In) (2.4V~5.5V) 2.2uF(2.4V~3.6V) 3.3V IOB[15:0] IOC[15:0] Note1: These capacitor values are for design guidance only. Th e recommended 32K XTAL features are ESR=11.2~60K and CL1=CL2 =26~36pF (including PCB parasitic loading, for example, user should apply additional 20~30pF on X32I and X32O if PCB parasitic loading is 6pF) . Note2: V33_REG is output of built-in regulator with maximum current 60mA. It is recommended that only use it for internal power pad. Note3: VSS_USB and VDD_USB are supported by body (ref. to “6 SIGNAL DESCRIPTIONS ”). It is recommended that the supplied power of VDD_USB uses external power instead of V33_REG. Note4: VSS_INT and VDD_INT are supported by body (ref. to “6 SIGNAL DESCRIPTIONS”).

9.5 OTP ROM Programming Circuit (by body)

VDD_REG SCK(IOB14) SDA(IOB15) VSS_IO VPP VCC SCK SDA GND VPP Generalplus Writer EPM VSS_REG V33_REG VSS VDDIN 2.2uF V27_REG 10uF Note: There must be 3V or 5V power connected to VDD_IOB, VSS_IOB should be connected to ground.

10 PACKAGE/PAD LOCATIONS

10.1 Ordering Information

Body Product Number Package Type GPCE4P096UA GPCE4P096UA-NnnV-C Chip form GPCE4P096UA-NnnV-QL09x Green Package – LQFP128 GPCE4P096UA-NnnV-QL03x Green Package – LQFP80 GPCE4P096UA-NnnV-QL02x Green Package – LQFP64 GPCE4P096UA-NnnV-QV09x Green Package – QFN64 GPCE4P096UA-NnnV-QL23x Green Package – LQFP48 GPCE4096UA GPCE4096UA-NnnV-C Chip form GPCE4096UA-NnnV-QL09x Green Package – LQFP128 GPCE4096UA-NnnV-QL03x Green Package – LQFP80 GPCE4096UA-NnnV-QL02x Green Package – LQFP64 GPCE4096UA-NnnV-QV09x Green Package – QFN64 GPCE4096UA-NnnV-QL23x Green Package – LQFP48 GPCE4096A GPCE4096A-NnnV-C Chip form GPCE4096A-NnnV-QL09x Green Package – LQFP128 GPCE4096A-NnnV-QL03x Green Package – LQFP80 GPCE4096A-NnnV-QL02x Green Package – LQFP64 GPCE4096A-NnnV-QV09x Green Package – QFN64 GPCE4096A-NnnV-QL23x Green Package – LQFP48 GPCE4064A GPCE4064A-NnnV-C Chip form GPCE4064A-NnnV-QL09x Green Package – LQFP128 GPCE4064A-NnnV-QL03x Green Package – LQFP80 GPCE4064A-NnnV-QL02x Green Package – LQFP64 GPCE4064A-NnnV-QV09x Green Package – QFN64 GPCE4064A-NnnV-QL23x Green Package – LQFP48 Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 1 - 9, serial number).

10.2 Package Information

10.2.1 LQFP 128L Outline Dimensions

A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 b 0.13 0.16 0.23 c 0.09 - 0.20 D 16.00 BSC D1 14.00 BSC E 16.00 BSC E1 14.00 BSC e 0.40 BSC L 0.45 0.60 0.75 L1 1.00 REF θ 0° 3.5° 7° Notes: 1. Datum plane H is located at the bottom of the mold parting line coincident with where the lead exits the body. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D imensions D1 and E1 do include mold mismatch and are determined at datum plane H. 3. Dimension b does not include dambar protrusion.

10.2.2 LQFP 80 Outline Dimensions

10.2.3 LQFP 64 Outline Dimensions

10.2.4 QFN 64 Outline Dimensions

10.2.5 LQFP 48 Outline Dimensions

11 DISCLAIMER

The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulat ed in the terms of sale only. GENERALPLUS makes no warranty, express, stat utory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLU S reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Pr oducts described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical l ife support equipment, are specifically not recommended without a dditional processing by GENERALPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.

12 REVISION HISTORY

Date Revision # Description Page 13,20,27, 42,47 Apr. 17, 2017 1.0 Original 45

Product Information

GPCE4096A-NnnV-QL02x specifications and overview.

Summary

16-bit Sound Controller

Description

16-bit Sound Controller

Source title GPCE4096A-NnnV-QL02x Datasheet(PDF) - Generalplus Technology Inc.

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