GPC41A3 GENERALPLUS | Alldatasheet
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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GG SEP . 19, 2007 Version 1.0 PPCC4411AA33 4400KKBB SSoouunndd CCoonnttrroolllleerr In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviatio n devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 SEP. 19, 2007 Version: 1.0 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 SEP. 19, 2007 Version: 1.0 40KB SOUND CONTROLLER 1. GENERAL DESCRIPTION The GPC41A3 is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 40K-byte ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 13 sec speech duration @ 6KHz sampling rate) and 128-byte working SRAM. It includes two Timer/Counters, 16 Software Selectable I/Os, and two 8-bit current output (D/A). For audio processing, melody and speech can be mixed into one output. It operates over a wide voltage range of 1.9V - 5.5V and includes Low Voltage Reset function. The Low Voltage Reset automatically resets when the working voltage is less than 1.9V. In addition, GPC41A3 has a Clock Stop mode for power savings. The power savings mode saves the RAM contents, but freez es the oscillator, causing all other chip functions to be inoperative. The Max. CPU clock frequency is 6.0MHz. It has an Instruction Cycle Rate of 2 clock cycles (min.) - 6 clock cycles (max.). The GPC41A3 includes, not only the latest technology, but also the full commitment and technical support of Generalplus. 2. BLOCK DIAGRAM 8-bit RISC controller 40K-byte ROM 128-byte SRAM Two Timers TimeBase INT control Two 8-bit D/As (current)
16 PINS GENERAL I/O PORT
(I/O) IOC3-0 (I/O) IOD7-0 (I/O) AUD1 AUD2Low Voltage Reset XO XI (Rosc) 3. FEATURES 8-bit microprocessor Provides 40K-byte ROM for program and audio data 128-byte working SRAM Software-based audio processing Wide operating voltage: 1.9V – 5.5V @ 4.0MHz 3.6V - 5.5V @ 6.0MHz Supports Crystal Resonator or ROSC (with Bonding option) Max. CPU clock: 4.0MHz @ 1.9V – 5.5V 6.0MHz @ 3.6V - 5.5V Standby mode (Clock Stop mode) for power savings. M a x . 2μA @ 5.0V 500ns instruction cycle time @ 4.0MHz CPU clock Provides 16 general I/Os Two 12-bit timer/counters 6 INT sources Key wake-up function Approx. 13 sec speech @ 6KHz sampling rate with 4-bit ADPCM Two 8-bit current output (D/A) Low Voltage Reset 4. APPLICATION FIELD Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese) M a t h High end toy controller Talking instrument controller General speech synthesizer Industrial controller
© Generalplus Technology Inc. Proprietary & Confidential 4 SEP. 19, 2007 Version: 1.0 5. SIGNAL DESCRIPTIONS** Mnemonic PIN No. Type Description VDD 12 I Logic and I/O VDD VSS 5 I Logic GND I/O GND XI 15 I Oscillator crystal input or RESISTOR (Resistor should be connected to VDD) XO 14 O Oscillator crystal output *OPT 13 I ROSC option, connect to VDD RESET 6 I This pin is an active low reset for the chip TEST 18 I TEST pin, NC AUD1 AUD2 O AUDIO OUTPUT IOA0 IOA1 IOA2 IOA3 I/O I/O I/O I/O Port A is a 4-bit bi-directional Input / Output port with Pull-high or Open-drain option. As inputs, Port A can be in either the Pure or Pull-high states. As outputs Port A can be a Buffer or an Open-drain NMOS type (Sink current). See note 1 and 2 below. IOC0 IOC1 IOC2 IOC3 I/O I/O I/O I/O Port C is a 4-bit bi-directional Input / Output port with Pull-high or Open-drain option. As inputs, Port C can be in either the Pure or Pull-high states. As outputs Port C can be a Buffer or an Open-drain NMOS (Sink current). IOC1: EXT INT IN IOC2: EXT COUNT IN See note 1 and 2 below. IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 I/O I/O I/O I/O I/O I/O I/O I/O Port D is an 8-bit bi-directional Input / Output port with Pull-low or Open-drain option. As inputs, Port D can be in either the Pure or Pull-low states. As output Port D can be either buffer or an Open-drain PMOS (Send current). Also, Port D can be software programmed for wake-up I/O pins. (Programmable I/O, Key Change, Wake-up I/O). **See note 1 and 2 below. * OPT is the selection pin for ROSC or X’TAL. The shape look s like in the right figure. When ROSC is selected, OPT is connected to VDD and if X’TAL is selected, OPT is floating. The reason of OPT near by VDD is that when ROSC is selected, it is easy to make connection between VDD and OPT. OPTVDD Refer to GPC Programming Guide for complete information. *Note: 1). Two input states can be specified; Pure Input, Pull-High or Pull Low. 2). Three output states can be specified, Buffer output, Open Drain PMOS output <send>, Open Drain NMOS output <sink>.
© Generalplus Technology Inc. Proprietary & Confidential 5 SEP. 19, 2007 Version: 1.0 6. FUNCTIONAL DESCRIPTIONS 6.1. CPU The 8-bit micro-processor of GPC41A3 is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). GPC41A3 is able to perform with 6.0MHz (max.) depending on the application specifications. 6.2. Oscillator The GPC41A3 supports Crystal or RC Oscillator by bonding option. The diagrams listed below are typical X’TAL/ROSC circuits for most applications: (a) Crystal or Ceramic Resonator Connections 20 pf 20 pf Rosc (b) RC Oscillator Connections VDD GPC41A3 XI/R XO GPC41A3 XI/R XO 6.3. Bonding Option When ROSC is selected, OPT pad is connected to VDD nearby and if X’TAL is selected, OPT pad is floating. 6.4. ROM Area The GPC41A3 provides a 40K-byte ROM that can be defined as the program area, audio data area, or both. To access ROM, users should program the BANK SELECT Register, choose bank, and access address to fetch data. 6.5. RAM Area The total RAM consists of 128 bytes (including Stack) at locations from $80 through $FF. 6.6. Map of Memory and I/Os *NMI SOURCE: HW register, I/Os USER RAM and STACK UNUSED GENERALPLUS TEST PROGRAM USER'S PROGRAM & DATA AREA ROM BANK #0 DUMMY AREA ROM BANK #1 $00000 $00080 $00100 $00200 $00600 $08000 $0E000 *I/O PORT: w PORT IOA $0002 IOC $0004 IOD $0005 w I/O CONFIG $0000 $0001 w INTA (from TIMER *INT SOURCE: w INTA (from TIMER *MEMORY MAP (From ROM view) w INTB (from TIMER w CPU CLK / 1024 w CPU CLK / 8192 w CPU CLK / 65536 w EXT INT $0FFFF 6.7. Speech and Melody Since the GPC41A3 provides a large ROM and wide range of CPU operation speeds, it is most suitable for speech and melody synthesis. For speech synthesis , the GPC41A3 can provide NMI for accurate sampling frequency. Users can record or synthesize the sound and digitize it into the ROM. The sound data can be played back in the sequence of t he control functions as designed by the user's program. Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and ADPCM. For melody synthesis, the GPC41A3 provides dual tone mode. Once the GPC41A3 enters the dual tone mode, users only need to fill either TMA or TMB, or both TMA and TMB to the tone frequency for each channel, and count the envelope of each channel. The hardware will toggle the tone wave automatically without INT.
© Generalplus Technology Inc. Proprietary & Confidential 6 SEP. 19, 2007 Version: 1.0 6.8. Power Savings Mode The GPC41A3 provides a power savings mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU clock by writing the STOP CLOCK Register. The CPU will then go to the stand-by mode. In such a mode, RAM and I/Os will remain in their previous states until being awoken. Port IOD7-0 is the only wake-up source in the GPC41A3. After the GPC41A3 is awoken, the internal CPU will go to the RESET State (Tw ≧ 65536 x T1) and then continue processing the program. Wakeup Reset will not affect RAM or I/Os (FIG.1). Tw CPU CLK Sleep Wake-up Reset Internal FIG. 1 T1 = 1 / (FCPU), Tw ≧ 65536 x T1 6.9. Low Voltage Reset The GPC41A3 includes a Low Voltage Reset (LVR) function. Below the minimum power-supply voltage of 1.9V, the CPU system will become unstable and malfunction. Low Voltage Reset will reset all functions into the initial operational (stable) state if the VDD power-supply voltage drops about 1.9V (FIG.2). 1.9V VDD CPU CLK TWRESET T2 ≧ 2 * T1 (The LVR function is the same as Power ON Reset or External Reset.) FIG. 2
© Generalplus Technology Inc. Proprietary & Confidential 7 SEP. 19, 2007 Version: 1.0 6.10. Timer/Counter The GPC41A3 contains two 12-b it timer/counters, TMA and TMB respectively. TMA can be specifi ed as a timer or a counter, but TMB can only be used as a timer. In the timer mode, TMA and TMB are re-loaded up-counters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user’s pre-set value and be up-counted again. At the same time, the carry signal will generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset by loading #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time. Clock source of Timer/Counter can be selected as follows: Timer/Counter Clock Source 12-BIT TIMER CPU CLOCK (T) or T/4 TMA 12-BIT COUNTER T/64, T/8192, T/65536 or EXT CLK TMB 12-BIT TIMER T or T/4 MODE SELECT REGISTER TMA only, select timer or counter TIMER CLOCK SELECTOR Select T or T/4
© Generalplus Technology Inc. Proprietary & Confidential 8 SEP. 19, 2007 Version: 1.0 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to + 60 ℃ Storage Temperature TSTO -50℃ to + 150 ℃ Note: Stresses beyond those given in the Absolute Maximum Rating tabl e may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 7.2. AC Characteristics (TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition - - 4.0 MHz VDD = 1.9V - 3.6V, 2-battery CPU Clock FCPU - - 6.0 MHz VDD = 3.6V - 5.5V, 3-battery 7.3. DC Characteristics (VDD = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 1.9 - 3.6 V For 2-battery Operating Current IOP - 1.5 - mA FCPU = 4.0MHz @ 3.0V, no load Standby Current ISTBY - - 2.0 μA VDD = 3.0V Audio Output Current IAUD - 2.4 - mA VDD = 3.0V, full-scale Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V VDD = 3.0V Output High I IOA, IOC, IOD IOH - -4 - mA VOH = 2.4V (0.8*VDD) VDD = 3.0V Output Sink I IOA, IOC, IOD IOL 12 - mA VOL = 0.8V Pull Low Input Resistor IOD RIN - 90 - Kohm VDD = 3.0V
© Generalplus Technology Inc. Proprietary & Confidential 9 SEP. 19, 2007 Version: 1.0 7.4. DC Characteristics (VDD = 5.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 4 - mA FCPU = 4.0MHz @ 5.0V, no load Standby Current ISTBY - - 2.0 μA VDD = 5.0V Audio output current IAUD - 4.8 - mA VDD = 5.0V, full-scale Input High Level VIH 3.0 - - V VDD = 5.0V Input Low Level VIL - - 0.8 V VDD = 5.0V VDD = 5.0V Output High I IOA, IOC, IOD IOH - -10 - mA VOH = 4.0V (0.8*VDD) VDD = 5.0V Output Sink I IOA, IOC, IOD IOL - 17 - mA VOL = 0.8V Pull Low Input Resistor IOD RIN - 45 - Kohm VDD = 5.0V 7.5. The Relationship between the ROSC and the FCPU 8.504 8.072 7.402 6.763 6.209 5.694 4.723 4.3033.9563.570 2.532 1.246 0 50 100 150 200 250 300 Rosc (K ohms) Fcpu (MHz) 8.756 8.292 7.599 6.949 6.409 5.836 4.837 4.4084.050 3.647 2.592 1.273 0 50 100 150 200 250 300 Rosc (K ohms) Fcpu (MHz) 7.5.3. Comparisons of GPC41A, GPC41A1, GPC41A2 and GPC41A3 FCPU=6MHz FCPU=5MHz FCPU=4MHz FCPU=3MHz FCPU=2MHz
© Generalplus Technology Inc. Proprietary & Confidential 10 SEP. 19, 2007 Version: 1.0 8. APPLICATION CIRCUITS 8.1. Application Circuit - (1) GPC41A3 RESET IOC3 IOC2 IOC1 IOC0 IOA3 IOA2 IOA1 IOA0 VDD XO XI AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VSS TEST VDD VDD VDD 220μF RESET 50K 680 0.1μ 8050 Speaker 0.1μ 0.1μ
© Generalplus Technology Inc. Proprietary & Confidential 11 SEP. 19, 2007 Version: 1.0 8.2. Application Circuit - (2) GPC41A3 RESET IOC3 IOC2 IOC1 IOC0 IOA3 IOA2 IOA1 IOA0 VDD XO AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VSS TEST VDD VDD VDD RESET 50K 680 8050 Speaker 0.1μ XI 20p 0.1μ 220μF 0.1μ 20p
© Generalplus Technology Inc. Proprietary & Confidential 12 SEP. 19, 2007 Version: 1.0 9. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment 12345 18 2625242322212019 I O A I O A I O A I O A V S S RESET IOC3 IOC2 IOC1 IOC0 VSS VDD XO XI AUD1 AUD2 TEST I O D I O D I O D I O D I O D I O D I O D I O D OPT 13 X Y (0,0) The IC substrate should be connected to VSS Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type GPC41A3-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc. Proprietary & Confidential 13 SEP. 19, 2007 Version: 1.0 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 14 SEP. 19, 2007 Version: 1.0 11. REVISION HISTORY Date Revision # Description Page SEP. 19, 2007 1.0 Original 14