GPC3002A GENERALPLUS | Alldatasheet
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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GG Feb. 16, 2012 Version 1.0 PPCC33000022AA 33--CChhaannnneell SSoouunndd CCoonnttrroolllleerr In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 Feb. 16, 2012 Version: 1.0 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 Feb. 16, 2012 Version: 1.0 3-CHANNEL SOUND CONTROLLER 1. GENERAL DESCRIPTION 3. FEATURES Wide Operating Voltage: 2.0V * - 5.5V The GPC3002A is embedded with an 8-bit processor, a set of A/D bus for external program/data memory (maximal 4M bytes SRAM/Flash) and 256-byte working SRAM, three sets of 12-bit timer/counters, 32 general I/Os, a 3-channel mixer, a pair of 12-bit PWM outputs and a Real Time Clock(RTC). The microprocessor can implement software based on audio processing, functional control and others. For audio processing, melody and speech can be mixed into one output. It operates over a wide voltage range from 2.0V through 5.5V, and it includes Low Voltage Reset to assure system operating appropriately under low voltage condition. In addition, GPC3002 A also features the sleep mode for power saving. With the high cost/performance ratio, GPC3002A is one of the most suitable engines in the industry for vocal applications. * The lowest operating voltage depends on LVR (Low Voltage Reset) level. Typical LVR voltage is 2.0V but with+/- 0.1V deviation possibility Working Voltage with 6MHz system clock: 2.2V - 5.5V Working Voltage with 8MHz system clock: 2.4V - 5.5V ** The system clock would start to slow down at lowest working voltage (6MHz at 2.2V, 8MHz at 2.4V); please refer to the Frequency vs. VDD curve on page 12 External 4M bytes maximal memory (SRAM/Flash) 256-byte working SRAM Generalplus ICE_CORE embedded Built-in internal (8MHz or 6MHz) or external RC oscillator Standby mode (Clock Stop mode) for power savings. Max. 5.0uA @ 4.5V 32 general I/Os (including four high brightness LED driving I/Os) Three 12-bit timer/counters 2. BLOCK DIAGRAM 8 IRQs & 1 NMI interrupts Three wake-up sources Feedback function Low Voltage Reset (LVR) function Watchdog function IR function RTC function Four sets of 256 level PWMIO outputs A 3-channel mixer with melody or ADPCM/PCM input A pair of PWM outputs with volume control 4. APPLICATION FIELD Talking instrument controller General music synthesizer High end toy controller Intelligent education toys And more
© Generalplus Technology Inc. Proprietary & Confidential 4 Feb. 16, 2012 Version: 1.0 5. SIGNAL DESCRIPTIONS PIN Name PIN No. LQFP 128 Pin. No. Type Description IO Port IOA[7:0] 83-76 111-104 I/O IOA[7:0] is a bi-directi onal I/O port, which can be software programmed as wake up I/O. 1Mohm || 100Kohm feedback pull low resistor IOA7 shared pad with IR output IOA1 shared pad with external clock input IOA0 shared pad with external interrupt input IOA[2:1 ]share pad with feedback function IOB[7:0] 75-68 103-101, 92-88 I/O IOB[7:0] is a bi-dir ectional I/O port, which can be software programmed as wakeup I/O. 1Mohm || 100Kohm feedback pull low resistor IOB5 shared pad with XTAL 32KHz input IOB4 shared pad with XTAL 32KHz output IOB[3:0] shared pad with 256-level PWM output, high sink current IOC[7:0] 65-58 85-78 I/O IOC[7:0] is a bi-directional I/O port, which can be software programmed as wake up I/O. 1Mohm || 100Kohm feedback pull low resistor IOD[7:0] 57-50 77-70 I/O IOD[7:0] is a bi-directional I/O port, which can be software programmed as wake up I/O. 1Mohm || 100Kohm feedback pull low resistor Power & Ground PAD VDD1、VDD2、VDD3 66,84,93 86, 112, 120 P Power supply voltage input, VDD3 is for 3.3V regulator input. VSS1、VSS2 67,88 87,115 G Ground reference VDD33 94 121 P 3.3V regulator output VDD_MEM1、VDD_MEM2 26,37 40,51 P External SRAM/Flash address & data bus power supply voltage input, which can be lower than or equal to VDD1, VDD2, VDD3. VSS_MEM1、VSS_MEM2 27,38 41,52 G External SRAM/Flash address & data bus ground reference PVDD 2 8 P PWM driver power; which can be higher than or equal to VDD1, VDD2, VDD3 PVSS 4 10 G PWM driver ground reference External memory Address & Data bus Interface XROMCEB 11 17 O External SRAM/Flash chip select enable (low active). VDD_MEM power domain XROMOEB 10 16 O External SRAM/Flash output enable (low active). VDD_MEM power domain XROMWEB 9 15 O External SRAM/Flash write enable (low active). VDD_MEM power domain XBKA[21:20]B 20-21 26-27 O Complementation of XBKA[21:19], for extend external SRAM/Flash, VDD_MEM power domain XBKA[21:14] 23-25,28-32 37-39, 42-46 O External SRAM/Flash bank selection address. VDD_MEM power domain ,49 47-50, 53-61, 69 O External SRAM/Flash address bus. VDD_MEM power domain XD[7:0] 19-12 25-18 I/O External SRAM/Flash data bus. VDD_MEM power domain ICE related ICE_EN 95 122 I ICE enable, high active (with pull low) ICE_CLK 96 123 I ICE clock (with pull low) ICE_SDA 97 124 I/O ICE serial data bus
© Generalplus Technology Inc. Proprietary & Confidential 5 Feb. 16, 2012 Version: 1.0 PIN Name PIN No. LQFP 128 Pin. No. Type Description Others -86 - - N/A RESB 91 118 I System reset input, low active (with pull high) TEST 92 119 I Test pin, high active (with pull low) AUDN, AUDP 1,3 7,9 O PWM output HMCUEN 5 11 I Hard macro CPU enable, high active, tied to VDD_MEM. XSLEEP 6 12 O System sleep status output, high active. VDD_MEM power domain DFI 7 13 I Disconnect external SRAM/Flash interface, high active (with pull low). VDD_MEM power domain ICE_ID 8 14 I ICE identify signal (with pull low). VDD_MEM power domain OSC 85 113 I R-oscillator input, connect resistor to VDD IOSC_PEN 22 36 I Oscillator select signal When ICE mode (input floating). VDD_MEM power domain Total: 97 Pins Legend: I = Input, O = Output, P = Power, G = Ground
© Generalplus Technology Inc. Proprietary & Confidential 6 Feb. 16, 2012 Version: 1.0 5.1. PAD Assignment The IC substrate should be connected to VSS or floated Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note2: VDD_MEM can be lower than or equal to VDD. Note3: PVDD can be higher than or equal to VDD. Note4: Please DON’T bond TEST pin.
© Generalplus Technology Inc. Proprietary & Confidential 7 Feb. 16, 2012 Version: 1.0 5.2. PIN Map NC NC NC NC ICE_SDA ICE_CLK ICE_EN VDD33 VDD3 TEST RESB NC NC VSS2 NC OSC VDD2 IOA7 IOA6 IOA5 IOA4 IOA3 IOA2 IOA1 IOA0 IOB7 IOB6 IOB5 NC NC NC NC NC NC NC NC NC XBKA20B XBKA21B XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 XROMWEB ICE_ID DFI XSLEEP HMCUEN PVSS AUDP PVDD AUDN NC NC NC NC NC NC NC NC NC NC XA0 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 VDD1 VSS1 IOB0 IOB1 IOB2 IOB3 IOB4 NC NC NC NC NC NC NC IOSC_PEN XBKA21 XBKA20 XBKA19 VDD_MEM1 VSS_MEM1 XBKA18 XBKA17 XBKA16 XBKA15 XBKA14 XA13 XA12 XA11 XA10 XA9 XA8 XA7 XA6 XA5 XA4 XA3 XA2 XA1 NC NC NC 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 GPC3002A LQFP 128 XROMOEB XROMCEB VDD_MEM2 VSS_MEM2
© Generalplus Technology Inc. Proprietary & Confidential 8 Feb. 16, 2012 Version: 1.0 6. FUNCTIONAL DESCRIPTIONS 6.1. CPU The microprocessor inside the GPC3002A is an 8-bit high performance processor equipped with Accumulator, Program Counter, X and Y Register, Stack pointer and Processor Status Register (the same as the 6502 instruction structure). The maximum CPU speed of 8.0MHz is capable of generating clearer speech, pleasant music as well as achieving the best performance. 6.2. RAM Area The total RAM size is 128-byte or 256-byte (including Stack), 128-byte RAM start from address $0080 through $00FF ($0080 - $00FF mapping to $0180 - $01FF), and 256-byte RAM start from address $0080 through $017F ($0100 - $017F mapping to $0180 - $01FF). 6.3. External memory Area The GPC3002A provides external 4M-byte maximal memory that can be defined as the program area, audio data area, or both. To access memory, users should program the BANK SELECT Register; choose bank, and access address to fetch data. 6.4. Map of Memory and I/Os I/O &$0000-$007F $0840-$3FFF $C000-$FFFF CPU View Bank0 ROM View ROM address= $C000-$FFFF Use Bank register to mapping address . . . Reg. $0080-$00FF Program ROM Bank0 RAM1 $3F8000 - $3FBFFF $3FC000 - $3FFFFF $00000 - $03FFF $04000 - $07FFF $08000 - $0BFFF $0C000 - $0FFFF $10000 - $13FFF $14000 - $17FFF $0180-$01FF $0200-$07DF Test ROM $07E0-$07F5 Test IRQ $07F6-$07F9 $07FA-$07FF Test Vector $081A-$081F Normal IRQ$0820-$0835 $0836-$083F Normal Vector $0800-$0819 Reserved Reserved $4000-$7FFF Program ROM Bank1 $8000-$BFFF Program ROM Bank2 $0100-$017F Same as $80-$FF or $0100-$017F Program ROM Bank register to assign bank Bank1 Bank2 Bank3 Bank4 Bank5 Bank254 Bank255 Reserved RAM2 6.5. I/O Port There are 32 IOs (IODA[7:0], IODB[7:0], IOC[7:0] and IOD[7:0]) in the GPC3002A, which are bit-controlled IOs. They can be programmed as input (pure input or pull-low) or output buffer. As pull-low input, they keep a less impedance to get better noise immunity. While pressing the key (IOs to VDD), a large impedance retained to save DC power. IOA7 can be programmed as an IR transmitter. IOA1 can be programmed as an external clock source. IOA0 can be programmed as an external interrupt source. IOA[2:1] can also be programmed as feedback function with IOA2 connecting to the input of inverter and IOA1 connecting to the output of inverter. With feedback function, RC or Xtal oscillation can be im plemented. For mode flexible application, IO wakeup and ECK as timerA clock source are also available when feedback function enable. Refer the programming guide for more information about feedback function. IOB5 and IOB4 can be programmed as a 32KHz crystal clock generator by adding external components. IOB[3:0] can sink high current to drive high brightness LED. IO port configuration: Register Control logic pull low Pin pad Buffer(R) Data(R) Port_Data(W) Port_Buffer(W) Port_DIR(R/W) 1M ohm Input/Output port : IOA[7:0], IOB[7:0],IOC[7:0], IOD[7:0] pull low 100K ohm 6.6. Power Saving Mode The GPC3002A includes a power saving mode (standby mode) for those applications that require low standby current. To enter standby mode, the Wake-up Register must be enabled and then stop the CPU clock by writing the STOP CLOCK Register to enter standby mode. In such mode, RAM and I/Os will remain in their previous states until being awakened. All 32 IOs, RTC (8Hz/2Hz), and external interrupt (IOA0) are wake-up sources in the GPC3002A. After the GPC3002A is awakened, the internal CPU will continue to execute the program. 6.7. RTC (Real Time Clock) GPC3002A provides two RTC (real time clock) sources: 2Hz, 8Hz. The RTC sources can be used for time counting or system awaking. Each RTC occurs, the system wakes up and users can use this signal for time count ing. In addition, GPC3002A supports 32768Hz OSC in auto mode, the first one second runs at strong mode (consumes the highest power) and then switch to weak mode automatically to save power.
© Generalplus Technology Inc. Proprietary & Confidential 9 Feb. 16, 2012 Version: 1.0 6.8. Low Voltage Reset The GPC3002A has a Low Voltage Reset (LVR) function. In general, the CPU becomes unstabl e and malfunctions under low voltage condition. With the unique design of Low Voltage Reset in GPC3002A, it is able to reset all functions to the initial operational (stable) state if the power voltage drops below certain operation voltage. 6.9. Timer/Counter The GPC3002A has three 12-bit timer/counters: TMA, TMB, and TMC respectively. In the timer mode, TMA, TMB, and TMC are re-loadable up-counters. When ti mer overflows from $0FFF to $0000, the carry (overflow) signal will make the user’s pre-set value to be loaded into timer automatically and count up again. At the same time, the carry signal will generate an INT signal if the corresponding bit in the INT ENABLE Register is enabled. Suppose TMB is specified as a c ounter, users can reset it by loading #0 into the counter. After the counter is activated, the counter value can also be read at the same time. The read instruction will not affect the counter value nor reset it. 6.10. Speech and Melody In speech synthesis, the GPC3002A can use NMI for accurate sampling frequency. User can store the speech data in external memory and play it back with realistic sound quality. Several algorithms are recommended for high fidelity and compression of sound: PCM, ADPCM, SACMA3400 and A3400Pro.
© Generalplus Technology Inc. Proprietary & Confidential 10 Feb. 16, 2012 Version: 1.0 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V < 7.0V + Input Voltage Range V (VSS-0.3V) to (V IN + + 0.3V) 0℃ to +70℃ Operating Temperature TA -65℃ to +150℃ Storage Temperature TSTO Note: Stresses beyond those given in the Absolute Maximum Rating tabl e may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 7.2. DC Characteristics (TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Min. Operating Voltage VDD, min 1.9 2.0 2.1 V Max. Operating Voltage VDD, max - - 5.5 V Low Voltage Reset Level V 1.9 2.0 2.1 V LVR - 2 - mA FCPU = 6MHz @ 3.0V, PWM output off Operating Current IOP - 4 - mA FCPU = 6MHz @ 4.5V, PWM output off - - 5 uA VDD = 3.0V Standby Current ISTBY - - 5 uA VDD = 4.5V GPIO Input High Level 0.7VDD - - V VDD = 4.5V VIH (IOA, IOB, IOC, IOD) GPIO Input Low Level - - 0.3VDD V VDD = 4.5V VIL (IOA, IOB, IOC, IOD) - 5 - mA VDD = 3.0V, VOH = 0.7*VDD Output High Current IOH (IOA, IOB, IOC, IOD) - 10 - mA VDD = 4.5V, VOH = 0.7*VDD - 10 - mA VDD = 3.0V, VOL = 0.3*VDD Output Low Current IOL (IOA, IOB[7:4], IOC, IOD) - 20 - mA VDD = 4.5V, VOL = 0.3*VDD - 20 - mA VDD = 3.0V, VOL = 0.3*VDD Output Low Current IOL (IOB[3:0]) - 40 - mA VDD =4.5V, VOL = 0.3*VDD - 200 - Kohm VDD = 3.0V, IO = 0V Input Pull Low Resistor RL (IOA, IOB, IOC, IOD) - 100 - Kohm VDD = 4.5V, IO = 0V - 2000 - Kohm VDD = 3.0V, IO = 3.0V Input Pull Low Resistor RL (IOA, IOB, IOC, IOD) - 1000 - Kohm VDD = 4.5V, IO = 4.5V - 180 - mA VDD = 3.0V, 8 Ohms load PWM Driver Current IPWM - 280 - mA VDD = 4.5V, 8 Ohms load - 2 - % Fosc(4.5V) Fosc(2.4v)Fosc(4.5v)− External ROSC Frequency deviation by △F/F voltage drop - 2 - % Fosc(3.0v) Fosc(2.4v)Fosc(3.0v)− FCPU = 6MHz, Internal ROSC - 2 - % Fosc(3.0v) Fosc(2.4v)Fosc(3.0v)− = 8MHz, Internal ROSC FCPU
© Generalplus Technology Inc. Proprietary & Confidential 11 Feb. 16, 2012 Version: 1.0 Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition - 2 - % Fosc(4.5v) Fosc(3.0v)Fosc(4.5v)− = 6MHz, Internal ROSC FCPU - 2 - % Fosc(4.5v) Fosc(3.0v)Fosc(4.5v)− = 8MHz, Internal ROSC FCPU -7 - 7 % 6MHz 6MHzFosc(3.0v) − FCPU = 6MHz @ 3.0V, ROSC=51Kohm, External ROSC -7 - 7 % 6MHz 6MHzFosc(4.5v) − FCPU = 6MHz @ 4.5V, ROSC=51Kohm, External ROSC -3 - 3 % 6MHz 6MHzFosc(3.0v) − FCPU = 6 M H z @ 3 . 0 V , Internal ROSC -3 - 3 % 8MHz 8MHzFosc(3.0v) − FCPU = 8 M H z @ 3 . 0 V , Internal ROSC △F/F Frequency lot deviation -3 - 3 % 6MHz 6MHzFosc(4.5v) − FCPU = 6 M H z @ 4 . 5 V , Internal ROSC -3 - 3 % 8MHz 8MHzFosc(4.5v) − FCPU = 8 M H z @ 4 . 5 V , Internal ROSC Note: VDD, min may have +/-0.1V variation due to process issue. 7.3. (3volt) External Oscillator R Relative FOSC Table (the table is only for reference) R(Kohm) 39 51 75 F (MHz) 8 6 4 OSC
© Generalplus Technology Inc. Proprietary & Confidential 12 Feb. 16, 2012 Version: 1.0 7.4. The Relationship between the ROSC and the FCPU 7.4.1. Frequency vs. VDD (built-in 6MHz R OSC) 7.4.3. Operating Current vs. VDD (PWM output off) 123456 VDD(V) Fosc(MHz) 2.2 22 . 533 . 544 . 555 . 56 VDD(V) Iop(mA) Fosc=8M Fosc=6M 7.4.2. Frequency vs. VDD (built-in 8MHz ROSC) 123456 VDD(V) Fosc(MHz) 2.4
© Generalplus Technology Inc. Proprietary & Confidential 13 Feb. 16, 2012 Version: 1.0 8. APPLICATION CIRCUITS 8.1. Application Circuits with Low Loading PCB Layout Guidelines: 1. VDD, VDD_MEM and PVDD must be connected to power input port directly, not the branch of each other. 2. VDD_MEM can be lower than or equal to VDD. 3. PVDD can be higher than or equal to VDD. 4. VSS, VSS_MEM, PVSS must be connected to ground input directly, not the branch of each other. 5. Capacitor (used for XTAL32K) is proposed to be 12~20 pF. 6. When using 2 batteries, C1 is suggested 0.1uF~4.7uF, and should be increased in high volume application. 7. R1 can be removed when using internal oscillator.
© Generalplus Technology Inc. Proprietary & Confidential 14 Feb. 16, 2012 Version: 1.0 8.2. Application Circuits Heavy Loading (such as motor, high brightness LED) PCB Layout Guidelines: 1. VDD, VDD_MEM and PVDD must be connected to power input port directly, not the branch of each other. 2. VDD_MEM can be lower than or equal to VDD. 3. PVDD can be higher than or equal to VDD. 4. VSS, VSS_MEM and PVSS must be connected to ground input directly, not the branch of each other. 5. Capacitor (used for XTAL32K) is proposed to be 12~20 pF. 6. The typical value of C2 is 47uF, and should be modified in different loading. 7. R1 can be removed when using internal oscillator.
© Generalplus Technology Inc. Proprietary & Confidential 15 Feb. 16, 2012 Version: 1.0 9. PCB LAYOUT GUIDE FOR HEAVY LOADING APPLICATION To avoid the unexpected noises that may end up with abnormal CPU operations, the following cares must be exercised while design ing the PCB layout: Bond all VDD and VSS pins out. The 0.1uF capacitor placed between VDD and VSS must be as close as possible to IC itself. Power lines are as independent as possible, The PCB layout examples are given as follows: The PCB layout method (Power line connects in series) as below is not recommended.
© Generalplus Technology Inc. Proprietary & Confidential 16 Feb. 16, 2012 Version: 1.0 10. PACKAGE/PAD LOCATIONS 10.1. Ordering Information Product Number Package Type GPC3002A - C Chip form GPC3002A - QL09x Halogen Free Package 10.2. Package Information LQFP 128 Millimeter Symbol Min. Nom. Max. A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 D 16.00 BSC. D1 14.00 BSC. E 16.00 BSC. E1 14.00 BSC.
© Generalplus Technology Inc. Proprietary & Confidential 17 Feb. 16, 2012 Version: 1.0 Millimeter Symbol Min. Nom. Max. e 0.40 BSC. θ 0° 3.5° 7° b 0.13 0.16 0.23 c 0.09 - 0.20 L 0.45 0.60 0.75 L1 1.00 REF
© Generalplus Technology Inc. Proprietary & Confidential 18 Feb. 16, 2012 Version: 1.0 11. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GE NERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are curr ent before placing orders. Products descri bed herein are intended for use in normal com mercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 19 Feb. 16, 2012 Version: 1.0 12. REVISION HISTORY Date Revision # Description Page Feb. 16, 2012 1.0 Original 19