GPC251A1 GENERALPLUS | Alldatasheet

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GENERALPLUS T ECHNOLOGY I NC. re serves the rig ht to change t his documentation w ithout p rior n otice. I nformation pr ovided by GENE RALPLUS TECHNOLOGY INC. is believ ed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no w arranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPCC225511AA11 225566KKBB SSoouunndd CCoonnttrroolllleerr FEB. 23, 2006 Version 1.0 In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

© Generalplus Technology Inc. Proprietary & Confidential 2 FEB. 23, 2006 Version: 1.0

  1. GENERAL DESCRIPTION The GPC 251A1 is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor w ith 69 instructions, 256K-byte ROM for speech and melody data (Speech is compressed b y a 4-bit ADPCM with app rox. 85 sec speech duration @ 6KHz sampling rate) and 128-byte working SRAM. It includes tw o T imer/Counters, 2 4 Sof tware Select able I/Os, and two 8- bit curre nt output s (D/A). For audio proc essing, melod y and speech can be mixed into one output. It operates over a wide voltage range of 2.4V - 5.5V and includes Low Voltage Reset function. The Low Voltage Res et automatically resets when the working voltage is less than 2.2V . In addition, G PC251A1 has a Clock Stop mode for p ower savings. The po wer savings mode saves the RAM content s, but fr eezes the oscillator , causing all other chip funct ions to be inop erative. The M ax. CP U clock frequency is 6.0 MHz. It has an Instruction C ycle Rate of 2 clock cycles (min.) - 6 clock cy cles (m ax.). The GPC251A1 includes not onl y the late st technology, b ut also the full commitment and technical support of Generalplus. 2. BLOCK DIAGRAM 8-bit microprocessor 256K-byte ROM 128-byte SRAM INT control

24 PINS GENERAL I/O PORT

(current) IOB7-0 (I/O) IOC7-0 (I/O) IOD7-0 (I/O) 3. FEATURES „ 8-bit microprocessor „ Provides 256K-byte ROM for program and audio data „ 128-byte working SRAM „ Software-based audio processing „ Wide operating voltage: 2.4V - 3.6 V @ 4.0MHz 3.6V - 5.5V @ 6.0MHz „ Supports Crystal Resonator or ROSC (w ith Mask option) „ Max. CPU clock: 4.0MHz @ 2.4V - 3.6V 6.0MHz @ 3.6V - 5.5V „ Standby mode (Clock Stop mode) for power savings. M ax. 2µA @ 5.0V „ 500ns instruction cycle time @ 4.0MHz CPU clock „ Provides 24 general I/Os „ Two 12-bit timer/counters „ 6 INT sources „ Key wake-up function „ Approx. 85 sec speech @ 6KHz sampling rate with 4-bit ADPCM „ Two DA output „ Low Voltage Reset „ Volume control function 4. APPLICATION FIELD „ Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese) Math „ High end toy controller „ Talking instrument controller „ General speech synthesizer „ Industrial controller © Generalplus Technology Inc. Proprietary & Confidential 3 FEB. 23, 2006 Version: 1.0

  1. SIGNAL DESCRIPTIONS* Mnemonic Pin No. Type Description VDD 17 I Power VDD VSS 13, 14 I Power VSS XI 19 I Oscillator crystal input or RESISTOR (Resistor should be connected to VDD) XO 18 O Oscillator crystal output TEST 22 I Test pin, NC RESET 16 I This pin is an active low reset for the chip. AUD1 AUD2 O Audio output IOB0 IOB1 IOB2 IOB3 IOB4 IOB5 IOB6 IOB7 I/O I/O I/O I/O I/O I/O I/O I/O Port B is an 8-bit bi-directional Input / Output port with Pull-low or Open-drain opti on. As inputs, Port B can be in eith er the Pure o r Pull-low states. As outputs, Port B can be either Buffer or Open-drain NMOS types (Sink current). See note 1 and 2 below. IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 I/O I/O I/O I/O I/O I/O I/O I/O Port C is an 8-bit bi-directional In put / Out put port with Pull-high or Open-d rain option. As inputs, Port C can be in either the Pur e or P ull-high states. As outputs Port C can be a Buf fer type or Open-drain t ype. Port C3 - 0 are Open-drain NMOS t ype ( Sink current) and Port C7 - 4 are Open-drain PMOS (Send current). IOC0: Serial programming Data IOC1: Also selectable as an external interrupt PIN IOC2: EXT COUNT IN See note 1 and 2 below. IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 I/O I/O I/O I/O I/O I/O I/O I/O Port D is an 8- bit bi-directional prog rammable Input / Outp ut port w ith Pull-low or Open-drain option. As inputs, Port D can be either Pure or Pull-low states. As outputs, Port D can be either Buffer or Open-drain PMOS (send current). Also, Port D can b e sof tware p rogrammed for wake-up I/O pins. (Ke y Change, Wake-up I/O). **See note 1 and 2 below. * Refer to GPC Programming Guide for complete information. **Note: 1.) Two input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified as Buffer output, Open Drain PMOS output (send), or Open Drain NMOS output <sink>. © Generalplus Technology Inc. Proprietary & Confidential 4 FEB. 23, 2006 Version: 1.0
  1. FUNCTIONAL DESCRIPTIONS 6.1. CPU The 8 -bit micro processor of GPC251A1 is a high perfo rmance processor equipped with Accumulator , Progr am Counter , X Register, Stack pointer and Processor S tatus Register (this is the same as the 65 02 instruction structure). GPC251A1 is able to perform with 6 .0MHz (ma x.) depending on the application specifications. 6.2. Oscillator The GPC251A1 support s A T-cut p arallel reso nant oscillated Crystal / Resonator or RC Oscillator or ex ternal clock sour ces by mask option (select one from tho se three t ypes). The design of application circu it should fo llow t he vendors’ specifications or recommendations. The diagrams listed below a re t ypical X’TAL/ROSC circuits for most applications: (a) Crystal or Ceramic Resonator Connections 20 pf 20 pf Rosc (b) RC Oscillator Connections VDD GPC251A1 XI/R XO GPC251A1 XI/R XO 6.3. Mask Option The GPC251A1 has the following mask option: hSupports Crystal Resonator or ROSC (with mask option). 6.4. ROM Area The GPC251A1 provides a 256K-byte ROM that can be defined as the prog ram area, audio data area, o r both. To access ROM, users should program the BANK SELECT Register; choose bank, and access address to fetch data. 6.5. RAM Area The GPC251A1 total RAM consists of 128 bytes (including Stack) at locations from $80 through $FF. 6.6. Volume Control Function The GP C251A1 contains a volu me control function that provides an 8-step volu me controller to control current D/A output. A volume control function selector (Enable/Disable) re gister and controller register is provided. 6.7. Map of Memory and I/Os HW register, I/ Os USER RAM and STACK UNUSED GENERALPLUS TEST PROGRAM USER'S PROGRAM & DATA AREA ROM BANK #0 $00000 $00080 $00100 $00200 $00600 $3FFFF *MEMORY MAP (From ROM view) $08000 ROM BANK #1 $10000 ROM BANK #2 $18000 ROM BANK #3 $1FFFF $20000 ROM BANK #4 ROM BANK #7 $38000 *I/O PORT: *NMI SOURCE: ─ INTA (from TIMER A) *INT SOURCE: ─ PORT IOA $0002 ─ I/O CONFIG $0000 $0001 ─ INTA (from TIMER A) ─ INTB (from TIMER B) ─ CPU CLK / 1024 ─ CPU CLK / 8192 ─ CPU CLK / 65536 ─ EXT INT IOB $0003 IOC $0004 IOD $0005 6.8. I/O Port Configurations* Input/Output IOB port : IOB3 - 0 60K OD : Open Drain input data logic_1 control output data OD-NMOS or buffer Input/Output IOB port : IOB7 - 4 60K OD : Open Drain input data logic_2 control output data OD-NMOS or buffer © Generalplus Technology Inc. Proprietary & Confidential 5 FEB. 23, 2006 Version: 1.0

Input/Output IOC port : IOC3 - 0 input data output data logic_3 control 90K VDD OD-NMOS buffer or OD : Open Drain 6.9. Timer/Counter The GPC251A1 contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be spe cified as a t imer or a counter , but TMB can onl y be used as a tim er. In the timer mode, TMA and TMB ar e r e-loaded up -counters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user ’s pre-set valu e and be up-counted again. At the same time, t he carry signal w ill generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset b y loa ding #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time. The read instruction will not affect the value of the counter or reset it. Input/Output IOC port : IOC7 - 4 input data output data logic_4 control 90K VDD OD-PMOS buffer or OD : Open Drain Clock source of Timer/Counter can be selected as follows: Timer/Counter Clock Source 12-BIT TIMER CPU CLOCK (T) or T/4 TMA 12-BIT COUNTER T/64, T /8192, T/65536 o r EX T CLK TMB 12-BIT TIMER T or T/4 MODE SELECT REGISTER TMA only, select timer or counter TIMER CLOCK SELECTOR Select T or T/4 Input/Output IOD port : IOD3 - 0 60K OD : Open Drain input data logic_5 control output data OD-PMOS or buffer 6.10. Speech and Melody Since the GPC2 51A1 provides a large R OM and w ide range o f CPU operation speeds, it is most suitable for spe ech and melod y synthesis. For speech s ynthesis, the GP C251A1 can provide NMI fo r accurate sampling frequency. Users can record or synthesize the sound and digitize it into the ROM. The soun d dat a can be played back in t he sequence of the control fu nctions as designed by the user's program. Several algorithms are r ecommended for high fidelity and compression of sound including PCM, L OG PCM, and ADPCM. Input/Output IOD port : IOD7 - 4 60K OD : Open Drain input data logic_6 control output data OD-PMOS or buffer For melod y s ynthesis, the GPC 251A1 provides the dual tone mode. After selecting the dual t one mode, users only need to fill either TMA or T MB, or both TM A and TMB to generate e xpected frequency for ea ch channel. The hard ware will toggle the ton e wave automatic ally without ent ering into an interrupt service routine. Users are able to simulate musical instruments or sound effects by simply controlling the envelope of tone output. *Values shown are for VDD = 5.0V test conditions only. © Generalplus Technology Inc. Proprietary & Confidential 6 FEB. 23, 2006 Version: 1.0

6.11. Power Savings Mode The GPC251A1 provides a po wer savings mode ( Standby mode) for those ap plications that require very low stand-by current. To enter st andby m ode, the W ake-Up Register should be enabled and then stop the CPU clock b y writing the ST OP CLOCK Register. The CPU will then go to the stand-by mode. In such a mode, RAM and I/Os will remain in their previous states until being awakened. Po rt IOD7-0 is th e onl y wake-up source in the GPC251A1. After the GPC251A1 is awakened, the internal CPU will go to the RESET State (Tw ≧ 65536 x T1) and then continue processing the program. Wakeup Reset will not af fect RAM or I/Os (See FIG.1). Tw CPU CLK Sleep Wake-up Reset FIG. 1 T1 = 1 / (FCPU), Tw 65536 x T1≧ 6.12. L ow Voltage Reset The GP C251A1 includes a Lo w V oltage Rese t (L VR) function . Below the minimum power-sup ply volt age of 2.2V, the CPU system will become unst able and malfunction. Lo w V oltage Reset will reset all functions into the initial ope rational (st able) state if the VDD power-supply voltage drops below 2.2V (FIG.2). TW T2 2 * T1≧ 2.2V VDD CPU CLK RESET (The LVR function is the same as Power ON Reset or External Reset.) FIG. 2 © Generalplus Technology Inc. Proprietary & Confidential 7 FEB. 23, 2006 Version: 1.0

  1. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to +60℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 7.2. AC Characteristics (TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition - 2.0 4.0 MHz VDD = 2.4V - 3.6V, 2-battery CPU Clock FCPU - 4.0 6.0 MHz VDD = 3.6V - 5.5V, 3-battery 7.3. DC Characteristics (VDD = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 2.4 - 3.6 V For 2-battery Operating Current IOP - 1.5 2.0 mA FCPU = 3.0MHz @ 3.0V, no load Standby Current ISTBY - - 2.0 µA VDD = 3.0V Audio output current IAUD - -1.5 - mA VDD = 3.0V, one-channel Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output High I VDD = 3.0V IOB, IOC, IOD IOH -1.0 - - mA VOH = 2.0V Output Sink I VDD = 3.0V IOB, IOC, IOD IOL 2.0 - - mA VOL = 0.8V Input Resistor Pull Low IOB, IOD RIN - 90 - Kohm VDD = 3.0V © Generalplus Technology Inc. Proprietary & Confidential 8 FEB. 23, 2006 Version: 1.0

7.4. DC Characteristics (VDD = 5.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 4.0 5.0 mA FCPU = 4.0MHz @ 5.0V, no load Standby Current ISTBY - - 2.0 µA VDD = 5.0V Audio output current IAUD - -3.0 - mA VDD = 5.0V, one-channel Input High Level VIH 3.0 - - V VDD = 5.0V Input Low Level VIL - - 0.8 V VDD = 5.0V Output High I VDD = 5.0V IOB, IOC, IOD IOH -1.0 - - mA VOH = 4.2V Output Sink I VDD = 5.0V IOB, IOC, IOD IOL 4.0 - - mA VOL = 0.8V Input Resistor Pull Low IOB, IOD RIN - 45 - Kohm VDD = 5.0V 7.5. The Relationship between the ROSC and the FCPU Frosc vs. Rosc 0 100 200 300 400 500 600 700 800 900 Rosc (KΩ) Frosc (MHz) VDD=3.0V VDD=4.5V Frosc vs. Rosc (VDD=3.0V) 0 100 200 300 400 500 600 700 800 900 Rosc Value (KΩ) Frosc (MHz) Frosc vs. Rosc (VDD=4.5V) 0 100 200 300 400 500 600 700 800 900 Rosc Value (KΩ) Frosc (MHz) © Generalplus Technology Inc. Proprietary & Confidential 9 FEB. 23, 2006 Version: 1.0

  1. APPLICATION CIRCUITS 8.1. Application Circuit - (1) GPC251A1 RESET IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 VDD XO XI AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VSS VSS TEST VDD RESET 0.1µ VDD 680 8050 0.1µ VDD Speaker 220µF 0.1µ © Generalplus Technology Inc. Proprietary & Confidential 10 FEB. 23, 2006 Version: 1.0

8.2. Application Circuit - (2) GPC251A1 RESET IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 VDD XO XI AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VSS VSS TEST VDD RESET 0.1µ VDD 680 8050 0.1µ VDD Speaker 220µF 0.1µ 680 8050 0.1µ VDD Speaker © Generalplus Technology Inc. Proprietary & Confidential 11 FEB. 23, 2006 Version: 1.0

8.3. Application Circuit - (3) GPC251A1 RESET IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 VDD AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VSS VSS TEST VDD 220µF RESET 0.1µ 680 8050 VDD Speaker XO XI 20p20p 0.1µ 0.1µ © Generalplus Technology Inc. Proprietary & Confidential 12 FEB. 23, 2006 Version: 1.0

8.4. Application Circuit - (4) GPC251A1 RESET IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 VDD XO XI AUD1 AUD2 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VSS VSS TEST VDD 220µF RESET 0.1µ 680 8050 VDD Speaker 20p20p 680 8050 VDD Speaker 0.1µ 0.1µ 0.1µ © Generalplus Technology Inc. Proprietary & Confidential 13 FEB. 23, 2006 Version: 1.0

  1. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment This IC substrate should be connected to VSS Note1: To ensure that the IC functions properly, bond VDD and VSS pins. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type GPC251A1-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). © Generalplus Technology Inc. Proprietary & Confidential 14 FEB. 23, 2006 Version: 1.0
  1. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuit s sold b y Generalplus Technology a re covered by the warranty a nd patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, e xpress, st atutory implied or b y descrip tion rega rding th e information in this publication or regarding the free dom of t he described chip(s) from p atent infringement. FUR THERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specification s and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet s and othe r information in thi s publication are current before placing orders. Products described her ein are intended fo r use in normal co mmercial applications. A pplications in volving unusual environment al or reliabil ity requirements, e.g. milit ary e quipment o r medical lif e su pport equipment, are s pecifically not re commended without additional proc essing by GENERALPLUS for such applicat ions. Please note that application circuits illustrated in this document are for reference purposes only. © Generalplus Technology Inc. Proprietary & Confidential 15 FEB. 23, 2006 Version: 1.0
  1. REVISION HISTORY Date Revision # Description Page FEB. 23, 2006 1.0 Original Note: The GPC251A1 data sheet v1.0 is a continued version of SPC251A1 data sheet v1.3. © Generalplus Technology Inc. Proprietary & Confidential 16 FEB. 23, 2006 Version: 1.0