GPC21A3 GENERALPLUS | Alldatasheet
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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GG DEC. 12, 2005 Version 1.1 PPCC2211AA33 200KKBB SSOOUUNNDD CCOONNTTRROOLLLLEERR In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviatio n devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 DEC. 12, 2005 Version: 1.1 Table of Contents PAGE
© Generalplus Technology Inc. Proprietary & Confidential 3 DEC. 12, 2005 Version: 1.1 20KB SOUND CONTROLLER 1. GENERAL DESCRIPTION The GPC21A3 is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 20K-byte ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 6 sec speech duration @ 6KHz sampling rate) and 64-byte working SRAM. It includes two Timer/Counters, 10 Software Selectable I/Os, and one 8-bit current D/A output. For audio processing, melody and speech can be mixed into one output. It operates over a wide voltage range of 2.4V - 5.1V and includes Low Voltage Reset function. The Low Voltage Reset automatically resets when the working voltage is less than 2.2V. In addition, GPC21A3 has a Clock Stop mode for power savings. The power savings mode saves the RAM contents, but freez es the oscillator, causing all other chip functions to be inoperative. The Max. CPU clock frequency is 6.0MHz. It has an Instruction Cycle Rate of 2 clock cycles (min.) - 6 clock cycles (max.). The GPC21A3 includes, not only the latest technology, but also the full commitment and technical support of Generalplus. 2. BLOCK DIAGRAM 8-bit 20K-byte ROM 64-byte SRAM INT control
10 PINS GENERAL I/O PORT
(I/O) AUD Two Timers TimeBasemicroprocessor Two 8-bit D/A (current)XI Low Voltage Reset CLK OSC IOD5-0 (I/O) 3. FEATURES 8-bit microprocessor Provides 20K-byte ROM for program and audio data 64-byte working SRAM Software-based audio processing Wide operating voltage: 2.4V - 3.6V @ 4.0MHz 3.6V - 5.5V @ 6.0MHz Supports ROSC only Max. CPU clock: 4.0MHz @ 2.4V - 3.6V 6.0MHz @ 3.6V - 5.5V Standby mode (Clock Stop mode) for power savings. M a x . 2μA @ 5.0V 500ns instruction cycle time @ 4.0MHz CPU clock Provides 10 general I/Os Two 12-bit timer/counters 6 INT sources Key wake-up function Approx. 6 sec speech @ 6KHz sampling rate with 4-bit ADPCM One D/A output Low Voltage Reset 4. APPLICATION FIELD Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese) M a t h High end toy controller Talking instrument controller General speech synthesizer Industrial controller
© Generalplus Technology Inc. Proprietary & Confidential 4 DEC. 12, 2005 Version: 1.1 5. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description VDD 8 I Supply voltage input VSS 1, 7 I Ground XI 9 I Rosc only. (Resistor should be connected to VDD) RESET 2 I RESET TEST 11 I TEST MODE AUD 10 O AUDIO OUTPUT IOC0 IOC1 IOC2 IOC3 I/O I/O I/O I/O Port C is a 4-bit bi-directional programmabl e Input / Output port with Pull-high or Open-drain option. As inputs, Port C can be in either the Pure or Pull-high states. As outputs Port C can be a Buffer or Open-drain NMOS type (sink current). IOC1: EXT INT IN IOC2: EXT COUNT IN See note 1 and 2 below. IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 I/O I/O I/O I/O I/O I/O Port D is a 6-bit bi-directional programm able Input / Output port with Pull-low or Open-drain option. As inputs, Port D can be either Pure or Pull-low states. As outputs, Port D can be either Buffer or Open-drain PMOS type (send current). (Key change, Wake up I/O) See note 1 and 2 below. * Refer to GPC Programming Guide for complete information. **Note: 1). Two input states can be specified; Pure Input, Pull-High or Pull Low. 2). Three output states can be specified as Buffer output, Open Drain PMOS output (send), or Open Drain NMOS output (sink).
© Generalplus Technology Inc. Proprietary & Confidential 5 DEC. 12, 2005 Version: 1.1 6. FUNCTIONAL DESCRIPTIONS 6.1. CPU The GPC21A3 8-bit microprocessor is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). GPC21A3 is able to perform with 6.0MHz (max.) depending on the application specifications. 6.2. ROM Area The GPC21A3 provides a 20K-byte ROM that can be defined as the program area, audio data area, or both. 6.3. RAM Area The GPC21A3 total RAM consists of 64-bytes (including Stack) at locations from $C0 through $FF. 6.4. Map of Memory and I/Os Hardw are register, I /Os USER RA M and STA CK UNUSED GENERA LPLUS TEST PROGRA M USER'S PROGRA M & DA TA A REA *MEMORY MA P ( Fr om ROM v iew ) DUMMY A REA USER‘ S PROGRA M & DA TA A REA *I/O PORT: - PORT IOC $0004 IOD $0005 - I/O CONFIG $0000 $0001 *NMI SOURCE: - I NTA (from TI M E R A) *INT SOURCE: - I NTA (from TI M E R A) - I NTB (from TI ME R B) - CPU CLK / 1024 - CPU CLK / 8192 - CPU CLK / 65536 - E XT I NT $00000 $000C0 $00100 $00200 $00600 $03FFF $07000 $07FFF 6.5. I/O Port Configuration* input data output data logic_2 control 60K VDD OD-NMOS buffer or OD : Open Drain Input/Output IOC port : IOC3 - 0 Input/Output IOD port : IOD3 - 0 60K OD : Open Drain input data logic_3 control output data OD-PMOS or buffer Input/Output IOD port : IOD5 - 4 60K OD : Open Drain input data logic_4 control output data OD-PMOS or buffer *Values shown are for VDD = 5.0V test conditions only.
© Generalplus Technology Inc. Proprietary & Confidential 6 DEC. 12, 2005 Version: 1.1 6.6. Power Savings Mode The GPC21A3 provides a power savings mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU clock by writing the STOP CLOCK Register. The CPU will then go to the stand-by mode. In such a mode, RAM and I/Os will remain in their previous states until being awakened. Port IOD7 - 0 is the only wake-up source in the GPC21A3. After the GPC21A3 is awakened, the internal CPU will go to the RESET State (Tw ≧ 65536 x T1) and then continue processing the program. Wakeup Reset will not affect RAM or I/Os (FIG.1). Tw CPU CLK Sleep Wake-up Reset FIG. 1 T1 = 1 / ( FCPU ), Tw ≧ 65536 x T1 6.7. Low Voltage Reset The GPC21A3 includes a Low Voltage Reset (LVR) function. Below the minimum power-supply voltage of 2.2V, the CPU system will become unstable and malfunction. Low Voltage Reset will reset all functions into the initial operational (stable) state if the VDD power-supply voltage drops below 2.2V (FIG.2). TW T2 2 * T1≧ 2.2V VDD CPU CLK RESET (The LVR function is the same as Power ON Reset or External Reset.) FIG. 2
© Generalplus Technology Inc. Proprietary & Confidential 7 DEC. 12, 2005 Version: 1.1 6.8. Timer/Counter The GPC21A3 contains two 12-b it timer/counters, TMA and TMB respectively. TMA can be specifi ed as a timer or a counter, but TMB can only be used as a timer. In the timer mode, TMA and TMB are re-loaded up-counters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user’s pre-set value and be up-counted again. At the same time, the carry signal will generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset by loading #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time. The read instruction will not affect the value of the counter or reset it. Clock source of Timer/Counter can be selected as follows: Timer/Counter Clock Source 12-BIT TIMER CPU CLOCK (T) or T/4 TMA 12-BIT COUNTER T/64, T/8192, T/65536 or EXT CLK TMB 12-BIT TIMER T or T/4 MODE SELECT REGISTER TMA only, select timer or counter TIMER CLOCK SELECTOR Select T or T/4 6.9. Speech and Melody Since the GPC21A3 provides a large ROM and wide range of CPU operation speeds, it is most suitable for speech and melody synthesis. For speech synthesis, the GPC21A3 can provide NMI for accurate sampling frequency. Users can record or synthesize the sound and digitize it into the ROM. The sound data can be played back in the sequence of the control func tions as designed by the user's program. Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and ADPCM. For melody synthesis, the GPC21A3 provides the dual tone mode. After selecting the dual tone mode, users only need to fill either TMA or TMB, or both TMA and TMB to generate expected frequency for each channel. The hardware will toggle the tone wave automatically without entering into an interrupt service routine. Users are able to simula te musical instruments or sound effects by simply controlling the envelope of tone output.
© Generalplus Technology Inc. Proprietary & Confidential 8 DEC. 12, 2005 Version: 1.1 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to + 60 ℃ Storage Temperature TSTO -50℃ to + 150 ℃ Note: Stresses beyond those given in the Absolute Maximum Rating ta ble may cause operational errors or damage to the device. For no rmal operational conditions see AC/DC Electrical Characteristics. 7.2. AC Characteristics (TA = 25°C) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition - 2.0 4.0 MHz VDD = 2.4V - 3.6V, 2-battery OSC Frequency FOSC2 - 4.0 6.0 MHz VDD = 3.6V - 5.5V, 3-battery 7.3. DC Characteristics (VDD = 3.0V, TA = 25°C) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 2.4 - 3.6 V For 2-battery Operating Current IOP - 1.5 2.0 mA FCPU = 3.0MHz @ 3.0V, no load Standby Current ISTBY - - 2.0 μA VDD = 3.0V Audio output current IAUD - -1.5 - mA VDD = 3.0V, one-channel Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output High I (IOC, IOD) IOH -1.0 - - mA VDD = 3.0V, VOH = 2.0V Output Sink I (IOC, IOD) IOL 2.0 - - mA VDD = 3V, VOL = 0.8V Input Resistor (IOD) RIN - 110 - Kohm Pull Low, VDD = 3.0V 7.4. DC Characteristics (VDD = 5.0V, TA = 25°C) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 4.0 5.0 mA FCPU = 4.0MHz @ 5.0V, no load Standby Current ISTBY - - 2.0 μA VDD = 5.0V Audio output current IAUD - -3.0 - mA VDD = 5.0V, one-channel Input High Level VIH 3.0 - - V VDD = 5.0V Input Low Level VIL - - 0.8 V VDD = 5.0V Output High I (IOC, IOD) IOH -1.0 - - mA VDD = 5.0V, VOH = 4.2V Output Sink I (IOC, IOD) IOL 4.0 - - mA VDD = 5.0V, VOL = 0.8V Input Resistor (IOD) RIN - 60 - Kohm Pull Low, VDD = 5.0V
© Generalplus Technology Inc. Proprietary & Confidential 9 DEC. 12, 2005 Version: 1.1 7.5. The Relationship between the ROSC and the FCPU 0.0 1.0 2.0 3.0 4.0 0 200 400 600 800 Rosc ( Kohms ) Fosc ( MHz ) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 200 400 600 800 Rosc ( Kohms ) Fosc ( MHz ) 7.5.3. Frequency vs. temperature 01 02 03 04 05 06 07 0 0.96 1.00 0.98 1.02 1.04 Temperature ( )℃ FCPU/FCPU(25 )℃ Frequency normalized to 25℃ Rosc=200Kohms VDD=5.0V 7.5.4. Frequency vs. VDD 0.0 1.0 2.0 3.0 4.0 5.0 2 . 03 . 04 . 05 . 0 VDD ( Volts ) Fosc ( MHz ) Rosc = 100 Kohms Rosc = 200 Kohms 0123456 Fosc ( MHz ) IOP ( mA ) VDD = 3V VDD = 4.5V
© Generalplus Technology Inc. Proprietary & Confidential 10 DEC. 12, 2005 Version: 1.1 8. APPLICATION CIRCUITS 8.1. Application Circuit GPC21A3 RESET IOC3 IOC2 IOC1 IOC0 VDD XI AUD IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VSS TEST 1 , 7 VDD VDD RESET 50K 150K 680 8050 Speaker 0.1μ VDD 0.1μ 220μF 0.1μ
© Generalplus Technology Inc. Proprietary & Confidential 12 DEC. 12, 2005 Version: 1.1 9. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment This IC substrate should be connected to VSS Note1: To ensure that the IC functions properly, bond all VDD and VSS pins. Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type GPC21A3-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc. Proprietary & Confidential 13 DEC. 12, 2005 Version: 1.1 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provis ions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, st atutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 14 DEC. 12, 2005 Version: 1.1 11. REVISION HISTORY Date Revision # Description Page DEC. 12, 2005 1.1 Modify “max. operating voltage” to section 3 and 7. 3, 8 OCT. 31, 2005 1.0 Original 14