GPC192A GENERALPLUS | Alldatasheet

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GENERALPLUS T ECHNOLOGY I NC. re serves the rig ht to change t his documentation w ithout p rior n otice. I nformation pr ovided by GENE RALPLUS TECHNOLOGY INC. is believ ed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no w arranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPCC119922AA 119922KKBB SSoouunndd CCoonnttrroolllleerr FEB. 20, 2006 Version 1.0 In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

© Generalplus Technology Inc. Proprietary & Confidential 2 FEB. 20, 2006 Version: 1.0

  1. GENERAL DESCRIPTION The GPC192A is a CPU bas ed t wo-channel speech/melod y synthesizer which includes a CMOS 8- bit microprocessor , 192K-byte ROM for speech and melody data (speech compressed by a 4-bit ADPCM with approx. 63 sec speech duration @ 6.0KHz sampling rate) and 1K-b yte working SRAM. In addition, it includes two timer/counters, 10 -bit ADC, PGA, 8 x 10 FIFO, two OP Amp., 32 sof tware pr ogrammable I/Os, and one PWM audio output. For audio processing, melod y and speech can be mi xed into one output. It operates over a wide voltage range of 2.4V - 5.5V. The Low Voltage Reset function automatically resets CPU whenever th e working volt age drop s belo w 2 .2V. Moreover , GPC192A has a Clock S top mo de for po wer sa vings that saves the RAM content s, but freezes the oscillator . The Clock S top mode makes all other functions inoperative. The maximum CPU clock frequency is 5.0MHz. It has an Instruction C ycle Rate of 2 clock cy cles ( min.) - 6 clock cy cles ( max.). The G PC192A includes not only the latest technolog y, b ut also the fu ll commitment and technical support of Generalplus. 2. BLOCK DIAGRAM 8-bit 12-bit timer/counter PWM output

32 PIN GENERAL I/O PORT

IOA[7:0] IOB[7:0] IOC[7:0] IOD[7:0] ADEC RESET RESET AUDP AUDN IOA[7:0] IOB[7:0] IOC[7:0] IOD[7:0] XI/R XO Clock R/X'TAL VMIC 10-bit AD PGA 8x10 FIFO OP2 IP1 IN1 OP1 IP2 IN2 OP1 OP2 ADIP PGAIP VREF PGAOP 3. FEATURES „ 8-bit microprocessor „ Provides 192K-byte ROM for program and audio data „ 1K-byte working SRAM „ Software-based audio processing „ Wide operating voltage: 2.4V - 5.5V @ 5.0MHz „ Supports Crystal Resonator or ROSC (with Mask option) „ Max. CPU clock: 5.0MHz @ 2.4V - 5.5V „ Standby mode (Clock Stop mode) for power savings. M ax. 2.0µA @ 5.0V „ 400ns instruction cycle time @ 5.0MHz CPU clock „ Provides 32 general I/Os „ Two 12-bit timer/counters „ 6 INT sources „ Key wake-up function „ 10-bit ADC and PGA „ Two independent OP Amp. „ 8 x 10 FIFO „ One PWM audio output (single speaker) „ Low Voltage Reset (with mask option) „ Approx. 63 sec speech @ 6.0KHz sampling rate with 4-bit ADPCM 4. APPLICATION FIELD „ Intelligent educational toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese) M ath „ High-end toy controller „ Talking instrument controller „ General speech synthesizer „ Industrial controller © Generalplus Technology Inc. Proprietary & Confidential 3 FEB. 20, 2006 Version: 1.0

  1. SIGNAL DESCRIPTIONS* Mnemonic PIN No. Type Description VDD 18 I VDD for I/O and logic circuit PVDD 47 I VDD for audio output VSS 9 I GND for I/O and logic circuit PVSS 49 I GND for audio output AVDD 19 I VDD for analog circuit VMIC 20 O Microphone voltage VREF 21 O Reference voltage IP1 22 I OP1 non-invert input IN1 23 I OP1 invert input OP1 24 O OP1 output VDACT 25 O DAC output for test mode measure use only OP2 26 O OP2 output IN2 27 I OP2 invert input IP2 28 I OP2 non-invert input PGAIP 29 I PGA input PGAOP 30 O PGA output ADIP 31 I ADC input AVSS 32 I Analog ground XI 34 I Oscillator crystal input or RESISTOR (Resistor should be connected to VDD) XO 35 O Oscillator crystal output TEST 36 I Test pin, NC RESET 37 I Active low reset for the chip AUDP AUDN O O Audio output IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 I/O I/O I/O I/O I/O I/O I/O I/O Port A is an 8-bit bi-directional In put / Output port with Pull-high or Open -drain option. As inputs, Port A can be in either the Pure or Pull-high st ates. As outputs, Port A3 - 0 can be either Buf fer or Ope n-drain NMOS t ypes (Sink current). Port A7 - 4 can be either Buffer or Open-drain PMOS types (Send current) See note 1 and 2 below. IOB0 IOB1 IOB2 IOB3 IOB4 IOB5 IOB6 IOB7 I/O I/O I/O I/O I/O I/O I/O I/O Port B is an 8-bit bi-directional Input / Output port with Pull-low or Open-drain opti on. As inputs, Port B can be in eith er the Pure o r Pull-low states. As outputs, Port B can be either Buffer or Open-drain NMOS types (Sink current). See note 1 and 2 below. IOC0 IOC1 I/O I/O Port C is an 8-bit bi-directional In put / Out put port with Pull-high or Open-d rain option. As inputs, Port C can be in either the Pur e or P ull-high states. As outputs Port C can © Generalplus Technology Inc. Proprietary & Confidential 4 FEB. 20, 2006 Version: 1.0

Mnemonic PIN No. Type Description IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 I/O I/O I/O I/O I/O I/O be a Buf fer type or Open-drain t ype. Port C3 - 0 are Open-drain NMOS t ype ( Sink current) and Port C7 - 4 are Open-drain PMOS (Send current). IOC0: EXT RC-OSC OUTPUT IOC2: EXT RC-OSC INPUT / EXT COUNT IN See note 1 and 2 below. IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 I/O I/O I/O I/O I/O I/O I/O I/O Port D is an 8-bit bi-directional Input / Output port with Pull-low or Open-drain option. As inputs, Port D can be either buffer or Open-drain PMOS (Send current). Also, Port D can be sof tware p rogrammed for wake-up I /O pi ns. (Programmable I/O, Key Change, Wake-up I/O). See note 1 and 2 below. * Refer to GPC Programming Guide for more information. **Note: 1.) Two input states can be specified: Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified: Buffer output, Open Drain PMOS output <send>, Open Drain NMOS output <sink>. © Generalplus Technology Inc. Proprietary & Confidential 5 FEB. 20, 2006 Version: 1.0

  1. FUNCTIONAL DESCRIPTIONS 6.1. CPU The 8-bit microprocessor of GPC192A is a high performance processor equipped with Accumulator , Progr am Counter , X Register, S tack pointer and Pro cessor S tatus Register (it is the same as the 6502 instruction st ructure). GPC192A is able to perform with 5 .0MHz (ma x.) depending on the application specifications. 6.2. Oscillator The GPC192A supports AT-cut parallel resonant oscillated Cr ystal / Resonator or RC O scillator or ex ternal clock s ources b y mask option (select one from those three t ypes). The design of application circu it should fo llow t he vendors’ specifications or recommendations. The diagrams listed below are typical X’TAL / ROSC circuits for most applications: (a) Crystal or Ceramic Resonator Connections 20 pf 20 pf Rosc (b) RC Oscillator Connections VDD GPC192A XI/R XO GPC192A XI/R XO 6.3. Mask Option The GPC192A has the following mask option: hSupports Crystal Resonator or ROSC with mask option. 6.4. ROM Area The GPC192A provides a 192K-byte ROM that can be defined as the progr am are a, audio dat a ar ea, or both. To access ROM, users should program the BANK SELECT Register, choose bank, and access address to fetch data. 6.5. RAM Area The total RAM consists of 1K b ytes (including S tack) at locations from $80 through $47F. 6.6. Map of Memory and I/Os *I/O PORT: HW register, I/Os USER RAM and STACK UNUSED GENERALPLUS TEST PROGRAM USER'S PROGRAM & DATA AREA ROM BANK #0 ROM BANK #1 $00000 $00080 $00480 $00500 $00900 $08000 $2FFFF - PORT IOA $0002 IOB $0003 IOC $0004 IOD $0005 *NMI SOURCE: - I/O CONFIG $0000 $0001 - INTA (from TIMER A) *INT SOURCE: - INTA (from TIMER A) - INTB (from TIMER B) - CPU CLK / 1024 - CPU CLK / 8192 - CPU CLK / 65536 - EXT INT *MEMORY MAP (From ROM view) ROM BANK #2 ROM BANK #3 $10000 $18000 ROM BANK #4 ROM BANK #5 $20000 $28000 © Generalplus Technology Inc. Proprietary & Confidential 6 FEB. 20, 2006 Version: 1.0

6.7. I/O Port Configuration* Input/Output IOA port : IOA3 - 0 input data output data logic_0 control 90K VDD OD-NMOS buffer or OD : Open Drain Input/Output IOA port : IOA7 - 4 input data output data logic_1 control 90K OD-PMOS buffer or OD : Open Drain VDD Input/Output IOB port : IOB3 - 0 60K OD : Open Drain input data logic_2 control output data OD-NMOS or buffer Input/Output IOB port : IOB7 - 4 60K OD : Open Drain input data logic_3 control output data OD-NMOS or buffer Input/Output IOC port : IOC3 - 0 input data output data logic_4 control 90K OD-NMOS buffer or OD : Open Drain VDD Input/Output IOC port : IOC7 - 4 input data output data logic_5 control 90K OD-PMOS buffer or OD : Open Drain VDD Input/Output IOD port : IOD3 - 0 60K OD : Open Drain input data logic_6 control output data OD-PMOS or buffer Input/Output IOD port : IOD7 - 4 60K OD : Open Drain input data logic_7 control output data OD-PMOS or buffer * Figures shown are for VDD = 5.0V test conditions only. © Generalplus Technology Inc. Proprietary & Confidential 7 FEB. 20, 2006 Version: 1.0

6.8. Timer/Counter 6.9. ADC (Analog to Digital Converter) The GPC192A contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be spe cified as a t imer or a counter , but TMB can only be a timer. In the timer mode, TMA and TMB are re-loaded up -counters. When time r overflow s from $0F FF to $0000, the carry signal will make the timer automatically reload to the user’s pre-set value and up-count again. At the same time, the carry signal will generate an INT signal if the corresponding bit is enabled in the INT ENABLE R egister. If TMA is used as a counter, users can reset it b y loading “0” into the counter. After the counter has been activated, t he value of the c ounter can also be read from the counter at the same time. Clock source of Timer/Counter can be selected as follows: Timer/Counter Clock Source 12-BIT TIMER CPU CLOCK (T) or T/4 TMA 12-BIT COUNTER T/64, T /8192, T/65536 o r EX T CLK TMB 12-BIT TIMER T or T/4 MODE SELECT REGISTER TMA only, select timer or counter TIMER CLOCK SELECTOR Select T or T/4 The way to ma ke AD work is using an ADC ( analog-to-digital converter) t o se nd a h ypothetical data and com pare it with input signal by comp arator. GPC192A determines th e actual value in two ways, auto mode and manual mode. In auto mode, hardware automatically creates a value for binar y search b y SAR (successive-approximation register) and will acquire a 10-bit PCM data at the end of search. Du ring converting, sy stem cont rols sample/hold hardware by its own. The second method is manual mode. Within t his mode, user s can use th eir own algorithms such as DM, ADM, PCM, ADPCM, etc. In the auto mode, users are req uired onl y to setup t he ri ght sample freq uency b y setting Timer B, an d sy stem ente rs into auto DAC mo de. More over, users can also use FIFO to reduce interrupt redundanc y to improve the perf ormance. In manual mode, use rs need to send the h ypothetical value into DAC register and read the comp ared result back from hard ware to decide w hether the h ypothetical value is lower or higher than the actual input sign al. Within this mode, FI FO is disabled and users need to con trol sample and hold on their own. © Generalplus Technology Inc. Proprietary & Confidential 8 FEB. 20, 2006 Version: 1.0

6.10. Power Savings Mode The GPC192A provides a power savings mode (standby mode) for applications that require ver y low st and-by curr ent. T o en ter standby mode, the Wake-Up Register should be enabled and then stop the CPU clock by writing the STOP CLOCK Register. As a result, the CPU goes to the st and-by mode. In such a mode, RAM and I/Os r emain in their pre vious states until being awoken. Port IOD7 - 0 is the only wake-up source in the GPC192A. After the GPC192A is aw oken, the internal CPU will go to the RESET State (T w ≧ 65536 x T1) an d then continue to execute the program. Wakeup Reset will not influence RAM or I/Os (FIG.1). Tw CPU CLK Sleep Wake-up Reset Internal FIG. 1 T1 = 1 / (FCPU), Tw 65536 x T1≧ 6.11. L ow Voltage Reset The GPC192A includes a Low V oltage Reset (L VR) f unction. Below the minimum power-sup ply volt age of 2.2V, the CPU system will become unst able and malfunction. Lo w V oltage Reset will reset all functions into the initial ope rational (st able) state if the VD D po wer-supply v oltage dro ps below 2.2V (FIG.2) (with mask option). 2.2V VDD CPU CLK TWRESET T2 2 * T1≧ (The LVR function is the same as Power ON Reset or External Reset.) FIG. 2 © Generalplus Technology Inc. Proprietary & Confidential 9 FEB. 20, 2006 Version: 1.0

6.12. F IFOs GPC192A provides a FIF O with (8+1) (depth) x 10(width). FIFO reduces the time to fetch ADC sa mple data. It only works when auto mode ADC is enabled. There are two flags users can read, Empty Flag and Full Flag. The Empt y Flag ind icates the FIF O status when FIFO is empty. The Full Flag represents FIFO status when FIFO is e qual or great th an FI FO dept h samples. For example, suppose users setup FIFO as FIFO depth to 4 samples, once FIFO received 4 samples without an y dat a read b y CPU (which means FIFO keeps the amount of samples inside), the Full Flag w ill active. The FIFO de dicates (8+1) x 10 depth which means the maximum dat a FIFO can store is 8 samples plus one over-come sam ple. Once FIFO over -run (me ans dat a is still coming while FIFO is keeping 9 samples already), the last coming data will overwrite the 9 th data in FIFO regardless the assignment of FIFO depth. FIFO can be re-initialized or cleared by power on reset, writing data to setup FIFO depth, setting to manual mode or turning-off the ADC_EN. 6.13. Speech and Melody Since the GPC 192A provides a large R OM and high CP U operating speeds, it is one of the most suitable devices for speech and melody synthesis. For speech synthesis, the GPC192A can provide NMI fo r accurate sampling freque ncy. Users can record or synthesize the sound and digitize it into the R OM. The sound data can be played back in the sequence of the control functions as designed b y the user 's pro gram. Sever al algorithms are recommended for high fidelity and compression of sound including PCM, L OG PC M, and ADPCM. Fo r melod y s ynthesis, the GPC192A provides dual tone mode. Once the GPC192A enters the dual tone mode, users only need to fill either TMA or TMB, or both TMA and TMB to the tone f requency for each channel, and count the envelope of each ch annel. The hardware will toggle the tone wave automatically without INT. © Generalplus Technology Inc. Proprietary & Confidential 10 FEB. 20, 2006 Version: 1.0

  1. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to + 60℃ Storage Temperature TSTO -50℃ to + 150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions, see AC/DC Electrical Characteristics. 7.2. AC Characteristics (TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Condition Input Bias Current IBIAS - 1.0 5.0 µA - Input Offset Voltage VOFFSET - 10 - mV - Slew Rate - 0.5 - V/µs VDD = 5.0V Output Voltage Swing 0.2 - VDD - 0.2 V - Input Impedance - 1.2 - MΩ - ADC Reference Voltage VREF 1.1 1.3 1.5 V - ADC Input Range VIN VREF - 1/2VREF - VREF+ 1/2VREF V - VMIC Output Current IO - 2.0 - mA When VDD = 2.4V, Vo = 2.0V 7.3. DC Characteristics (VDD = 3.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Condition Operating Voltage VDD 2.4 - 3.6 V For 2-battery Operating Current IOP - 6.0 - mA FCPU = 3.58MHz @ 3.0V, no load Standby Current ISTBY - - 2.0 µA VDD = 3.0V PWM Output High I IPOH1 - -80 - mA VDD = 3.0V, VOH = 2.5V For one channel PWM Output High I IPOH2 - -140 - mA VDD = 3.0V, VOH = 2.0V For one channel PWM Output Low I IPOL1 - 80 - mA VDD = 3.0V, VOL = 0.5V For one channel PWM Output Low I IPOL2 - 140 - mA VDD = 3.0V, VOL = 1.0V For one channel Input High Level VIH 2.0 - - V VDD = 3.0V Input Low Level VIL - - 0.8 V VDD = 3.0V Output high I (IOA, IOC, IOD) IOH -1.0 -2.0 - mA VDD = 3.0V, VOH = 2.0V Output low I (IOA, IOC, IOD) IOL 3.0 5.0 - mA VDD = 3.0V, VOL = 0.8V Input Resistor (IOA, IOC) RIN - 220 - KΩ Pull-high, VDD = 3.0V Input Resistor (IOD) RIN - 90 - KΩ Pull-low, VDD = 3.0V © Generalplus Technology Inc. Proprietary & Confidential 11 FEB. 20, 2006 Version: 1.0

7.4. DC Characteristics (VDD = 5.0V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Condition Operating Voltage VDD 3.6 - 5.5 V For 3-battery Operating Current IOP - 9.5 - mA FCPU = 4.0MHz @ 5.0V, no load Standby Current ISTBY - - 2.0 µA VDD = 5.0V PWM Output High I IPOH1 - -155 - mA VDD = 5.0V, VOH = 4.2V For one channel PWM Output High I IPOH2 - -300 - mA VDD = 5.0V, VOH = 3.3V For one channel PWM Output Low I IPOL1 - 175 - mA VDD = 5.0V, VOL = 0.8V For one channel PWM Output Low I IPOL2 - 310 - mA VDD = 5.0V, VOL = 1.67V For one channel Input High Level VIH 3.0 - - V VDD = 5.0V Input Low Level VIL - - 0.8 V VDD = 5.0V Output high I (IOA, IOC, IOD) IOH -1.0 -3.5 - mA VDD = 5.0V, VOH = 4.2V Output low I (IOA, IOC, IOD) IOL 4.0 8.0 - mA VDD = 5.0V, VOL = 0.8V Input Resistor (IOA, IOC) RIN - 110 - KΩ Pull-high, VDD = 5.0V Input Resistor (IOD) RIN - 50 - KΩ Pull-low, VDD = 5.0V © Generalplus Technology Inc. Proprietary & Confidential 12 FEB. 20, 2006 Version: 1.0

  1. APPLICATION CIRCUITS 8.1. Application Circuit - (1) GPC192A XOXI VDD VDD C14 RESET R12 Speaker C15 IOD[7:0] IOC[7:0] IOB[7:0] IOA[7:0] VMIC PGAOP PGAIP IP2 IN2 OP2 OP1 IN1 IP1 VREF C17 0.1µF R11 10K 0.1µF R10 10K C16 100µF 10V 0.1µF 82pF R8 340K 68.1K 820pF 84.5K C6 0.1µF 649K 820pF 100KR5 100K 649KC3 820pF 10K 100µF 10V 100K MIC1 ELECTRET 0.1µ PVDD -0.1µF AVDD 100µF10V C10 100µF10V 0.1µF 0.1µ AVDDVDDPVDD PVSS VSS AVSS RESET IOA[7:0] IOB[7:0] IOC[7:0] IOD[7:0] VDD AVDD PVDD VSSAVSS PVSS AUDP AUDN ADIP C11 C13 © Generalplus Technology Inc. Proprietary & Confidential 13 FEB. 20, 2006 Version: 1.0

8.2. Application Circuit - (2) 20p 20p 32768 GPC192A RESET XOXI AUDP AUDN RESET Speaker VMIC ADIP PGAOP PGAIP IP2 IN2 OP2 OP1 IN1 IP1 VREF C17 0.1µF R11 10K 0.1µF R10 10K C16 100µF 10V 0.1µF 82pF R8 340K 68.1K 820pF 84.5K C6 0.1µF 649K 820pF 100KR5 100K 649KC3 820pF 10K 100µF 10V 100K MIC1 ELECTRET VDD VSS VDD C14C15AVSS AVDD PVDD PVSS 0.1µ PVDD -0.1µF AVDD 100µF10V C10 100µF10V 0.1µF AVDDVDDPVDD PVSS VSS AVSS 0.1µ IOD[7:0] IOC[7:0] IOB[7:0] IOA[7:0]IOA[7:0] IOB[7:0] IOC[7:0] IOD[7:0] C11 C13 C12 C18 © Generalplus Technology Inc. Proprietary & Confidential 14 FEB. 20, 2006 Version: 1.0

  1. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment This IC substrate should be connected to VSS Note1: To ensure IC function properly, please bond all of the VDD and VSS pins. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type GPC192A-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). © Generalplus Technology Inc. Proprietary & Confidential 15 FEB. 20, 2006 Version: 1.0
  1. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold b y Generalplus Technology a re covered by the warranty a nd patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, e xpress, st atutory implied or b y descrip tion rega rding th e information in this publication or regarding the free dom of the described chip(s) from p atent infringement. FUR THERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specification s and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and othe r information in thi s publication are current before placing orders. Products described her ein are intended fo r use in normal co mmercial applications. A pplications in volving unusual environment al or reliabil ity requirements, e.g. milit ary e quipment o r medical lif e su pport equipment, are s pecifically not re commended without additional proc essing by GENERALPLUS for such applicat ions. Please note that application circuits illustrated in this document are for reference purposes only. © Generalplus Technology Inc. Proprietary & Confidential 16 FEB. 20, 2006 Version: 1.0
  1. REVISION HISTORY Date Revision # Description Page FEB. 20, 2006 1.0 Original Note: The GPC192A data sheet v1.0 is a continued version of SPC192A data sheet v0.3. © Generalplus Technology Inc. Proprietary & Confidential 17 FEB. 20, 2006 Version: 1.0