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GPBA01B GENERALPLUS | Alldatasheet

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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENE RALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus. MAY 28, 2007 Version 1.1 GGPPBBAA0011BB BBuuss EExxtteennddeerr

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Version: 1.1 Table of Contents PAGE

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Version: 1.1

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Version: 1.1 BUS EXTENDER 1. GENERAL DESCRIPTION GPBA01B, a low cost 8-bit bus extender (BEX) by GENERALPLUS, manipulates two pins, MC0 and MC1, to receive the multiplexed 8-bit address/data bus from main processor, e.g. GENERALPLUS GPL13x and GPLB3x and…etc. GPBA01B is able to facilitate the expansion of memory capacity up to 4M bytes of RAM/ROM/EPROM/FLASH, or 25 I/O pins. Users may concatenate numbers of GPBA01B (up to 7) to fit application needs. Plus, GPBA01B equips a Cl ock divider to easily generate clock for IR application or any other applications. As compared with GPBA01A, majority of functions are identical, but AC characteristics have better pe rformance and DVP mode is phased out. 2. FEATURES Fully compatible with GPBA01A expect DVP mode A speed-up version of bus extender*: One GPBA01B Expansible up to 4M bytes or 25I/Os. Daisy chain logic concatenates up to 7 extenders Supports varieties of memory types: SRAM, ROM, EPROM, EEPROM and FLASH Note: when co-work with Generalplus controller, e.g. GPL13X or GPLB3X series and GPR23LXXX Mask ROM series, it is applicable to 4MHz@2.4V 6MHz@3.6V. 3. APPLICATION FIELD Memory extension, I/O extension for data bank and any others. 4. BLOCK DIAGRAM 4.1. Work as Memory Extender MC[1:0] AD[7:0] GPBA01B CIOUT MC[1:0] AD[7:0] MPU AT29C040 D[7:0] A[21:0] CE OE WE A[21:0] CE OE WE Flash Memory GPL131/GPLB31,...) 4.2. Work as I/O Extender MC[1:0] AD[7:0] GPBA01B CIOUT MC[1:0] AD[7:0] MPU Key MatrixP17-P10 P27-P20 P07-P00 (GPL131/GPLB31,...) 4.3. GPBA01B Block Diagram A/D bus control Address latch Register Bank Daisy chain IO/Addr Multiplexing Clock Divider MC1 MC0 AD[7:0] XI XO CLKO CI cez wrz rdz a[15:0] d[7:0] AHG ALG P0[7:0] P1[7:0] P2[7:0] P55(WE) OSCO(OE) CO P0[6:0](B[7:0]) P27(CE0) P07(CE1) P06(CE2) P1[7:0](A[7:0]) P2[6:0](A[14:8])

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Version: 1.1 5. SIGNAL DESCRIPTIONS Mnemonic History alias PIN No. Type Description CI PCI 17 I Cascade in for daisy chain CO PCO 16 O Cascade out for daisy chain AD7 - AD0 PD7 - PD0 4 - 11 I/O Multiplexing Address/Data bus(AD BUS) MC1, MC0 PMC1, PMC0 1, 2 I Input pins to indicate AD bus status P27( CE0 ) P26 - P20 XP27 - XP20 26 - 20 I/O P2 are short for P27-P20. Memory extender P27( CE0 ): Memory-0 chip-enable pin P26-P20: Memory offset address A[14:8]. I/O extender Input Mode: Pull-low internal Output Mode: Pure P17 - P10 XP17 - XP10 37 - 44 I/O P1 are short for P17-P10. Memory extender P17-P10: Memory offset address A[7:0]. I/O extender Input Mode: Pull-low internal Output Mode: Pure P07( CE1) P06( CE2 ) P05 - P00 XP07 - XP00 28 30 - 35 I/O P0 are short for P07-P00. Memory extender P07( CE1): Memory-1 chip-enable pin P06/( CE2 ): Memory-2 chip-enable pin P06-P00: Memory bank address B[6:0], GPBA01B support up to 128 banks, each bank is 32K bytes. I/O extender Input Mode: Pull-low internal Output Mode: Pure OSCO( OE ) PRDZ 18 O Memory extender OSCO( OE ): External memories output-enable signal I/O extender Output only: 1.84MHz oscillator output P55( WE ) PWRZ 19 O Memory extender P55( WE ): External memories write-enable signal I/O extender Output only control by B5 of $0023 XI XTAL1 12 I 1.84 MHz crystal input (20p capacitor required) XO XTAL2 13 O 1.84 MHz crystal output (20p capacitor required) CLKO ICLK 15 O Clock divider output VDD 36 I Positive supply VSS 3 I Ground reference DVP 14 I Test mode, please leave it open. Pull-low internal. Note1: Fully compatible with GPBA01A, expect DVP mode is discarded. Note2: There are built-in pull low resistors at all input and bi-direction pins except AD [7:0], MC0, MC 1, CI. The pull low resistors of bi-direction pin are disabled when working in output mode. Note3: Internal pull-low resistor with value of approx. 37K Ohms @ VDD = 5.0V; 78K Ohms @ VDD = 3.0V. Note4: Generalplus strongly recommend user use Mnemonic name instead of History alias for easy understanding. Note5: Physical addresses are concatenated from {B [6:0], A [14:8], A [7:0]}.

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Version: 1.1 6. FUNCTIONAL DESCRIPTIONS 6.1. The Easiest System Bus extender (BEX) plays a role as an interface between MPU (GPLB31, GPL131…) and general-purposed (third-party) memory products. In fact, the BEX is a bus translator that translates the AD bus of BMI tm to the general-purposed memory bus. Below figure show the easiest way to use GPBA01B, the MPU send 11 signals to GPBA01B, GPBA01B latch the address and then send it to AT29C040 flash memory, GPBA01B also have responsibility to generate CE , OE , WE to the memory. On read cycle, the memory output the data at the common bus (AD7-AD0); while write cycle, GPL131 drive the written-data to AD7-AD0. The AD bus (AD7-AD0) may Address High-Byte (AH), Address-Low-Byte (AL) and 8-bit bi-direction data. Also, the AD bus is common for MPU, GPBA01B, and memory. All of these may drive the bus depending on MC1, MC0 status. MC[1:0] AD[7:0] GPBA01B CIOUT MC[1:0] AD[7:0] MPU AT29C040 D[7:0] A[21:0] CE OE WE A[21:0] CE OE WE Flash Memory GPL131/GPLB31,...) 6.2. Address/Data Bus Control The GPBA01B (Bus extender) is a bridge between MPU (GPL130A, GPLB31A…) and gener al-purposed (third-party) memory products. The MC1 and MC0 are the control signals for AD7-AD0, which can be three states: Address High-Byte (AH), Address-Low-Byte (AL) and 8-bit bi-direction data. When MC1 is high, AD [7:0] functions as an address-bus, otherwise the AD [7:0] becomes a data-bus. In address-bus mode, AD [7:0] signifies high-address, A [15:8], when MC0 is high; in contrast, AD [7:0] expresses low-address, A [7:0], when MC0 is low. In data-bus mode, AD [7:0] represents data, D [7:0], which will be read from CPU when MC0 is high and CPU writes data to AD [7:0] when MC0 is low. P0, P1, P2, WE , OE can be utilized as address-line, chip-enable, output-enable or write-enable for addressing external memory chip (please refer to Bus Extender Pin Assignment for 8 configurations). The number of pins needed for addressing depends on configuration and the remaining pins used for I/O port. When used as memory extender, chip-enable ( CE ), output-enable ( OE ) and write-enable ( WE ) operate in negative logic (voltage low stands for active, and voltage high stands for inactive). The address lines in clude A [14:0] (presenting CPU address) and B [6:0] (presenting bank register). 6.2.1. Decode table MC1 decides AD bus to be address or data bus, and MC0 decides operation mode (Read or Write). MC1 MC0 AD BUS H H AH H L AL L H Data for Read L L Data for Write 6.2.2. Timing relations between control signals, AH, AL and data. MC0 Read Cycle: MC1 AD AH AL DATA for read Write Cycle: MC0 MC1 AD AH AL DATA for write

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Version: 1.1 6.3. Example on Address Mapping 1. CI=0 2. CI=1 3. %MOV P_0DH_BMIVolumeID,#%00000001 4. %MOV P_23H_BEXConfig,#%1100-0000 ; set CFG=6(B[7:5]), three 1MB memory enable 5. %MOV P_00H_BankSelect,#%1010-0000 ; select MEM1’s bank0,(i.e. CE1 will active when access) 6. %MOV 0x8000, 0x1111 ; write 0x1111 to MEM0[0x00000] 7. %MOV 0xBFFF, 0x2222 ; write 0x2222 to MEM0[0x03fff] 8. %MOV 0x4000, 0x3333 ; write 0x3333 to MEM0[0x04000] 9. %MOV 0x7fff, 0x4444 ; write 0x4444 to MEM0[0x7ffff] 10. %MOV P_00H_BankSelect,#%1010-0001 ; select MEM1’s bank1 11. %MOV 0x8000, 0x5555 ; write 0x5555 to MEM0[0x08000] 12. %MOV 0xBFFF, 0x6666 ; write 0x6666 to MEM0[0x0bfff] 13. %MOV 0x4000, 0x7777 ; write 0x7777 to MEM0[0x0c000] 14. %MOV 0x7fff, 0x8888 ; write 0x8888 to MEM0[0xfffff] After consecutive 8 write ADDRESS DATA Memo 00000H 1111H BANK0, 32KB per bank … … 03FFFH 2222H 04000H 3333H … … 07FFFH 4444H 08000H 5555H BANK1 … … 0BFFFH 6666H 0C000H 7777H … … 0FFFFH 8888H 10000H … BANK2 … … … 6.4. Address Mapping on a System Bus extender usually use $4000~$BFFF for memory extension, while $0000~003f for register setting. Each bank are 32K bytes, $8000H~$BFFFH are mapped to $0000H~$3FFFH; $4000H~$7FFFH are mapped to $4000H~7FFFH. ROM (16KB) (Bank)H I/O$0000-$003F $2000-$3FFF $4000-$7FFF $8000-$BFFF $C000-$FFF9 $FFFA-$FFFF CPU View $00000-$03FFF $04000-$07FFF $08000-$0BFFF $0C000-$0FFFF $10000-$13FFF $14000-$17FFF ROM View $C000-$FFFF always mapping into 0L n n . . . $0040-$03FF ROM (16KB) (Bank)L ROM (16KB) Ext. RAM (8KB) RAM Interrupt Sensor Buffer $0C00-$1FFF RAM $0800-$084F

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Version: 1.1 6.5. Daisy Chain There are 11 pins connecting from MPU to BEX, except MC0, MC1, and AD bus. In addition, there is another pin, named CI, the Cascade-In of BEX. When CI goes from low to high, the VID/SID of BEX will be reset and must be setup. When accessing BEX, the CI pin must keep in logical high level. Both CI and CO provide the circui try to concatenate up to seven BEX. In such case, the CO (Cascade-Out) of the former BEX is connected to the CI of next BEX to form a daisy-chain. After CI of st BEX goes from low to high, the 1 st setting of Volume ID, VID, (setting $000DH) will apply to the 1 st BEX. After the 1 st BEX is configured, it will raise its CO. The CO of the 1 st BEX is connected with the CI of the 2 nd BEX; as a result, the configuration will apply to the 2 nd BEX, and…etc. CO MC[1:0] AD[7:0] BEXA CIOUT MC[1:0] AD[7:0] MPU CO MC[1:0] AD[7:0] BEXB CI 0 0 0 0 For correction operation, if there are 5 BEXs on the system, issue exactly five unique VID. After all VID have been set, any writing activity to $000D will be taken as “selecting”. For example, after setting the VID of the BEXs as 1, 2, 3... up to 7, simply write 3 to $000DH to select and access it when MPU intends to access BEX of ID 3. Note that the sequence of ID is not necessary of 1, 2, 3...7. The mind that the 1 st ID is applied to the 1 st BEX in the daisy chain. The 0 is not a valid ID. Because we want all BEXs to share the same BMI, every BEX needs two variables, Volume-ID (VID) and Select-ID (SID) inside. We must send unique VID to every BEX and then we should choose one of these BEX by setting SID. At any time, only one BEX can operate . Which BEX will be activated depending on which BEX has VID=SID (but VID cannot be 0). $000DH register is used for set both VID and SID, but VID can be written once only. When MPU sends OUT=0, CI of BEXA=0 causes VID, SID, CO of BEXA=0, too; CO of BEXA always causes VID, SID, CO of BEXB=0. Finally, all functions in these two GPBA01B are disabled and all registers remain at the previous states, except volume-id ( VID) and select-id (SID), which are reset to zero. 6.5.1. Example We will describe the action of two BEX on the daisy chain as follows. It’s important that MPU shares bus with BEXs. How can we identify BEX and send a unique VID to each BEX? It is achieved by CI and CO. CO MC[1:0] AD[7:0] BEXA CIOUT MC[1:0] AD[7:0] MPU CO MC[1:0] AD[7:0] BEXB CI 0 0 0 0 VID =0 SID=0 VID =0 SID=0 $000DH register works for setting a unique VID for each BEXs, and then acts as SID only. VID are write-once register. The first step is accessing BEXA and then accessing BEXB as follows: 1. MPU’s OUT=0 2. MPU’s OUT=1 3. Send_addr_data($000d,$03) ; Set 3 to VID of BEXA(VID write once) 4. Send_addr_data($000d,$05) ; Set 5 to VID of BEXB(VID write once) 5. Send_addr_data($000d,$03) ; Set 3 to SID of BEXA and BEXB ( BEXA active, BEXB inactive) 6. Send_addr_data($0023,$XX) ; Configure BEXA as ‘Memory extender’ or ‘I/O extender’ 7. ( Access BEXA…. ) 8. ….. 9. Send_addr_data($000d,$05) ; Set 5 to SID of BEXA and BEXB (BEXA inactive, BEXB active) 10. Send_addr_data($0023,$XX) ; Configure BEXB as ‘Memory extender’ or ‘I/O extender’ 11. ( Access BEXB….. )

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Version: 1.1 After step 9, the status of BEXA and BEXB are as following CO MC[1:0] AD[7:0] BEXA CIOUT MC[1:0] AD[7:0] MPU CO MC[1:0] AD[7:0] BEXB CI 0 0 0 0 VID =3 SID=5 VID =5 SID=5 active!! 6.5.2. Configuration BEX has two modes: memory extender (major mode), and I/O extender. As we use the BEX, we need to set configuration register immediately after volume-id is given. Writing to B[7:5] of $0023H establishes the GPBA01B configurations. . When GPBA01B works as memory extender, it can extend from 1 to 3 memories, depending configur ation. Please refer to Register description chapter. When using as I/O extender, P0, P1 and P2 are bi-directional pins. The value written to B[4:0] of $0023H defines directions. Logical “1” stands for output and logical “0” stands for input. Specially, P55 ( WE ) and OSCO ( OE ) cannot operate in input direction. 6.6. Clock Divider Writing to PS [1:0] (B [5:4] of register $0021H) and CDP [7:0] (register $0022H) sets the frequency of CLKO out. Writing a logical one to OSCE (B7 of register $0021H) makes the crystal oscillator enable. Writing a logical zero to OSCE makes the crystal oscillator disable, and reduces power consumption. When both OSCE and CLKOE are logical one, CLKO is enabled. Divide m Divide n Divide 2 CLKO Crystal oscillator XI XO OSCO OSCE CLKOE OSCO CLKO

0 X H L

Freq1 is dependent on crystal. Freq2 = freq1/ (m*n*2), where n=2^PS [1:0], m=256-(CDP [7:0] value) OSCO is available in CFG0 and CFG1

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Version: 1.1 7. REGISTER DESCRIPTION 7.1. P_00H_BMIBank ($0000) (W) Bank Selection Register B7 B6 B5 B4 B3 B2 B1 B0 W must be1 BANK6 BANK5 BANK4 BANK3 BANK2 BANK1 BANK0 B6 - B0 are BANK6-BANK0. The extended memory is dividing into banks, 32K bytes per bank. Each AD BUS cycle can only address up to 32KB. To access another bank, you should issue P_00H_BMIBank ($0000) command. When GPBA01B connects to one 4MB memory, B6 - B0 are bank selections for total of 128 banks. In CFG=6 mode, one GPBA01B can support up to three memory; thus, B6 - B5 act as memory selections while B4 - B0 act as bank selection. 7.1.1. CFG=3 Example CFG=3, one 4MB is configured and B6 - B0 are all for 128-bank selections. B6-B0 Description B6 A21 B5 A20 B4 A19 B3 A18 B2 A17 B1 A16 B0 A15 7.1.2. CFG=6 Example CFG=6, three 1MB are configured and B4 - B0 are for 32-bank selections. B6-B5 Description

00 CE2 will be asserted

01 CE1 will be asserted

7.2. P_0DH_BMIVolumeID ($000D) (W) Bus memory Volume ID Setup & Selection B7 B6 B5 B4 B3 B2 B1 B0 Write-once - - - - - VID2 VID1 VID0 W - - - - - SID2 SID1 SID0 VID [2:0]: Volume-ID for unique identify the GPBA01B on the daisy-chain, write once only. SID [2:0]: Select-ID for selection one of GPBA01Bs on the daisy-chain. 7.3. P_20H_BEXPort0 ($0020)(R/W) Extender Port0 B7 B6 B5 B4 B3 B2 B1 B0 I/O extender: P07-P00: bi-direction port to communication with external device. The direction is set by B [2:0] of $0023. Memory extender: No function.

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Version: 1.1 7.4. P_21H_BEXPort1 ($0021) (R/W) Extender Port1 & Function Control (W) B7 B6 B5 B4 B3 B2 B1 B0 W OSCE CLKOE PS1 PS0 1 X X X I/O extender: P17-P10: bi-direction port to communicate with external device. The direction is set by B3 of $0023. Memory extender: OSCE: Oscillator Enable CLKOE: Clock Output Enable PS [1..0]: Pre-scalar Counter B 3 : M u s t b e 1 . 7.5. P_22H_BEXPort2 ($0022) (R/W) Extender Port2 & ClockDividerPreload (W) B7 B6 B5 B4 B3 B2 B1 B0 W CDP7 CDP 6 CDP 5 CDP 4 CDP 3 CDP 2 CDP 1 CDP 0 I/O extender: P27-P20: bi-direction port to communication with external device. The direction is set by B4 of $0023. Memory extender: CDP [7:0]: Clock divider preload value. 7.6. P_23H_BEXConfig ($0023)(W) Bus Extender Configuration B7 B6 B5 B4 B3 B2 B1 B0 W CFG2 CFG1 CFG0 P55 DIR2 DIR1 DIR03 DIR01 DIR00 CFG [2..0]: Bus Extender Configuration Number (0~7) P55: ExterndPort55 Output Bit (P55 is output pin only) DIR2: ExtendPort2 Control (1: Output, 0: Input) DIR1: ExtendPort1 Control (1: Output, 0: Input) DIR03: ExtendPort0 [7..3] Control (1:Output, 0: Input) DIR01: ExtendPort0 [2..1] Control (1:Output, 0: Input) DIR00: ExtendPort0.0 Control (1: Output, 0: Input) Note 1: P55 is available for output only if CFG=0 or 1 Note 2: If the extend port is configured as input, there will be an internal pull-low resistor (37K Ohms @ VDD=5V or 78K Ohms @ VDD=3V).

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Version: 1.1 7.6.1. Bus extender pin assignment for 8 configurations Configuration Register $0023[7:5] PINs Name 000(I/O) 001(I/O) 010(32KB) 011(4MB) 100(1MB) 101(4MB) 110(1MB) 111(2MB) P00 I/O I/O I/O B0 B0 B0 B0 B0 P01 I/O I/O I/O B1 B1 B1 B1 B1 P02 I/O I/O I/O B2 B2 B2 B2 B2 P03 I/O I/O I/O B3 B3 B3 B3 B3 P04 I/O I/O I/O B4 B4 B4 B4 B4 P05 I/O I/O I/O B5 I/O B5 I/O B5 P06 I/O I/O I/O B6 I/O B6 CE2 CE2 P07 I/O I/O I/O I/O CE1 CE1 CE1 CE1 P10 I/O I/O A0 A0 A0 A0 A0 A0 P11 I/O I/O A1 A1 A1 A1 A1 A1 P12 I/O I/O A2 A2 A2 A2 A2 A2 P13 I/O I/O A3 A3 A3 A3 A3 A3 P14 I/O I/O A4 A4 A4 A4 A4 A4 P15 I/O I/O A5 A5 A5 A5 A5 A5 P16 I/O I/O A6 A6 A6 A6 A6 A6 P17 I/O I/O A7 A7 A7 A7 A7 A7 P20 I/O I/O A8 A8 A8 A8 A8 A8 P21 I/O I/O A9 A9 A9 A9 A9 A9 P22 I/O I/O A10 A10 A10 A10 A10 A10 P23 I/O I/O A11 A11 A11 A11 A11 A11 P24 I/O I/O A12 A12 A12 A12 A12 A12 P25 I/O I/O A13 A13 A13 A13 A13 A13 P26 I/O I/O A14 A14 A14 A14 A14 A14 P27 I/O I/O CE0 CE0 CE0 X CE0 X OSCO/ OE OSCO OSCO OE OE OE OE OE OE P55/ WE LOW HIGH WE WE WE WE WE WE Total I/O Available 25 25 8 1 2 0 1 0 No. of Memories available 0 0 1 1 2 1 3 2 Total memory size 0 0 32KB 4MB 2MB 4MB 3MB 4MB The memory is divided into banks, 32KB per bank. banks are address by B6-B0, while A14-A0 are offset address of bank. ITEM Description Memo B6-B0 Memory extender: Bank selection pin A14-A0 Memory extender: Address pin to access 32KB memory in a bank CE2 , CE1, CE0 Memory extender: Chip enable pin X Memory extender: Don’t use. I/O I/O extender: Pins can be configured as input or output O I/O extender: Output pin only OSCO I/O extender: Crystal output P55 I/O extender: When CFG=0 output Low, when CFG=1 output High

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Version: 1.1 7.6.2. Memory Mapping Summary with Configuration 2~7 Mapping Address Bank Select Value($0000) Mode Chip Selection CFG=2 Asserting CE0 to select last 8KB memory CFG=4 Bank, with b[4:0] become 11111. CFG=5 CFG=6 $2000~$3FFF (8K) CFG=7 1XXXXXXX CFG=2 Access 32KB Memory with CE0 1BBBBBBB CFG=3 Access 4MB Memory with CE0 10XBBBBB CFG=4 Access 1MB Memory with CE1 11XBBBBB CFG=4 Access 1MB Memory with CE0 1BBBBBBB CFG=5 Access 4MB Memory with CE1 100BBBBB CFG=6 Access 1MB Memory with CE2 101BBBBB CFG=6 Access 1MB Memory with CE1 11XBBBBB CFG=6 Access 1MB Memory with CE0 10BBBBBB CFG=7 Access 2MB Memory with CE2 $8000~$BFFF $4000~$7FFF (32K each bank, mainly used for memory extension) 11BBBBBB CFG=7 Access 2MB Memory with CE1 Note1: “B” is for extender memory bank selection; “KB” means K-byte and “MB” for M-byte. Note2: “X” means “don’t care” which has no effect on bank selection.

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Version: 1.1 8. STANDBY CONDITION Item Description CI VDD VSS MC1-MC0 VDD AD7-AD0 VDD or VSS P0, P1, P2 Memory extender: Leave open I/O extender: Output mode: inhibit any pull-low or pull-up Input mode: leave open or VSS DVP Leave open or VSS Register OSCE(B7 of $0021) Must be set to 0 9. PCB LAYOUT CONSIDERATION Due to MC0 and Mc1 are edge triggering signal, the trace must be as short as possible; shielding with ground signal is better.

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Version: 1.1 10. ELECTRICAL SPECIFICATIONS 10.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V + < 7.0V Input Voltage Range V IN -0.5V to V + + 0.5V Operating Temperature T A 0℃ to +70 ℃ Storage Temperature T STO -50℃ to +150 ℃ Note: Stresses beyond those given in the Absolute Maximum Ratings tabl e may cause operational errors or damage to the device. For no rmal operational conditions see AC/DC Electrical Characteristics. 10.2. DC Characteristics (VDD = 2.4V - 5.5V, T A = 0℃ to 70 ℃) Limits Characteristics Symbols Min. Typ. Max. Units Test conditions Operating Voltage VDD 2.4 - 5.5 V - - 0.32 0.6 mA/MHz VDD = 2.4V, C L = 10pF - 0.55 1.0 mA/MHz VDD = 3.6V, C L = 10pF Operating Current I CC - 0.88 2.0 mA/MHz VDD = 5.5V, C L = 10pF - 1.4 3.0 mA/MHz VDD = 2.4V, C L = 50pF - 2.3 4.0 mA/MHz VDD = 3.6V, C L = 50pF Operating Current I CC2 - 3.6 6.0 mA/MHz VDD = 5.5V, C L= 50pF Standby Current I STBY - - 1.0 μA All signal un-toggle, TA = 25℃ Input High Voltage V IH 0.7VDD - VDD V - Input Low Voltage V IL -0.3V - 0.2 VDD V - Output High Voltage V OH 0.75 VDD - - V IOH = 1.0mA @ 2.4V IOH = 1.5mA @ 3.0V IOH = 4mA @ 5.0V Output Low Voltage V OL - - 0.15VDD V IOL = 0.8mA @ 2.4V IOL = 1.2mA @ 3.0V IOL = 3mA @ 5.0V Pull-low MOS Current I PL3 - 38 - μA VDD = 3.0V, V IN = VDD Pull-low MOS Current I PL3 - 157 - μA VDD = 5.0V, V IN = VDD

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Version: 1.1 10.3. AC Characteristics (VDD = 2.4V - 5.5V, TA = 0℃ to 70 ℃) Test Condition VIH = VDD, VIL = 0V, Input Rise and Fall Times = 1ns, I/O Timing Reference Level = VDD/2, Output Load: CLOAD = 100pF Limits Characteristics Symbols Min. Typ. Max. Units Test conditions AH Setup Time T ahs 10 - - ns - AH Hold Time T ahh 10 - - ns - AL Setup Time T als 10 - - ns - 10 - 25 ns VDD = 2.4V 10 - 15 ns VDD = 3.6V AL Hold Time T alh 10 - 10 ns VDD = 5.5V Data Setup Time T ds 10 - - ns - Data Hold Time T dh 10 - - ns - - - 15 ns VDD = 2.4V - - 9 ns VDD = 3.6V MC1 Falling to MC0 Rising T m1m0 - - 4 ns VDD = 5.5V - 31 49 ns VDD = 2.4V - 21 30 ns VDD = 3.6V Address High Delay T ahd - 16 22 ns VDD = 5.5V - 32 58 ns VDD = 2.4V @ ah hold time = 10n - 20 31 ns VDD = 3.6V @ ah hold time = 10n Address Low Delay T ald - 17 23 ns VDD = 5.5V @ ah hold time = 10n - 46 69 ns VDD = 2.4V - 28 40 ns VDD = 3.6V MC1 Rising to Chip-enable Falling Tcezf - 22 30 ns VDD = 5.5V - 29 46 ns VDD = 2.4V - 19 28 ns VDD = 3.6V MC1 Rising to Chip-enable Rising Tcezr - 14 20 ns VDD = 5.5V - 36 52 ns VDD = 2.4V - 23 34 ns VDD = 3.6V MC1 Falling to Write-enable Falling Twrzf - 18 23 ns VDD = 5.5V - 19 25 ns VDD = 2.4V - 13 20 ns VDD = 3.6V MC1 Falling to Write-enable Rising Twrzr - 10 15 ns VDD = 5.5V - 37 54 ns VDD = 2.4V - 24 35 ns VDD = 3.6V MC1 Falling to Read-enable Falling Trdzf - 18 25 ns VDD = 5.5V - 24 39 ns VDD = 2.3V - 16 24 ns VDD = 3.6V MC1 Rising to Read-enable Rising Trdzr - 12 17 ns VDD = 5.5V - 54 90 ns VDD = 2.3V - 34 54 ns VDD = 3.6V Read Port Data Delay Time T dd - 25 37 ns VDD = 5.5V Note1: Talh Max value prevent bus fighting. Note2: When write memory cycle, please refer to accompany memory. Note3: Measure from al_in to al_out.

17 MAY 28, 2007

Version: 1.1 10.4. Read Port Cycle MC1 AH tahh MC0 AD[7:0] tahs AL talh tals for CPU data tdh tdd P0,P1,P2 read port data tm1m0 10.5. Read Memory Cycle MC1 AH tahh MC0 AD[7:0] tahs AL talh tals data trdh AH tahd MA[21:15] MA[14:8] already reay on previous cycle ALMA[7:0] tald CEZ[2:0] RDZ half cycle trdzf tcezf trdd tm1m0 trdzr tcezr Note: trdd,trdh depend on external memory

18 MAY 28, 2007

Version: 1.1 10.6. Write Port Cycle MC1 AH tahh MC0 AD[7:0] tahs AL talh tals data tdh tds 10.7. Write Cycle MC1 AH tahh MC0 AD[7:0] tahs AL talh tals data td01s AH tahd MA[21:15] MA[14:8] already reay on previous cycle ALMA[7:0] tald CEZ[2:0] WRZ half cycle twrzf tcezf td01h Note: td01h depends on external memory, please pay extra attention to twrzr twrzr tcezr

19 MAY 28, 2007

Version: 1.1 11. APPLICATION CIRCUITS & EXAMPLE PROGRAM 11.1. Simplest Application--O ne Flash Memory Extension MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 MA18 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD2 AD0 AD4 CE0# MA3 AD5 MA9 MA16 MA15 MA18 MA17 MA2 CI CE2# MA1 MA12 MA13 AD3 MA8 MA4 GND MA5 MA0 MA7 VDD MA20 MA11 MA14 OE# MA10 CE1# MA6 AD1 MC0 MC1 AD6 AD7 AD0 MA19MA19MA19 AD0 CI AD5 AD6 AD4 AD2 MC1 AD3 MC0 AD7 AD1 MA17 WE# WE# OE# CE0# AT29C040 FLASH 12 13 A16 A15 A12 A0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A13 A14 WE A17 A18 SPBA01B_PLCC84 P01 P02 P00 VDD P17 P16 P15 P14 P13 P12 P11 P10 MC1 MC0 VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 P03 P04 P05 P06(CE2#) P07(CE1#) P27(CE0#) P26 P25 P24 P23 P22 P21 P20 P55(WE#) OSCO(OE#) CI CO CLKO DVP XO XI JP1 (SPLC131/SPLB31...) CI MC1 MC0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Use SPBA01B--BEX(Bus Extender) to access standard memory MPU %PullBEXENLow ; Set CI to 0 %PullBEXENHigh ; Set CI to 1 LDA #1 STA P_0DH_BexVolID ; Set Volume-ID and Select-IDto 1 LDA #%011XXXXX STA P_23H_BEXConfig ; Set CFG=3 for 4MB configuration ; 128 banks in total(bank0~bank127) LDA #%1 000-0010 STA P_00H_BexBank ; Set bank to 2, ; mapping $8000-$BFFF to $010000-$013FFF ; mapping $4000-$7FFF to $014000-$017FFF (access bank 2) ... LDA #%1 000-0000 STA P_00H_BexBank ; Set bank to 0, ; mapping $8000-$BFFF to $000000-$003FFF ; mapping $4000-$7FFF to $004000-$007FFF (access bank 0) ... LDA #%1 111-1111 STA P_00H_BexBank ; Set bank to 127, ; mapping $8000-$BFFF to $3F8000-$3FBFFF ; mapping $4000-$7FFF to $3FC000-$3FFFFF (access bank 127) ... Note: %PullBEXENLow and %PullBEXENHigh are macros that control the high or low for GPBA01B’s CI. SPLC131/GPLB31…) GPBA01B_PLCC84 GPBA01B

20 MAY 28, 2007

Version: 1.1 11.2. GPLB30A/31A with Bus Extender and Bus Flash GPRxxx Bus Flash GPLB30A/31A General- Purposed Third-Party External Memories SRAM ROM FLASH Address bus RD CEs WRMC0 MC1 ENP VCC_GPL13X VCC_GPBA An RD WR CS Output GPBA Bus Extender (I/O Extender) CI 8-Bit AD Bus AD0 - AD7MC0 MC1 The area in solid line can be viewed as a micro-controller with address bus. The area in dash line can be viewed as the memory within the bus extender.

21 MAY 28, 2007

Version: 1.1 11.3. One BEX with Three Memory AD2 AD0 AD4 CE0# MA3 AD5 MA9 MA16 MA15 MA18 MA17 MA2 CI MA1 MA12 MA13 AD3 MA8 MA4 GND MA5 MA0 MA7 VDD MA20 MA11 MA14 OE# WE# MA10 MA6 AD1 MC0 MC1 AD6 AD7 MA19MA19MA19 AD3 AD2 AD4 AD5 MC0 CI AD0 AD7 AD6 MC1 AD1 AD6 WE# MA10 MA14 MA2 AD5 MA16 MA9 MA13 AD2 MA3 MA7 AD4 MA1 MA5 AD0 MA4 MA12 AD7 AD1 MA0 OE# AD3 MA15 MA8 MA11 CE0# MA6 CE1# AD0 MA5 MA6 MA3 MA13 AD2 MA10 AD5 WE# AD6 AD7 MA1 MA11 AD3 MA8 MA15 AD1 MA12 MA16 MA2 AD4 MA7 MA9 MA14 OE# MA0 MA4 MA0 OE# MA14 MA9 MA7 AD4 MA2 MA16 MA12 AD1 MA15 MA8 AD3 MA11 MA1 MA4 AD7 AD6 WE# AD5 MA10 AD2 MA13 MA3 MA5 AD0 MA6 CE2# CE2# CE1# AT29C010 FLASH 12 13 A16 A15 A12 A0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A13 A14 WE AT29C010 FLASH 12 13 A16 A15 A12 A0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A13 A14 WE AT29C010 FLASH 12 13 A16 A15 A12 A0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A13 A14 WE SPBA01B_PLCC84 P01 P02 P00 VDD P17 P16 P15 P14 P13 P12 P11 P10 MC1 MC0 VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 P03 P04 P05 P06(CE2#) P07(CE1#) P27(CE0#) P26 P25 P24 P23 P22 P21 P20 P55(WE#) OSCO(OE#) CI CO CLKO DVP XO XI JP1 (SPLC131/SPLB31...) CI MC1 MC0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Use SPBA01B to access three 1Mb flash memory(C MPU %PullBEXENLow ; Set CI to 0 %PullBEXENHigh ; Set CI to 1 LDA #1 STA P_0DH_BexVolID ; Set Volume-ID and Select-IDto 1 LDA #%110XXXXX STA P_23H_BEXConfig ; Set CFG=6 for three 1MB configuration ; 128 banks in total( bank0~bank127) LDA #%110 0-0010 ; Select memory0, set bank to 2 (SPLC131/GPLB31…) GPBA01B_PLCC84 Use GPBA01B to access three 1Mb flash memory (CFG=6)

22 MAY 28, 2007

Version: 1.1 STA P_00H_BexBank (access memory0 bank 2) ... LDA #%101 0-0000 STA P_00H_BexBank ; Select memory1, set bank to 0 (access memory2 bank 3) ... LDA #%100 1-1111 STA P_00H_BexBank ; Select memory2, set bank to 31 (access bank 127) ... 11.4. Two BEXs form Daisy-Chain CE1# MA5 MA6 MA3 MA13 MA10 WE# MA1 MA11 MA8 MA15 MA12 MA16 MA2 MA7 MA9 MA14 OE# MA0 MA4 MA0 OE# MA14 MA9 MA7 MA2 MA16 MA12 MA15 MA8 MA11 MA1 MA4 WE# MA10 MA13 MA3 MA5 MA6 CE2# P26 P02 P55 P23 P20 P24 P05 P04 P03 GND P22 P25 P21 P06 P07 P27 P23 P24 P27 P26 P25 P22 P21 P20 P07 P06 P05 P04 P03 P02 P01 P00 AD1 MA17 MA4 MA2 MA14 AD6 AD4 AD2 CE2# WE# AD3 AD4 AD0 AD3 MA0 MC1 MC0 AD2 AD1 CE1# AD7 AD4 MA11 MA8 AD7 MA16 AD1 MA12 MC0 AD4 MA20 AD0 AD7 AD3 AD5 MA5 AD0 AD6 COA_CIB MA19MA19MA19 MC1 MC0 AD6 AD2 AD5 AD5 MA18 AD2 AD1 VDD MA6 AD7 GND OE# AD0 AD3 MC1 AD3 MA10 AD5 MA15 AD0 AD7 AD4 AD2 AD1 MPU_CIA MA3 MA13 MA9 AD6 AD5 MA7 MA1 AD6 MA18 P14 VDD P16 P01 P11 P00 P12 P10 P17 P15 P13CLKO AT29C020 12 13

30 A16

(SPLC131/SPLB31...) CI MC1 MC0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SPBA01B_PLCC84 P01 P02 P00 VDD P17 P16 P15 P14 P13 P12 P11 P10 MC1 MC0 VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 P03 P04 P05 P06(CE2#) P07(CE1#) P27(CE0#) P26 P25 P24 P23 P22 P21 P20 P55(WE#) OSCO(OE#) CI CO CLKO DVP XO XI AT29C020 12 13 SPBA01B_PLCC84 P01 P02 P00 VDD P17 P16 P15 P14 P13 P12 P11 P10 MC1 MC0 VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 P03 P04 P05 P06(CE2#) P07(CE1#) P27(CE0#) P26 P25 P24 P23 P22 P21 P20 P55(WE#) OSCO(OE#) CI CO CLKO DVP XO XI 1.84MHz BEXA is memory extender, BEXB is IO extender and clock divider MPU KEY MATRIX BEXA BEXB BEXA CFG=7; BEXB CFG=0 (1.84MHz/(m*n*2) %PullBEXENLow ; Set CI to 0 %PullBEXENHigh ; Set CI to 1 LDA #1 STA P_0DH_BexVolID ; Set BEXA Volume-ID to 1, BEXA Select-ID=1 LDA #3 STA P_0DH_BexVolID ; Set BEXB Volume-ID to 3 ; BEXA VID=1, SID=3(inactive) ; BEXB VID=3, SID=3(active) LDA #%000 11111 STA P_23H_BEXConfig ; Set CFG=0 ; BEXB act as IO extender, all port are output LDA #%10101010 ; BEXB: P0=AAH (SPLC131/GPLB31… ) GPBA01B_PLCC84 GPBA01B_PLCC84

23 MAY 28, 2007

Version: 1.1 STA P_20H_BEXPort0 LDA #%01010101 STA P_22H_BEXPort2 ; BEXB: P2=55H LDA #1 STA P_0DH_BexVolID ; BEXA: VID=1, SID=1(active) ; BEXB: VID=3, SID=1(inactive) LDA #%11 00-0010 STA P_00H_BexBank ; BEXA: Select memory1, set bank to 2 LDA #%1110-1000 STA P_21H_BEXPort1 ; BEXA: oscillator enable, CLKO enable, pre-scale = 2 LDA #%0011-1100 STA P_22H_BEXPort2 ; BEXA: CDP[7:0]=60, CLKO=1.84MHz/(2^2)/60/2=3.83KHz (access memory0 bank 2) ... ; Access BEXA memory1

24 MAY 28, 2007

Version: 1.1 12. PACKAGE/PAD LOCATIONS 12.1. PAD Assignment and Locations VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 28 27 26 25 24 P22 P21 CI CO CLKO DVP XO P00 P17 P16 P15 P14 P13 P12 P11 P10 P23 P24 P25 P26 P27(CE0) P05 P04 P03 P02 P01 XI AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 MC0 MC1 Sunplus P20 P55(WE) OSCO(OE) P07(CE1) P06(CE2) X Y (0,0) This IC substrate should be connected to VSS Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible. 12.2. Ordering Information Product Number Package Type GPBA01B - C Chip form

25 MAY 28, 2007

Version: 1.1 13. GPBA01B EVALUATION BOARD 13.1. Evaluation Board—one BEX with Three Memory Extension

26 MAY 28, 2007

Version: 1.1 14. LAYOUT IMAGES/ DIE PHOTOS 14.1. Die Photo 14.1.1. Characteristic marks (whole chip)

27 MAY 28, 2007

Version: 1.1 14.1.2. Characteristic marks (left-bottom corner)

28 MAY 28, 2007

Version: 1.1 15. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, st atutory implied or by description regarding the information in t his publication or regarding the freedom of t he described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GE NERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders . Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.

29 MAY 28, 2007

Version: 1.1 16. REVISION HISTORY Date Revision # Description Page May 28, 2007 1.1 1. Modify “FEATURES” in section 2. 2. Modify “CFG=3 Example” in section 7.1.1. JUN. 05, 2006 1.0 Original Note: The GPBA01B data sheet v1.0 is a continued version of SPBA01B data sheet v1.0.

Product Information

GPBA01B specifications and overview.

Summary

Bus Extender

Description

Bus Extender

Source title GPBA01B Datasheet(PDF) - Generalplus Technology Inc.

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