F0321818B

F0321818B EUDYNA | Alldatasheet

Document overview

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• PDF pages: 11

Technical content

• +5 or -5 V single power supply
• 20 dB typical gain
• 2.0 GHz typical -3 dB cutoff frequency
• On-chip matching to 50 Ω
• 55 mA typical operating current
• Differential input and output
• Differential ECL compatible input

Applications

• Post-amplifier of an optical receiver circuit up to 2.5 Gb/s
• Logic gate buffer to interface between analog circuit and logic circuit ♦♦♦♦♦ Functional Description The F0321818B is a stable GaAs integrated limiting amplifier for use in a post-amplifier of an optical receiver circuit up to 2.5 Gb/s. The F0321818B typically specifies a small signal gain of 20 dB (Rs=RL=50 Ω) with a 3 dB-cutoff-frequency of 2.0 GHz. It features single +5 or -5 V supply operation, excellent VSWR’s of 1.1:1, and a typical dissipation current of 55 mA. The F0321818B can be also used as interface circuits in sensing systems and measure- ment instruments. Emitter coupled logic (ECL) or source coupled FET logic (SCFL) circuits are the most popular IC’s for high speed digital circuits; the F0321818B operating under a differential ECL compatible input condition is the best choice as the interface IC to join ana- log circuits to ECL circuits or conventional GaAs logic IC’s. 02.04.24 Limiting Amplifier F0321818B

2 GHz Bandwidth

F0321818B2 GHz Limiting Amplifier ♦♦♦♦♦ Absolute Maximum Ratings Ta=25 °C, unless specified ♦♦♦♦♦ Recommended Operating Conditions VSS = GND ♦♦♦♦♦ Electrical Characteristics Ta = 25 °C, VDD = +5 V, VSS = GND, unless specified Parameter Symbol Value Units Supply Voltage Supply Current Input Voltage Swing (AC) Output Voltage Ambient Operating Temperature Storage Temperature V DD IDD VIN+ , VOUT- VOUT+ , VOUT- Ta Tstg VSS -0.5 to VSS +7 VDD -2.5 to VDD 0 to +70 -55 to +125 V mA V V Parameter Symbol Test Conditions Value Units Min. Typ. Max. Supply Current Input Bias Point Output bias Point VSWR (IN, OUT) Gain -3dB High Frequency Cutoff Maximum Output Swing (single output) I DD VIN VOUT SWR GV Fc Vom Pin=-40dBm Pin=-40dBm f=1MHz Pin=-40dBm RL=50 Ω f=1MHz Pin=-40dBm RL=50 Ω RL=50 Ω 0.4 1.5 3.5 1.1 2.0 0.6 1.8 0.8 mA V V dB GHz V retemaraPl obmyS eulaV stinU .niM. pyT. xaM egatloVylppuSV DD 57.45 6 4.5V daoLdelpuoCCAL R- 0 5- Ω erutarepmeTgnitarepOtneibmAT a 05 20 7C °

2 GHz Limiting Amplifier F0321818B

Amp. Amp. Output Buffer VIN+ LPF+ VIN- LPF- V OUT+ VOUT- VSS1 VSS2 VDD VDD Input AC Ground Input AC Ground Output Output Supply Voltage Supply Voltage Supply Voltage Supply Voltage

F0321818B2 GHz Limiting Amplifier ♦ ♦ ♦ ♦ ♦ Dia Pad Assignments *V DD1 is not connected to VDD2 in the bare chip IC. *V SS1 is not connected to VSS2 in the bare chip IC. * For +5 V users, we recommended the Pads of No.16,17 are connected to power supply pads (+5 V) and the pads of No. 6, 9,15,18 are connected to GND pads. * We recommend that unused input pin should be terminated to GND via coupling capacitor and 50 ohm load. Example : (unused input pin) → (coupling capacitor) → (50 ohm load) → (GND) * On the back of the bare die, we mount it on GND but no problem for mounted on VSS. .oNl obmyS) mµ(setanidrooCretneC. oNl obmyS) mµ(setanidrooCretneC

50Ω 50Ω 1) AC Characteristics F0321818B LPF- V SS VIN- VOUT- LPF+ V DD VDD VIN+ VOUT+ 0.1 µF 0.1µF 0.1µF Pin =-40dBm 2200 pF Vector Network Analyzer 50Ω50Ω 2) Limiting Characteristics 50Ω 50Ω 50Ω LPF- V SS VIN- VOUT- LPF+ V DD VDD VIN+ VOUT+ 0.1 µF 0.1µF 0.1µF 2200 pF Pulse Pattern Generator Attenuator Sampling OscilloscopeDATA CLOCK * DC BLOCK (PICOSECIND PULSE LABS, MODEL 5501) F0321818B

F0321818B2 GHz Limiting Amplifier ♦ Typical AC Characteristics (1) Gain Ta =25 °C, VDD =+5 V, VSS =GND, Pin =-40 dBm, RL =50 Ω, 300 kHz-3 GHz (2) Dependence of Gain and High Frequency Cutoff on Power Supply Variations Ta =25 °C, VDD =-5 V, VSS =GND, Pin =-40 dBm, RL =50 Ω, 300 kHz-3 GHz Gain (dB) High Frequency Cut-off (GHz) 4.5 5.0 5.5 VDD (V) 4.5 5.0 5.5 VDD (V) 2.10 2.12 2.14 2.16 2.18 2.20 1M 10M 100M 1G Frequency (Hz) (dB)

♦♦♦♦♦ Typical AC Characteristics (3) VSWR's Ta =25 °C, VDD =+5 V, VSS =GND, Pin =-40 dBm, RL =50 Ω, 300 kHz - 3 GHz (4) S parameters on Smith Chart Ta =25 °C, VDD =+5 V, VSS =GND, Pin =-40 dBm, RL =50 Ω S11 at VIN+ S22 at VOUT+ START 100 MHz STOP 3 GHz START 100 MHz STOP 3 GHz *Almost same characteristics is exhibited at VIN- *Almost same characteristics is exhibited at VOUT- 1M 10M 100M 1G Frequency (Hz) 1M 10M 100M 1G Frequency (Hz) [at VIN+] [at VOUT+ ]

F0321818B2 GHz Limiting Amplifier 10 mV/div (a) VIN+ = 5 mVp-p (b) VIN+ = 50 mVp-p 100 psec/div 100 mV/div (c) VIN+ = 500 mVp-p 100 mV/div 100 psec/div 100 psec/div ♦ Typical Limiting Characteristics (1) Eye diagrams for 2.5 Gb/s NRZ Pseudo-random Data Response 223-1, Ta = 25 °C, VDD =5 V, VSS =GND, RL =50 Ω

♦ General Description A post-amplifier is positioned between a preamplifier (an amplifier for a faint photocurrent from PIN photo diode) and a decision circuit (a circuit to discriminate the logic level of the received signal), enlarging the output signal from the preamplifier to a higher level to dis- criminate the logic level. The input signal amplitude of the post-amplifier, meaning the output signal of the preamplifier, varies widely, because the optical signal power received by the PIN photo diode depends on the length of the transmission line. Therefore, the post-ampli- fier should function to output an almost constant signal level under widely varying input volt- age. This is called a limiting function, and the F0321818B provides excellent limiting charac- teristics. As shown in the data sheet, the increase of only 200 mV (400 mV→600 mV) in the output voltage can be observed even if the 2.5 Gps input signal varies widely from 50 mV to 500 mV Wide use analog IC’s having satisfactory limiting functions as described above can not be found except for the F0321818B. Customized IC’s for each application or a circuit de- signed by discrete transistors are believed to have been developed. Post Matching Input/output VSWR’s of the F0321818B are well-designed for 50 Ω, typically showing excellent VSWR’s of 1.1:1. Therefore, the F0321818B can be applied for 50 Ω systems with no external parts. Furthermore, the fine VSWR characteristics provide stable operation even for cascade connections of two IC’s for a higher gain. The excellent VSWR characteristics of the F0321818B gives full play in a clock recovery system using SAW filters, because the impedance mismatch has a significant effect on the quality of the recovered clock signal. Gain Consideration The F0321818B has a small signal gain of 20 dB. A too high gain can be harmful because of parasitic oscillation. If a slightly higher gain is needed, a 6 dB higher gain of 26 dB can be obtained by a high impedance termination instead of a 50 Ω load. A double gain can be achieved by simple cascade connection if a still higher gain is required.

F0321818B2 GHz Limiting Amplifier ♦ Noise Performance The F0321818B based on the GaAs FET fabrication process intrinsically has more ex- cellent low-noise characteristics compared with IC’s based on the silicon bipolar process. Many transmission systems often demand superior signal-to-noise ratio; the F0321818B is the best choice for such applications. The differential circuit configuration in the input and output enable a complete differential operation to reduce common mode noise: simple single ended input and output operation is also available. LPF+ & LPF- The F0321818B has two terminals, LPF+ and LPF-, for AC ground. These terminals are connected to ground by a capacitor. The time constant of the feedback loop in the F0321818B depends on the capacitor, giving the lower frequency cutoff of the circuit by the large capacitor. A 0.1 micro farad is employed for conventional applications. Die-Chip Description The F0321818B is shipped like the die-chip described above. The die thickness is typi- cally 450 µm ± 20 µm with the available pad size uncovered by a passivation film of 95 µm square. The material of the pads is TiW/Pt/Au and the backside is metalized by Ti/Au. ♦ Assembling Condition SEI recommends the assembling process as shown below and affirms sufficient wire- pull and die-shear strength. The heating time of one minutes at the temperature of 310 °C gave satisfactory results for die-bonding with AuSn performs. The heating and ultrasonic wire-bonding at the temperature of 150 °C by a ball-bonding machine is effective.

♦ Quality Assurance For the Die-chip products, there is only one technically inevitable drawback in terms of quality assurance which is to be impossible of the burn-in test for screening owing to die- shipment. SEI will not ship them if customers do not agree on this point. On the other hand, the lot assurance test is performed completely without any problems according to SEI’s au- thorized rules. A microscope inspection is conducted in conformance with the MIL-STD- 883C Method 2010.7. Precautions Owing to their small dimensions, the GaAs FET’s from which the F0321818B is designed are easily damaged or destroyed if subjected to large transient voltages. Such transients can be generated by power supplies when switched on if not properly decoupled. It is also possible to induce spikes from static-electricity-charged operations or ungrounded equip- ment. Electron Device Department