EPA018BV EXCELICS | Alldatasheet

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Technical content

High Efficiency Heterojunction Power FET

  • • VERY HIGH fmax: 120GHz
  • • +20.0dBm TYPICAL OUTPUT POWER
  • • 13.0dB TYPICAL POWER GAIN AT 18 GHz
  • • TYPICAL 0.75dB NOISE FIGURE AND 12.5dB ASSOCIATED GAIN AT 12GHz
  • • 0.3 X 180 MICRON RECESSED “MUSHROOM” GATE
  • • Si 3 N 4 PASSIVATION AND VIA HOLE GROUNDING
  • • ADVANCED EPITAXIAL HETEROJUNCTION PROFILE PROVIDES EXTRA HIGH POWER EFFICIENCY, AND HIGH RELIABI LITY
  • • Idss SORTED IN 5 mA PER BIN RANGE ELECTRICAL CHARACTERISTICS (T a = 25 O C) SYMBOLS PARAMETERS/TEST CONDITIONS MIN TYP MAX UNIT P 1dB Output Power at 1dB Compression f=12GHz Vds=6V, Ids=50% Idss f=18GHz 18.0 20.0* 20.0* dBm G 1dB Gain at 1dB Compres sion f=12GHz Vds=6V, Ids=50% Idss f=18GHz 13.0 14.5 13.0 dB PAE Power Added Efficiency at 1dB Compression Vds=6V, Ids=50% Idss f=12Ghz NF Noise Figure f=12GHz Vds=2V, Ids=15mA 0.75 dB Ga Associated Gain f=12GHz Vds=2V, Ids=15mA 12.5 dB Idss Saturated Drain Current Vds=3V, Vgs=0V 30 55 80 mA Gm Transconductance Vds=3V, Vgs=0V 35 60 mS Vp Pinch - off Voltage Vds=3V, Ids=1.0mA - 1.0 - 2.5 V BVgd Drain Breakdown Voltage Igd=0.5mA - 9 - 15 V BVgs So urce Breakdown Voltage Igs=0.5mA - 7 - 14 V Rth Thermal Resistance (Au - Sn Eutectic Attach) 140 o C/W * P 1dB = 21.5dBm can be obtained with 8v/50% Idss bias. Consult factory for wafer selection. MAXIMUM RATINGS AT 25 O C SYMBOLS PARAMETERS ABSOLUTE 1 CONTI NUOUS 2 Vds Drain - Source Voltage 12V 6V Vgs Gate - Source Voltage - 8V - 3V Ids Drain Current Idss Idss Igsf Forward Gate Current 9mA 1.5mA Pin Input Power 16dBm @3dB Compression Tch Channel Temperature 175 o C 150 o C Tstg Storage Temperature - 65/175 o C - 65/ 150 o C Pt Total Power Dissipation 950mW 800mW Note: 1. Exceeding any of the above ratings may result in permanent damage. 2. Exceeding any of the above ratings may reduce MTTF below design goals. Excelics Semiconductor, Inc., 2908 Scott Blvd. , Santa Clara, CA 95054 Phone: (408) 970 - 8664 Fax: (408) 970 - 8998 Web Site: www.excelics.com : Via Hole Chip Thickness: 75 ± 13 microns All Dimensions In Microns

High Efficiency Heterojunction Power FET S - PARAMETERS S - PARAMETERS 2V, 15mA 6V, 1/2 Idss (G Hz) MAG ANG MAG ANG MAG ANG MAG ANG (GHz) MAG ANG MAG ANG MAG ANG MAG ANG Note: The data included 0.7 mils diameter Au bonding wires: 1 gate wire, 15 mils each; 1 drain wire, 20 mils each.