82C50A_06 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Single Chip UART/BRG
- DC to 625K Baud (DC to 10MHz Clock)
- Crystal or External Clock Input
- On Chip Baud Rate Generator 1 to 65535 Divisor Generates 16X Clock
- Prioritized Interrupt Mode
- Fully TTL/CMOS Compatible
- Microprocessor Bus Oriented Interface
- 80C86/80C88 Compatible
- Scaled SAJI IV CMOS Process
- Low Power - 1mA/MHz Typical
- Modem Interface
- Line Break Generation and Detection
- Loopback and Echo Modes
- Doubled Buffered Transmitter and Receiver
- Single 5V Supply
- Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
(°C) PACKAGE PKG. DWG. # CP82C50A-5 CP82C50A-5 0 to +70 40 Ld PDIP E40.6 CP82C50A-5Z (Note) CP82C50A-5Z 0 to +70 40 Ld PDIP (Pb-free) E40.6 CS82C50A-596 CS82C50A-5 0 to +70 44 Ld PLCC Tape and Reel N44.65 CS82C50A-5Z (Note) CS82C50A-5Z 0 to +70 44 Ld PLCC (Pb-free) N44.65 CS82C50A-5Z96 (Note) CS82C50A-5Z 0 to +70 44 Ld PLCC Tape and Reel (Pb-free) N44.65 IS82C50A-5 IS82C50A-5 -40 to +85 44 Ld PLCC N44.65 IS82C50A-5Z (Note) IS82C50A-5Z -40 to +85 44 Ld PLCC (Pb-free) N44.65 NOTE: Intersil Pb-free plus anneal pr oducts employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN2958.5 82C50A Data Sheet August 24, 2006
2 FN2958.5 August 24, 2006 82C50A Functional Diagram MR DISTR DISTR DOSTR DOSTR CSO CS1 CS2 ADS 25 MICROPROCESSOR INTERFACE INTERRUPT ENABLE, ID, & CONTROL
30 INTRPT
23 DDIS
24 CSOUT
10 SIN
9 RCLK
16 XTAL1
15 BAUDOUT
17 XTAL2
11 SOUT
32 RTS
33 DTR
34 OUT1
31 OUT2
36 CTS
37 DSR
38 DCD
3 FN2958.5 August 24, 2006 82C50A Pinout 82C50A (PDIP) TOP VIEW 82C50A (PLCC) TOP VIEW RCLK SIN SOUT CS0 CS1 CS2 BAUDOUT XTAL1 XTAL2 DOSTR DOSTR GND V CC RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT NC ADS CSOUT DDIS DISTR DISTR 44 43 42 41 40 2827 123456 20 21 22 23 24 25 261918 RCLK SIN NC SOUT CS0 CS1 CS2 BAUDOUT NC VCC RI DCD DSR CTS XTAL1 XTAL2 DOSTR DOSTR GND NC DISTR DISTR DDIS CSOUT ADS MR OUT1 DTR RTS OUT2 NC INTRP NC
4 FN2958.5 August 24, 2006 82C50A Pin Description SYMBOL PIN NUMBER TYPE ACTIVE LEVEL DESCRIPTION DISTR, DISTR I I H L DATA IN STROBE, DATA IN STROBE: DISTR, DISTR are read inputs which cause the 82C50A to output data to the data bus (D0-D7). The data output depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DISTR, DISTR inputs. Only an active DISTR or DISTR, not both, is used to receive data from the 82C50A during a read operation. If DISTR is used as the read input, DlSTR should be tied high. If DISTR is used as the active read input, DISTR should be tied low. DOSTR, DOSTR I I H L DATA OUT STROBE, DATA OUT STROBE: DOSTR, DOSTR are write inputs which cause data from the data bus (D0-D7) to be input to the 82C50A. The data input depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DOSTR, DOSTR inputs. Only an active DOSTR or DOSTR, not both, is used to transmit data to the 82C50A during a write operation. If DOSTR is used as the write input, DOSTR should be tied high. If DOSTR is used as the write input, DOSTR should be tied low. D0-D7 1-8 I/O DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of data, control and status information between the 82C50A and the CPU. For character formats of less than 8 bits, D7, D6 and D5 are “don’t cares” for data write operations and 0 for data read operations. These lines are normally in a high impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the first serial data bit to be received or transmitted. A0, A1, 28, 27, I I H REGISTER SELECT: The address lines select the internal registers during CPU bus operations. See Table 1. XTAL1, XTAL2 I O CRYSTAL/CLOCK: Crystal connections for t he internal Baud Rate Generator. XTAL1 can also be used as an external clock input, in which case XTAL2 should be left open. SOUT 11 O SERIAL DATA OUTPUT: Serial data output from the 82C50A transmitter circuitry. A Mark (1) is a logic one (high) and Space (0) is a logic zero (low). SOUT is held in the Mark condition when the transmitter is disabled, MR is true, the Transmitter Register is empty, or when in the Loop Mode. SOUT is not affected by the CTS input. GND 20 L GROUND: Power supply ground connection (V SS). CTS 36 I L CLEAR TO SEND: The logical state of the CTS pin is reflected in the CTS bit of the (MSR) Modem Status Register (CTS is bit 4 of the MSR, written MSR (4)). A change of state in the CTS pin since the previous reading of the MSR causes the setting of DCTS (MSR(O)) of the Modem Status Register. When CTS pin is ACTIVE (low), the modem is indicating that data on SOUT can be transmitted on the communications link. If CTS pin goes INACTIVE (high), the 82C50A should not be allowed to transmit data out of SOUT. CTS pin does not affect Loop Mode operation. DSR 37 I L DATA SET READY: The logical state of the DSR pin is reflected in MSR(5) of the Modem Status Register. DDSR (MSR(1)) indicates whether the DSR pin has changed state since the previous reading of the MSR. When the DSR pin is ACTIVE (low), the modem is indicating that it is ready to exchange data with the 82C50A, while the DSR Pin INACTIVE (high) indicates that the modem is not ready for data exchange. The ACTIVE condition indicates only the condition of the local Data Communications Equipment (DCE), and does not imply that a data circuit as been established with remote equipment. DTR 33 O L DATA TERMINAL READY: The DTR pin can be set (low) by writing a logic 1 to MCR(0), Modem Control Register bit 0. This signal is cleared (high) by writing a logic 0 to the DTR bit (MCR(0)) or whenever a MR ACTIVE (high) is applied to the 82C50A. When ACTIVE (low), DTR pin indicates to the DCE that the 82C50A is ready to receive data. In some instances, DTR pin is used as a power on indicator. The INACTIVE (high) state causes the DCE to disconnect the modem from the telecommunications circuit. RTS 32 O L REQUEST TO SEND: The RTS signal is an output used to enable the modem. The RTS pin is set low by writing a logic 1 to MCR (1) bit 1 of the Modem Control Register. The RTS pin is reset high by Master Reset. When ACTIVE, the RTS pin indicates to the DCE that the 82C50A has data ready to transmit. In half duplex operations, RTS is used to control the direction of the line. BAUDOUT 15 O BAUDOUT: This output is a 16X clock out used for the transmitter section (16X = 16 times the data rate). The BAUDOUT clock rate is equal to the reference oscillator frequency divided by the specified divisor in the Baud Rate Generator Divisor Latches DLL and DLM. BAUDOUT may be used by the Receiver section by tying this output to RCLK.
5 FN2958.5 August 24, 2006 82C50A OUT1 34 O L OUTPUT 1: This is a general purpose out put that can be programmed ACTIVE (low) by settingVCR(2) (OUT1) of the Modem Control Register to a high level. The OUT1 pin is set high by Master Reset. The OUT1 pin is INACTIVE (high) during loop mode operation. OUT2 31 O L OUTPUT 2: This is a general purpose out put that can be programmed ACTIVE (low) by setting MCR(3) (OUT1) of the Modem Control Register to a high level. The OUT2 pin is set high by Master Reset. The OUT2 signal is INACTIVE (high) during loop mode operation. RI 39 1 L RING INDICATOR: When low, RI indicates that a telephone ringing signal has been received by the modem or data set. The RI signal is a modem control input whose condition is tested by reading MSR(6) (RI). The Modem Status Register output TERI (MSR(2)) indicates whether the RI input has changed from a Low to High since the previous reading of the MSR. If the interrupt is enabled (IER (3) = 1) and RI changes from a Low to High, an interrupt is generated. The ACTIVE (low) state of RI indicates that the DCE is receiving a ringing signal. RI will appear ACTIVE for approximately the same length of time as the ACTIVE segment of the ringing cycle. The INACTIVE state of RI will occur during the INACTIVE segments not detected by the DCE. This circuit is not disabled by the INACTIVE condition of DTR. DCD 38 I L DATA CARRIER DETECT: When ACTIVE (low), DCD indicates that the data carrier has been detected by the modem or data set. DCD is a modem input whose condition can be tested by the CPU by reading MSR(7) (DCD) of the Modem Status Register. MSR(3) (DDCD) of the Modem Status Register indicates whether the DCD input has changed since the previous reading of the MSR. DOD has no effect on the receiver. If the DCD changes state with the modem status interrupt enabled, an interrupt is generated. When DCD is ACTIVE (low), the received line signal from the remote terminal is within the limits specified by the DCE manufacturer. The INACTIVE (high) signal indicates that the signal is not within the specified limits, or is not present. MR 35 1 H MASTER RESET: The MR input forces the 82C50A into an idle mode in which all serial data activities are suspended. The Modem Control Register (MCR) along with its associated outputs are cleared. The Line Status Register (LSR) is cleared except for the THRE and TEMT bits, which are set. The 82C50A remains in an idle state until programmed to resume serial data activities. The MR input is a Schmitt trigger input. See the DC Electrical Characteristics for Schmitt trigger logic input voltage levels. See Table 7 for a summary of Master Reset’s effect on 82C50A operation. lNTRPT 30 O H INTERRUPT REQUEST: The lNTRPT output goes ACTIVE (high) when one of the following interrupts has an ACTIVE (high) condition and is enabled by the Interrupt Enable Register: Receiver Error flag, Received Data Available, Transmitter Holding Register Empty, and Modem Status. The lNTRPT is reset low upon appropriate service or a MR operation. See Figure 1. Interrupt Control Structure. SIN 10 I H SERIAL DATA INPUT: The SIN input is the serial data input from the communication line or modem to the 82C50A receiver circuits. A mark (1) is high, and a space (0) is low. Data inputs on SIN are disabled when operating in the loop mode. V CC 40 H V CC: +5V positive power supply pin. A 0.1 μA decoupling capacitor from VCC (pin 40) to GND (pin 20) is recommended. CS0, CS1, CS2 12,13, I I H, H, L CHIP SELECT: The Chip Select inputs act as enable signals for the write (DOSTR, DOSTR) and read (DlSTR, DlSTR) input signals. The Chip Select inputs are latched by the ADS input. NC 29 Do Not Connect CSOUT 24 O H CHIP SELECT OUT: When ACTIVE (high), this pin indicates that the chip has been selected by active CS0, CS1, and CS2 inputs. No data transfer can be initiated until CSOUT is a logic 1, ACTIVE (high). DDIS 23 O H DRIVER DISABLE: This output is INACTIVE (low) when the CPU is reading data from the 82C50A. An ACTIVE (high) Dells output can be used to disable an external transceiver when the CPU is reading data. ADS 25 I L ADDRESS STROBE: When ACTIVE (low), ADS latches the Register Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) inputs. An active ADS is required when the Register Select pins are not stable for the duration of the read or write operation, multiplexed mode. If not required, the ADS input should be tied low, non-multiplexed mode. RCLK 9 I This input is the 16X Baud Rate Clock for the receiver section of the 82C50A. This input may be provided from the BAUDOUT output or an external clock. Pin Description (Continued) SYMBOL PIN NUMBER TYPE ACTIVE LEVEL DESCRIPTION
6 FN2958.5 August 24, 2006 82C50A Block Diagram DISTR DISTR DOSTR DOSTR DDIS CSOUT XTAL1 XTAL2 (22) (21) (19) (18) (23) (24) (16) (17) CS0 CS1 CS2 ADS MR (28) (27) (26) (12) (13) (14) (25) (35) D7 - D0 (1 - 8) (40) (20) DATA BUS RECEIVER SHIFT BUFFER POWER SUPPLY SELECT CONTROL LOGIC (10) SIN (9) RCLK (15) BAUDOUT (11) SOUT (32) RTS (33) DTR (34) OUT1 (36) OUT2 (31) CTS (37) DSR (38) DCD (39) RI RECEIVER RECEIVER TIMING & CONTROL TRANSMITTER TIMING & CONTROL TRANSMITTER SHIFT REGISTER MODEM CONTROL LOGIC RECEIVER BUFFER REGISTER LINE CONTROL REGISTER BAUD RATE GENERATOR DIVISOR LATCH (LS) DIVISOR LATCH (MS) LINE STATUS REGISTER TRANSMITTER HOLDING REGISTER MODEM CONTROL REGISTER MODEM STATUS REGISTER INTERRUPT ENABLE REGISTER INTERRUPT IO REGISTER SCRATCH REGISTER INTERRUPT CONTROL LOGIC (30) INTRPT +5V GND
by the register mnemonic and the bit number in parenthesis. An example, LCR(7) refers to Line Control Register Bit 7. TABLE 1. ACCESSING 82C50A INTERNAL REGISTERS Register or the Interrupt Enable Register. Baud Rate Generator During a Read or Write Operation.
8 FN2958.5 August 24, 2006 82C50A LINE CONTROL REGISTER (LCR) The format of the data character is controlled by the Line Control Register. The contents of the LCR may be read, eliminating the need for separate storage of the line characteristics in system memory. The contents of the LCR are described below. LCR BITS 0 THRU 7 LCR (0) Word Length Select Bit 0 (WLS0) LCR (1) Word Length Select Bit 1 (WLS1) LCR (2) Stop Bit Select (STB) LCR (3) Parity Enable (PEN) LCR (4) Even Parity Select (EPS) LCR (5) Stick Parity LCR (6) Set Break LCR (7) Divisor Latch Access Bit (DLAB) LCR(0) and LCR(1) Word Length Select Bit 0, Word Length Select Bit 1: The number of bits in each transmitted or received serial character is programmed as follows: LCR(2) Stop Bit Select: LCR(2) specifies the number of stop bits in each transmitted character. If LCR(2) is a logic 0, one stop bit is generated in the transmitted data. If LCR(2) is a logic 1 when a 5-bit word length is selected, 1.5 stop bits are generated. If LCR(2) is a logic 1 when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated. The receiver checks for two stop bits if programmed. LCR(3) Parity Enable: When LCR(3) is high, a parity bit between the last data word bit and stop bit is generated and checked. LCR(4) Even Parity Select: When parity is enabled (LCR(3) = 1), LCR(4) = 0 selects odd parity, and LCR(4) = 1 selects even parity. LCR(5) Stick Parity: When parity is enabled (LCR(3) = 1), LCR(5) = 1 causes the transmission and reception of a parity bit to be in the opposite state from that indicated by LCR(4). This allows the user to force parity to a known state and for the receiver to check the parity bit in a known state. LCR(6) Break Control: When LCR(6) is set to logic-1, the serial output (SOUT) is forced to the spacing (logic 0) state. The break is disabled by setting LCR(6) to a logic-0. The Break Control bit acts only on SOUT and has no effect on the transmitter logic. Break Control enables the CPU to alert a terminal in a computer communications system. If the following sequence is used, no erroneous or extraneous characters will be transmitted because of the break. 1. Load an all Os pad character in response to THRE. 2. Set break in response to the next THRE. 3. Wait for the transmitter to be idle, (TEMT = 1), and clear break when normal transmission has to be restored. During the break, the transmitter can be used as a character timer to accurately establish the break duration. LCR(7) Divisor Latch Access Bit (DLAB): LCR(7) must be set high (logic 1) to access the Divisor Latches DLL and DLM of the Baud Rate Generator during a read or write operation. LCR(7) must be input low to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register. LINE STATUS REGISTER (LSR) The LSR is a single register that provides status indications. The LSR is usually the first register read by the CPU to determine the cause of an interrupt or to poll the status of the 82C50A. Three error flags OE, FE, and PE provide the status of any error conditions detected in the receiver circuitry. During reception of the stop bits, the error flags are set high by an error condition. The error flags are not reset by the absence of an error condition in the next received character. The flags reflect the last character only if no overrun occurred. The Overrun Error (OE) indicates that a character in the Receiver Buffer Register has been overwritten by a character from the Receiver Shift Register before being read by the CPU. The character is lost. Framing Error (FE) indicates that the last character received contained incorrect (low) stop bits. This is caused by the absence of the required stop bit or by a stop bit too short to be detected. Parity Error (PE) indicates that the last character received contained a parity error based on the programmed and calculated parity of the received character. The Break Interrupt (BI) status bit indicates that the last character received was a break character. A break character is an invalid data character, with the entire character, including parity and stop bits, logic zero. The Transmitter Holding Register Empty (THRE) bit indicates that the THR register is empty and ready to receive another character. The Transmission Shift Register Empty (TEMT) bit indicates that the Transmitter Shift Register is empty, and the 82C50A has completed transmission of the last character. If the interrupt is enabled (lER(1)), an active THRE causes an interrupt (INTRPT). The Data Ready (DR) bit indicates that the RBR has been loaded with a received character (including Break) and that the CPU may access this data. Reading the LSR clears LSR (1) - LSR (4). (OE, PE, FE and BI). LCR(1) LCR(0) WORD LENGTH 00 5 B i t s 01 6 B i t s 10 7 B i t s 11 8 B i t s
9 FN2958.5 August 24, 2006 82C50A The contents of the Line Status Register are indicated in the above table and are described below. LSR(0) Data Ready (DR): Data Ready is set high when an incoming character has been received and transferred into the Receiver Buffer Register. LSR(0) is reset low by a CPU read of the data in the Receiver Buffer Register. LSR(1) Overrun Error (OE): Overrun Error indicates that data in the Receiver Buffer Register was not read by the CPU before the next character was transferred into the Receiver Buffer Register, overwriting the previous character. The OE indicator is reset whenever the CPU reads the contents of the Line Status Register. LSR(2) Parity Error (PE): Parity Error indicates that the received data character does not have the correct even or odd parity, as selected by the Even Parity Select bit (LCR (4)). The PE bit is set high upon detection of a parity error, and is reset low when the CPU reads the contents of the LSR. LSR(3) Framing Error (FE): Framing Error indicates that the received character did not have a valid stop bit. LSR(3) is set high when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). The FE indicator is reset low when the CPU reads the contents of the LSR. LSR(4) Break Interrupt (BI): Break Interrupt is set high when the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). The B indicator is reset when the CPU reads the contents of the Line Status Register. LSR(1) - LSR(4) are the error conditions that produce a Receiver Line Status interrupt (priority 1 interrupt in the Interrupt Identification Register (IIR)) when any of the conditions are detected. This interrupt is enabled by setting lER (2) = 1 in the Interrupt Enable Register. LSR(5) Transmitter Holding Register Empty (THRE): THRE indicates that the 82C50A is ready to accept a new character for transmission. The THRE bit is set high when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. LSR(5) is reset low by the loading of the Transmitter Holding Register by the CPU. LSR(5) is not reset by a CPU read of the LSR. When the THRE interrupt is enabled (IER(1) = 1), THRE causes a priority 3 interrupt in the lIR. If THRE is the interrupt source indicated in IIR, lNTRPT is cleared by a read of the IIR. LSR(6) Transmitter Empty (TEMT): TEMT is set high when the Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR) are both empty. LSR(6) is reset low when a character is loaded into the THR and remains low until the character is transferred out of SOUT. TEMT is not reset low by a CPU read of the LSR. LSR(7): This bit is permanently set to logic 0. MODEM CONTROL REGISTER (MCR) The MCR controls the interface with the modem or data set as described below. The MCR can be written and read. The RTS , DTR, OUT1 and OUT2 outputs are directly controlled by their control bits in this register. A high input asserts a low (true) at the output pins. MCR(0): When MCR(0) is set high, the DTR output is forced low. When MCR(0) is reset low, the DTR output is forced high. The DTR output of the 82C50A may be input into an ElA inverting line driver as the 1488 to obtain the proper polarity input at the modem or data set. MCR(1): When MCR(1) is set high, the RTS output is forced low. When MCR(1) is reset low, the RTS output is forced high. The RTS output of the 82C50A may be input into an ElA inverting line driver as the 1488 to obtain the proper polarity input at the modem or data set. MCR(2): When MCR(2) is set high, the OUT1 output is forced low. When MCR(2) is reset low, the OUT1 output is forced high. OUT1 is an user designated output. LSR BITS 0 THRU 7 LOGIC 1 LOGIC 0 LSR (0) Data Ready (DR) Ready Not Ready LSR (1) Overrun Error (OE) Error No Error LSR (2) Parity Error (PE) Error No Error LSR (3) Framing Error (FE) Error No Error LSR (4) Break Interrupt (BI) Break No Break LSR (5) Transmitter Holding Register Empty (THRE) Empty Not Empty LSR (6) Transmitter Empty (TEMT) Empty Not Empty LSR (7) Not Used MCR BITS 0 THRU 7 MCR BIT LOGIC 1 MCR BIT LOGIC 0 MCR (0) Data Terminal Ready (DTR) DTR Output Low DTR Output High MCR (1) Request to Send (RTS) RTS Output Low RTS Output High MCR (2) OUT1 OUT1 Output Low OUT1 Output High MCR (3) OUT2 OUT2 Output Low OUT2 Output High MCR (4) LOOP LOOP Enabled LOOP Disabled MCR (5) 0 MCR (6) 0 MCR (7) 0
10 FN2958.5 August 24, 2006 82C50A MCR(3): When MCR(3) is set high, the OUT2 output is forced low. When MCR(3) is reset low, the OUT2 output is forced high. OUT2 is an user designated output. MCR(4): MCR(4) provides a local loopback feature for diagnostic testing of the 62C50A. When MCR(4) is set high, Serial Output (SOUT) is set to the marking (logic 1) state, and the receiver data input Serial Input (SIN) is disconnected. The output of the Transmitter Shift Register is looped back into the Receiver Shift Register input. The four modem control inputs (CTS , DSR, DC, and RI) are disconnected. The four modem control outputs (DTR, RTS, OUT1 and OUT2) are internally connected to the four modem control inputs. The modem control output pins are forced to their inactive state (high). In the diagnostic mode, data transmitted is immediately received. This allows the processor to verify the transmit and receive data paths of the 82C50A. In the diagnostic mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the interrupt sources are now the lower four bits of the MCR instead of the four modem control inputs. The interrupts are still controlled by the Interrupt Enable Register. MCR(5) - MCR(7): These bits are permanently set to logic 0. MODEM STATUS REGISTER (MSR) The MSR provides the CPU with status of the modem input lines from the modem or peripheral device. The MSR allows the CPU to read the modem signal inputs by accessing the data bus interface of the 82C50A. In addition to the current status information, four bits of the MSR indicate whether the modem inputs have changed since the last reading of the MSR. The delta status bits are set high when a control input from the modem changes state, and reset low when the CPU reads the MSR. The modem input lines are CTS (pin 36), DSR (pin 37), RI (pin 39), and DCD (pin 38). MSR(4) - MSR(7) are status indications of these lines. The status indications follow the status of the input lines. If the modem status interrupt in the Interrupt Enable Register is enabled (IER(3)), a change of state in a modem input signals will be reflected by the modem status bits in the lIR register, and an interrupt (lNTRPT) is generated. The MSR is a priority 4 interrupt. The contents of the Modem Status Register are described below: Note that the state (high or low) of the status bits are inverted versions of the actual input pins. MSR(0) Delta Clear to Send (DCTS): DCTS indicates that the CTS input (Pin-36) to the 82C50A has changed state since the last time it was read by the CPU. MSR(1) Delta Data Set Ready (DDSR): DDSR indicates that the DSR input (Pin-37) to the 62C50A has changed state since the last time it was read by the CPU. MSR(2) Trailing Edge of Ring Indicator (TERI): TERI indicates that the RI input (Pin-39) to the 82C50A has Changed state from Low to High since the last time it was read by the CPU. High to Low transitions on RI do not activate TERI. MODEM CONTROL REGISTER (MCR) MCR MCR MCR MCR MCR MCR MCR MCR Data Terminal Ready 0 = DTR Output High (Inactive) 1 = DTR Output Low (Active) Request to Send 0 = RTS Output High (Inactive) 1 = RTS Output Low (Active) Out 1 0 = OUT 1 Output High (Inactive) 1 = OUT 1 Output Low (Active) Out 2 0 = OUT 2 Output High (Inactive) 1 = OUT 2 Output Low (Active) Loop 0 = Loop Disabled 1 = Loop Enabled These Bits are Permanently Set to a Logic 0. MSR BITS 0 THRU 7 MSR BIT MNEMONIC DESCRIPTION MSR (1) DDSR Delta Data Set Ready MSR (2) TERI Trailing Edge of Ring Indicator MSR (0) DCTS Delta Clear To Send MSR (3) DDCD Delta Data Carrier Detect MSR (4) CTS Clear To Send MSR (5) DSR Data Set Ready MSR (6) RI Ring Indicator MSR (7) DCD Data Carrier Detect
11 FN2958.5 August 24, 2006 82C50A MSR(3) Delta Data Carrier Detect (DDCD): DDCD indicates that the DCD input (Pin-36) to the 82C50A has changed state since the last time it was read by the CPU. MSR(4) Clear to Send (CTS): Clear to Send (CTS) is the status of the CTS input (Pin-36) from the modem indicating to the 82C50A that the modem is ready to receive data from the 62C50A transmitter output (SOUT). If the 82C50A is in the loop mode (MCR(4)=1), MSR(4) is equivalent to RTS in the MCR. MSR(5) Data Set Ready (DSR): Data Set Ready (DSR) is a status of the DSR input (Pin-37) from the modem to the 82C50A which indicates that the modem is ready to provide received data to the 82C50A receiver circuitry. If the 82C50A is in the loop mode (MCR(4) = 1), MSR(5) is equivalent to DTR in the MCR. MSR(6) Ring Indicator MSR(6): Indicates the status of the RI input (Pin-39). If the 82C50A is in the loop mode (MCR(4) = 1), MSR(6) is equivalent to OUT1 in the MCR. MSR(7) Data Carrier Detect (MSR(7)): Data Carrier Detect indicates the status of the Data Carrier Detect (DCD) input (Pin-38). If the 82C50A is in the loop mode (MCR(4) = 1), MSR(4) is equivalent to OUT2 of the MCR. The modem status inputs (RI, DCD, DSR and CTS) reflect the modem input lines with any change of status. Reading the MSR register will clear the delta modem status indications but has no effect on the status bits. The status bits reflect the state of the input pins regardless of the mask control signals. If a DCTS, DDSR, TERI, or DDCD are true and a state change occurs during a read operation (DlSTR, DISTR ), the state change is not indicated in the MSR. If DCTS, DDSR, TERI, or DDCD are false and a state change occurs during a read operation, the state change is indicated after the read operation. For LSR and MSR, the setting of status bits is inhibited during status register read (DISTR, DlSTR ) operations. If a status condition is generated during a read (DlSTR, DISTR) operation, the status bit is not set until the trailing edge of the read (DISTR, DISTR). If a status bit is set during a read (DlSTR, DISTR) operation, and the same status condition occurs, that status bit will be cleared at the trailing edge of the read (DlSTR, DISTR instead of being set again. BAUD RATE SELECT REGISTER (BRSR) The 82C50A contains a programmable Baud Rate Generator (BRG) that divides the clock (DC to 10MHz) by any divisor from 1 to 2 16-1 (see also BRG description). The output frequency of the Baud Generator is 16X the data rate [divisor # = frequency input ÷ (baud rate x 16)]. Two 8-bit divisor latch registers store the divisor in a 16-bit binary format. These Divisor Latch registers must be loaded during initialization. Upon loading either of the Divisor Latches, a 16-bit Baud counter is immediately loaded. This prevents long counts on initial load. Sample Divisor Number Calculation: Given: Desired Baud Rate 1200 Baud Frequency Input 1.8432MHz Formula: Divisor # = Frequency Input ÷ (Baud Rate x 16) Divisor # = 1843200 ÷ (1200 x 16) Answer: Divisor # = 96 = 60 HEX → DLL = 01100000 DLM = 00000000 Check: The Divisor # 96 will divide the input frequency 1.8432MHz down to 19200 which is 16 times the desired baud rate. RECEIVER BUFFER REGISTER (RBR) The receiver circuitry in the 82C50A is programmable for 5, 6, 7 or 8 data bits per character. For words of less than 8 bits, the data is right justified to the least significant bit (LSB = Data Bit 0 (RBR(0)). Data Bit 0 of a data word (RBR(0)) is the first data bit received. The unused bits in a character less than 8 bits are output low to the parallel output by the 82C50A. Received data at the SIN input pin is shifted into the Receiver Shift Register by the 16X clock provided at the RCLK input. This clock is synchronized to the incoming data based on the position of the start bit. When a complete character is shifted into the Receiver Shift Register, the assembled data bits are parallel loaded into the Receiver Buffer Register. The DR flag in the LSR register is set. Double buffering of the received data permits continuous reception of data without losing received data. While the Receiver Shift Register is shifting a new character into the 82C50A, the Receiver Buffer Register is holding a previously received character for the CPU to read. Failure to read the Divisor Latch Least Significant BYTE DLL (0) Bit 0 DLL (1) Bit 1 DLL (2) Bit 2 DLL (3) Bit 3 DLL (4) Bit 4 DLL (5) Bit 5 DLL (6) Bit 6 DLL (7) Bit 7 Divisor Latch Most Significant BYTE DLM (0) Bit 8 DLM (1) Bit 9 DLM (2) Bit 10 DLM (3) Bit 11 DLM (4) Bit 12 DLM (5) Bit 13 DLM (6) Bit 14 DLM (7) Bit 15
are ignored by the transmitter. flag (LSR(6)) indicates if both the THR and TSR are empty. This 8-bit Read/Write register has no effect on the 82C50A. programmer to hold data temporarily.
- Receiver Line Status (Priority 1)
- Received Data Ready (Priority 2)
- Transmitter Holding Register Empty (Priority 3)
- Modem Status (Priority 4).
indicated in Table 2 and are described below. highest priority interrupt pending as indicated in Table 2. lIR(3) - IIR(7): These five bits of the lIR are logic 0. TABLE 2. INTERRUPT IDENTIFICATION REGISTER
enables Received Data Available interrupt. enables the Transmitter Holding Register Empty interrupt. enables the Receiver Line Status interrupt. enables the Modem Status interrupt. IER(4) - IER(7): These four bits of the IER are logic 0. FIGURE 1. 82C50A INTERRUPT CONTROL STRUCTURE TABLE 3. 82C50A ACCESSIBLE REGISTER SUMMARY †LSB, Data Bit 0 is the first bit transmitted or received.
the transmission of the start bit. When the transmitter is idle, both THRE and TEMT are high. high one THR to TSR transfer time later. character due to a low going noise spike on the SIN input. odd parity on the parity bit, which precedes the first stop bit. If there is a parity error, the parity error is set in LSR (2). is not, a framing error indication is generated in LSR(3). as much as one 16X clock cycle prior to being detected. into the XTAL1 of the second 82C50A. providing an output 16X the data rate. frequency are less expensive than lower frequency crystals. standard rates using these three crystal frequencies. TABLE 4. BAUD RATES USING 1.8432MHz CRYSTAL
- Initializes the transmitter and receiver internal clock
- Clears the Line Status Register (LSR), except for
Transmitter Buffer Register are not effected. 82C50A remains in the idle mode until programmed. enabled, an interrupt occurs due to THRE. TABLE 5. BAUD RATES USING 2.4576MHz CRYSTAL TABLE 6. BAUD RATES USING 3.072MHz CRYSTAL TABLE 7. 82C50A RESET OPERATIONS
transmitting or receiving data. configuration, respectively. sinusoidal nature of the drive circuitry when using a crystal. external clock or a crystal attached to XTAL1 and XTAL2. maximum data rate is 625Kbps. TABLE 8. TYPICAL CRYSTAL OSCILLATOR CIRCUIT FIGURE 2. TYPICAL CRYSTAL OSCILLATOR CIRCUIT
17 FN2958.5 August 24, 2006 82C50A Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) Maximum Junction Temperature (Lead Tips Only for Surface Mount Packages) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 - V VIL Logical Zero Input Voltage - 0.8 V VTH Schmitt Trigger Logic One Input Voltage 2.0 - V MR Input VTL Schmitt Trigger Logic Zero Input Voltage - 0.8 V MR Input VIH (CLK) Logical One Clock Voltage V CC-0.8 - V External Clock VlL (CLK) Logical Zero Clock Voltage - 0.8 V External Clock VOH Output High Voltage 3.0 - V I OH = -2.5mA VCC-0.4 - V I OH = -100μA VOL Output Low Voltage - 0.4 V l OL = +2.5mA, II Input Leakage Current -1.0 +1.0 μAV IN = GND or VCC, DIP Pins 9,10,12, 13, 14, 18, 19, 21, 22, 25-28, 35-39 IO Input/Output Leakage Current -10.0 +10.0 μAV O = GND or VCC, DIP Pins 1-8 ICCOP Operating Power Supply Current - 6 mA External Clock F = 2.4576MHz, VCC = 5.5V, VIN = VCC or GND, Outputs Open ICCSB Standby Supply Current - 100 μAV CC = 5.5V, VIN = VCC or GND, Outputs Open Capacitance TA = 25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 15 pF FREQ = 1MHz, all measurements are referenced to device GNDCOUT Output Capacitance 15 pF CI/O I/O Capacitance 20 pF
18 FN2958.5 August 24, 2006 82C50A Timing Requirements SYMBOL PARAMETER 82C50A-5 TEST CONDITIONSMIN MAX UNITS (1) TAW Address Strobe Width 50 - ns (2) TAS Address Setup Time 60 - ns Note 1 (3) TAH Address Hold Time 0 - ns (4) TCS Chip Select Setup Time 60 - ns Note 1 (5) TCH Chip Select Hold Time 0 - ns (6) TDIW DISTR DlSTR Strobe Width 150 - ns (7) TRC Read Cycle Delay 270 - ns Note 1 (8) RC Read Cycle = TAR + TDIW + TRC 500 - ns (9) TDD DISTR DlSTR to Driver Disable Delay - 75 ns (10) TDDD Delay From DISTR DlSTR to Data - 120 ns (11) THZ DlSTR DISTR to Floating Data Delay 10 75 ns (12) TDOW DOSTR DOSTR Strobe Width 150 - ns (13) TWC Write Cycle Delay 270 - ns Note 1 (14) WC Write Cycle = TAW + TDOW + TWC 500 - ns (15) TDS Data Setup Time 90 - ns (16) TDH Data Hold Time 60 - ns NOTE: 1. “When using the 82C50A in the multiplexed mode (ADS operational), it will operate in 80C86/88 systems with a maximum 3MHz operating frequency.” Timing SYMBOL PARAMETER 82C50A-5 UNITS TEST CONDITIONSMIN MAX DEMULTIPLEXED OPERATION (17) TCSC Chip Select Output Delay from Select - 125 ns (18) TRA Address Hold Time from DISTR DISTR 20 - ns (19) TRCS Chip Select Hold Time from DISTR DISTR 20 - ns (20) TAR DISTR DISTR Delay from Address 80 - ns (21) TCSR DISTR DISTR Delay from Chip Select 80 - ns (22) TWA Address Hold Time from DOSTR DOSTR 20 - ns (23) TWCS Chip Select Hold Time from DOSTR DOSTR 20 - ns (24) TAW DOSTR DOSTR Delay from Address 80 - ns (25) TCSW DOSTR DOSTR Delay from Select 80 - ns (26) TMRW Master Reset Pulse Width 500 - ns (27) TXH Duration of Clock High Pulse 40 - ns (28) TXL Duration of Clock Low Pulse 40 ns
19 FN2958.5 August 24, 2006 82C50A BAUD GENERATOR (29) N Baud Divisor 1 2 16-1 (30) TBLD Baud Output Negative Edge Delay - 250 ns (31) TBHD Baud Output Positive Edge Delay - 250 ns (32) TLW Baud Output Down Time 40 - ns T XL = 50ns (33) THW Baud Output Up Time 40 - ns T XH = 50ns RECEIVER (34) TSCD Delay from RCLK to Sample Time - 250 ns (35) TSlNT Delay from Stop to Set Interrupt 1 1 BAUDOUT Cycles (36) TRlNT Delay from DISTR DISTR (RD RBR) to Reset Interrupt - 250 ns TRANSMITTER (37) THR Delay from DOSTR DOSTR to Reset Interrupt - 250 ns (38) TlRS Delay from Initial INTR Reset to Transmit Start 8 24 BAUDOUT Cycles (39) TS1 Delay from Initial Write to Interrupt 16 32 BAUDOUT Cycles (40) TSTl Delay from Stop to Interrupt (THRE) 8 24 BAUDOUT Cycles (41) TIR Delay from DISTR DISTR (RD lIR) to Reset Interrupt (THRE) - 250 ns MODEM CONTROL (42) TMDO Delay from DOSTR DOSTR to Output - 500 ns (43) TSIM Delay to Set Interrupt from Modem Input - 500 ns (44) TRIM Delay to Reset Interrupt from DISTR DlSTR (RD MSR) - 500 ns Timing (Continued) SYMBOL PARAMETER 82C50A-5 UNITS TEST CONDITIONSMIN MAX
FIGURE 10. MODEM CONTROLS TIMING
24 FN2958.5 August 24, 2006 82C50A Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E40.6 (JEDEC MS-011-AC ISSUE B)
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.980 2.095 50.3 53.2 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N4 0 4 0 9 Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2958.5 August 24, 2006 82C50A Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N44.65 (JEDEC MS-018AC ISSUE A)
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N4 4 4 4 6 Rev. 2 11/97