CS82C37A-12

82C37A_06 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

Features

• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitialization Capability
• Cascadable to any Number of Channels
• High Speed Data Transfers: - Up to 4MBytes/sec with 8MHz Clock - Up to 6.25MBytes/sec with 12.5MHz Clock
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation - ICCSB = 10 µA Maximum - ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
• Pb-Free Plus Anneal Available (RoHS Compliant)

Ordering Information

(°C) PKG. DWG. #5MHz PART MARKING 8MHz PART MARKING 12.5MHz PART MARKING CP82C37A-5 CP82C37A-5 CP82C37A CP82C37A-12 40 Ld PDIP 0 to +70 E40.6 IP82C37A-5 IP82C37A IP82C37A-12 -40 to +85 E40.6 CS82C37A-5 CS82C37A* CS82C37A CS82C37A-1296 CS82C37A-12 44 Ld PLCC 0 to +70 N44.65 CS82C37AZ (Note) CS82C37AZ 44 Ld PLCC (Pb-Free) 0 to +70 N44.65 IS82C37A-5 IS82C37A IS82C37A-12 44 Ld PLCC -40 to +85 N44.65 CD82C37A-5 CD82C37A CD82C37A-12 40 Ld CERDIP 0 to +70 F40.6 ID82C37A-5 ID82C37A ID82C37A-12 -40 to +85 F40.6 MD82C37A-5/B MD82C37A/B MD82C37A/B MD82C37A-12/B -55 to +125 F40.6 5962-9054301MQA 5962- 9054302MQA 5962- 9054303MQA SMD# F40.6 MR82C37A-5/B MR82C37A/B MR82C37A-12/B 44 Pad CLCC -55 to +125 J44.A 5962-9054301MXA 5962-9054302MXA 5962-9054303MXA SMD# J44.A *Add "96" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet FN2967.2 March 20, 2006 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2002, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN2967.2 March 20, 2006 82C37A Block Diagram Pinouts 82C37A (PDIP/CERDIP) TOP VIEW 82C37A (CLCC/PLCC) TOP VIEW IOR IOW MEMR MEMW NC READY HLDA ADSTB AEN HRQ CS CLK RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 (GND) VSS EOP VCC DB0 DB1 DB2 DB3 DB4 DACK0 DACK1 DB5 DB6 DB7 46 3 1 4041424344 2827262524232221201918 CS DACK2 NC NC CLK HRQ NC VCC DB0 DB1 DB2 DB3 NC DB4 READY NC MEMW EOP DACK3 DREQ3 DREQ2 DREQ1 DREQ0 GND DB5 DACK1 DB7 DACK0 DB6 MEMR ADSTB AEN IOW RESET HLDA IOR A4 - A7 EOP RESET CS READY CLK AEN ADSTB MEMR MEMW IOR IOW TIMING AND CONTROL DREQ0 - HLDA HRQ DACK0 - PRIORITY ENCODER AND ROTATING PRIORITY LOGIC DACK3 DREQ3

4 COMMAND

(8) MASK (4) REQUEST (4) MODE (4 x 6) STATUS (8) TEMPORARY (8) INTERNAL DATA BUS DECREMENTOR COUNT REG (16) TEMP WORD INC/DECREMENTOR REG (16) TEMP ADDRESS BUFFER IO 16-BIT BUS READ BUFFER ADDRESS BASE (16) WORD BASE COUNT (16) READ WRITE BUFFER ADDRESS CURRENT (16) WORD CURRENT COUNT (16) 16-BIT BUS BUFFER WRITE BUFFER READ A8 - A15 BUFFER OUTPUT CONTROL COMMAND D0 - D1 A0 - A3 BUFFER IODB0 - DB7

3 FN2967.2 March 20, 2006 82C37A Pin Description SYMBOL PIN NUMBER TYPE DESCRIPTION VCC 31 V CC: is the +5V power supply pin. A 0.1 µF capacitor between pins 31 and 20 is recommended for decoupling. GND 20 Ground CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing sig nals which control 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5 . The Clock may be stopped in either state for standby operation. CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU communications. RESET 13 I RESET: This is an active high input which clears the Command, Status, Request, and Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. Following a Reset, the controller is in an idle cycle. READY 6 I READY: This signal can be used to extend t he memory read and write pulses from the 82C37A to accommodate slow memories or I/O devices. READY must not make transitions during its specified set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode. HLDA 7 I HOLD ACKNOWLEDGE: The active high Hold A cknowledge from the CPU indicates that it has relinquished control of the system busses. HLDA is a synchronous input and must not transition during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of CLK, during which time HLDA must not transition. DREQ0- DREQ3 16-19 I DMA REQUEST: The DMA Request (DREQ) lines are individual asynch ronous channel request inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will acknowledge the recogniti on of a DREQ signal. Polarity of DREQ is programmable. RESET initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. DB0-DB7 21-23 26-30 I/O DATA BUS: The Data Bus lines are bidirectiona l three-state signals connected to the system data bus. The outputs are enabled in the Program condit ion during the I/O Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is programming the 82C37A contro l registers. During DMA cycles, the most significant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during the read-from-memory transfer, then dur ing the write-to-memory transfer, the data bus outputs write the data into the new memory location. IOR 1 I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used by the 82C37A to access data from the peripheral during a DMA Write transfer. IOW 2 I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer. 82C37A

4 FN2967.2 March 20, 2006 82C37A EOP 36 I/O END OF PROCESS: End of Process (EOP ) is an active low bidirectional signal. Information concerning the completion of DMA services is available at the bidirectional EOP pin. The 82C37A allows an external signal to termi nate an active DMA serv ice by pulling the EOP pin low. A pulse is generated by the 82C37A when te rminal count (TC) for any channel is reached, except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will be output when the TC for channel 1 occurs. The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor to VCC. When an EOP pulse occurs, whether internally or exte rnally generated, the 82C37A will terminate the service, and if autoinitialize is enabled, the base registers will be written to the current registers of that channel. The mask bit and TC bit in the status word will be set for the currently active channel by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear. A0-A3 32-35 I/O ADDRESS: The four least signi ficant address lines are bidirectional three-state signals. In the Idle cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address. A4-A7 37-40 O ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of address. These lines are enabled only during the DMA service. HRQ 10 O HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus. When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the 82C37A issues HRQ. The HLDA signal then info rms the controller when access to the system busses is permitted. For stand-alone operation where the 82C37A always controls the busses, HRQ may be tied to HLDA. This will result in one S0 state before the transfer. DACK0- DACK3 14, 15 24, 25 O DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them to active low. AEN 9 O ADDRESS ENABLE: Address Enable enables the 8- bit latch containing the upper 8 address bits onto the system address bus. AEN can also be used to disable other system bus drivers during DMA transfers. AEN is active high. ADSTB 8 O ADDRESS STROBE: This is an active high signal used to control latching of the upper address byte. It will drive directly the strobe input of exte rnal transparent octal latches, such as the 82C82. During block operations, ADSTB will only be issued when the upper address byte must be updated, thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling edge of the 82C37A clock. MEMR 3 O MEMORY READ: The Memory Read signal is an acti ve low three-state output used to access data from the selected memory location during a DMA Read or a memory-to-memory transfer. MEMW 4 O MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data to the selected memory location during a DMA Write or a memory-to-memory transfer. NC 5 NO CONNECT: Pin 5 is open and shoul d not be tested for continuity. Pin Description (Continued) SYMBOL PIN NUMBER TYPE DESCRIPTION 82C37A

6 FN2967.2 March 20, 2006 82C37A system busses and enter the active cycle. The active cycle is composed of several internal states, depending on what options have been selected and what type of operation has been requested. The 82C37A can assume seven separate states, each composed of one full clock period. State I (SI) is the idle state. It is entered when the 82C37A has no valid DMA requests pending, at the end of a transfer sequence, or when a Reset or Master Clear has occurred. While in SI, the DMA controller is inactive but may be in the Program Condition (being programmed by the processor). State 0 (S0) is the first state of a DMA service. The 82C37A has requested a hold but the processor has not yet returned an acknowledge. The 82C37A may still be programmed until it has received HLDA from the CPU. An acknowledge from the CPU will signal the DMA transfer may begin. S1, S2, S3, and S4 are the working state of the DMA service. If more time is needed to complete a transfer than is available with normal timing, wait states (SW) can be inserted between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed transfers, wait states can be inserted between S2 and S4. See timing Figures 14 and 15. Note that the data is transferred directly from the I/O device to memory (or vice versa) with IOR and MEMW (or MEMR and IOW) being active at the same time. The data is not read into or driven out of the 82C37A in I/O-to-memory or memory-to-I/O DMA transfers. Memory-to-memory transfers require a read-from and a write- to memory to complete each transfer. The states, which resemble the normal working states, use two-digit numbers for identification. Eight states are required for a single transfer. The first four states (S11, S12, S13, S14) are used for the read-from-memory half and the last four state (S21, S22, S23, S24) for the write-to-memory half of the transfer. Idle Cycle When no channel is requesting service, the 82C37A will enter the idle cycle and perform “SI” states. In this cycle, the 82C37A will sample the DREQ lines on the falling edge of every clock cycle to determine if any channel is requesting a DMA service. Note that for standby operation where the clock has been stopped, DMA requests will be ignored. The device will respond to CS (chip select), in case of an attempt by the microprocessor to write or read the internal registers of the 82C37A. When CS is low and HLDA is low, the 82C37A enters the Program Condition. The CPU can now establish, change or inspect the internal definition of the part by reading from or writing to the internal registers. The 82C37A may be programmed with the clock stopped, provided that HLDA is low and at least one rising clock edge has occurred after HLDA was driven low, so the controller is in an SI state. Address lines A0-A3 are inputs to the device and select which registers will be read or written. The IOR and IOW lines are used to select and time the read or write operations. Due to the number and size of the internal registers, an internal flip-flop called the First/Last Flip-Flop is used to generate an additional bit of address. The bit is used to determine the upper or lower byte of the 16-bit Address and Work Count registers. The flip-flop is reset by Master Clear or RESET. Separate software commands can also set or reset this flip-flop. Special software commands can be executed by the 82C37A in the Program Condition. These commands are decoded as sets of addresses with CS , IOR, and IOW. The commands do not make use of the data bus. Instructions include Set and Clear First/Last Flip-Flop, Master Clear, Clear Mode Register Counter, and Clear Mask Register. Active Cycle When the 82C37A is in the Idle cycle, and a software request or an unmasked channel requests a DMA service, the device will issue HRQ to the microprocessor and enter the Active cycle. It is in this cycle that the DMA service will take place, in one of four modes: Single Transfer Mode - In Single Transfer mode, the device is programmed to make one transfer only. The word count will be decremented and the address decremented or incremented following each transfer. When the word count “rolls over” from zero to FFFFH, a terminal count bit in the status register is set, an EOP pulse is generated, and the channel will autoinitialize if this option has been selected. If not programmed to autoinitialize, the mask bit will be set, along with the TC bit and EOP pulse. DREQ must be held active until DACK becomes active. If DREQ is held active throughout the single transfer, HRQ will go inactive and release the bus to the system. It will again go active and, upon receipt of a new HLDA, another single transfer will be performed, unless a higher priority channel takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this will ensure one full machine cycle execution between DMA transfers. Details of timing between the 82C37A and other bus control protocols will depend upon the characteristics of the microprocessor involved. Block Transfer Mode - In Block Transfer mode, the device is activated by DREQ or software request and continues making transfers during the service until a TC, caused by word count going to FFFFH, or an external End of Process (EOP ) is encountered. DREQ need only be held active until DACK becomes active. Again, an Autoinitialization will occur at the end of the service if the channel has been programmed for that option. Demand Transfer Mode - In Demand Transfer mode the device continues making transfers until a TC or external EOP is encountered, or until DREQ goes inactive. Thus, transfer may continue until the I/O device has exhausted its data capacity. 82C37A

8 FN2967.2 March 20, 2006 82C37A Channel 0 word count decrementing to FFFFH will not set the channel 0 TC bit in the status register nor generate an EOP , nor set the channel 0 mask bit in this mode. It will cause an autoinitialization of channel 0, if that option has been selected. If full Autoinitialization for a memory-to-memory operation is desired, the channel 0 and channel 1 word counts must be set to equal values before the transfer begins. Otherwise, if channel 0 underflows before channel 1, it will autoinitialize and set the data source address back to the beginning of the block. If the channel 1 word count underflows before channel 0, the memory-to-memory DMA service will terminate, and channel 1 will autoinitialize but channel 0 will not. In memory-to-memory mode, Channel 0 may be programmed to retain the same address for all transfers. This allows a single byte to be written to a block of memory. This channel 0 address hold feature is selected by setting bit 1 in the Command register. The 82C37A will respond to external EOP signals during memory-to-memory transfers, but will only relinquish the system busses after the transfer is complete (i.e. after an S24 state). It should be noted that an external EOP cannot cause the channel 0 Address and Word Count registers to autoinitialize, even if the Mode register is programmed for autoinitialization. An external EOP will autoinitialize the channel 1 registers, if so programmed. Data comparators in block search schemes may use the EOP input to terminate the service when a match is found. The timing of memory-to- memory transfers is found in Figure 13. Memory-to-memory operations can be detected as an active AEN with no DACK outputs. Priority - The 82C37A has two types of priority encoding available as software selectable options. The first is Fixed Priority which fixes the channels in priority order based upon the descending value of their numbers. The channel with the lowest priority is 3 followed by 2, 1 and the highest priority channel, 0. After the recognition of any one channel for service, the other channels are prevented from interfering with the service until it is completed. The second scheme is Rotating Priority. The last channel to get service becomes the lowest priority channel with the others rotating accordingly. The next lower channel from the channel serviced has highest priority on the following request. Priority rotates every time control of the system busses is returned to the processor. Rotating Priority With Rotating Priority in a single chip DMA system, any device requesting service is guaranteed to be recognized after no more than three higher priority services have occurred. This prevents any one channel from monopolizing the system. Regardless of which priority scheme is chosen, priority is evaluated every time a HLDA is returned to the 82C37A. Compressed Timing - In order to achieve even greater throughput where system characteristics permit, the 82C37A can compress the transfer time to two clock cycles. From Figure 12 it can be seen that state S3 is used to extend the access time of the read pulse. By removing state S3, the read pulse width is made equal to the write pulse width and a transfer consists only of state S2 to change the address and state S4 to perform the read/write. S1 states will still occur when A8-A15 need updating (see Address Generation). Timing for compressed transfers is found in Figure 15. EOP will output in S2 if compressed timing is selected. Compressed timing is not allowed for memory-to-memory transfers. Address Generation - In order to reduce pin count, the 82C37A multiplexes the eight higher order address bits on the data lines. State S1 is used to output the higher order address bits to an external latch from which they may be placed on the address bus. The falling edge of Address Strobe (ADSTB) is used to load these bits from the data lines to the latch. Address Enable (AEN) is used to enable the bits onto the address bus through a three-state enable. The lower order address bits are output by the 82C37A directly. Lines A0-A7 should be connected to the address bus. Figure 12 shows the time relationships between CLK, AEN, ADSTB, DB0-DB7 and A0-A7. During Block and Demand Transfer mode service, which include multiple transfers, the addresses generated will be sequential. For many transfers the data held in the external address latch will remain the same. This data need only change when a carry or borrow from A7 to A8 takes place in the normal sequence of addresses. To save time and speed transfers, the 82C37A executes S1 states only when updating of A8-A15 in the latch is necessary. This means for long services, S1 states and Address Strobes may occur only once every 256 transfers, a savings of 255 clock cycles for each 256 transfers. 1st SERVICE Highest Lowest 2nd SERVICE Service 3rd SERVICE Service Request Service

9 FN2967.2 March 20, 2006 82C37A Programming The 82C37A will accept programming from the host processor anytime that HLDA is inactive, and at least one rising clock edge has occurred after HLDA went low. It is the responsibility of the host to assure that programming and HLDA are mutually exclusive. Note that a problem can occur if a DMA request occurs on an unmasked channel while the 82C37A is being programmed. For instance, the CPU may be starting to reprogram the two byte Address register of channel 1 when channel 1 receives a DMA request. If the 82C37A is enabled (bit 2 in the Command register is 0), and channel 1 is unmasked, a DMA service will occur after only one byte of the Address register has been reprogrammed. This condition can be avoided by disabling the controller (setting bit 2 in the Command register) or masking the channel before programming any of its registers. Once the programming is complete, the controller can be enabled/unmasked. After power-up it is suggested that all internal locations be loaded with some known value, even if some channels are unused. This will aid in debugging. Register Description Current Address Register - Each channel has a 16-bit Current Address register. This register holds the value of the address used during DMA transfers. The address is automatically incremented or decremented by one after each transfer and the values of the address are stored in the Current Address register during the transfer. This register is written or read by the microprocessor in successive 8-bit bytes. See Figure 6 for programming information. It may also be reinitialized by an Autoinitialize back to its original value. Autoinitialize takes place only after an EOP . In memory-to- memory mode, the channel 0 Current Address register can be prevented from incrementing or decrementing by setting the address hold bit in the Command register. Current Word Count Register - Each channel has a 16-bit Current Word Count register. This register determines the number of transfers to be performed. The actual number of transfers will be one more than the number programmed in the Current Word Count register (i.e., programming a count of 100 will result in 101 transfers). The word count is decremented after each transfer. When the value in the register goes from zero to FFFFH, a TC will be generated. This register is loaded or read in successive 8-bit bytes by the microprocessor in the Program Condition. See Figure 6 for programming information. Following the end of a DMA service it may also be reinitialized by an Autoinitialization back to its original value. Autoinitialization can occur only when an EOP occurs. If it is not Autoinitialized, this register will have a count of FFFFH after TC. Base Address and Base Word Count Registers - Each channel has a pair of Base Address and Base Word Count registers. These 16-bit registers store the original value of their associated current registers. During Autoinitialize these values are used to restore the current registers to their original values. The base registers are written simultaneously with their corresponding current register in 8- bit bytes in the Program Condition by the microprocessor. See Figure 6 for programming information. These registers cannot be read by the microprocessor. Command Register - This 8-bit register controls the operation of the 82C37A. It is programmed by the microprocessor and is cleared by RESET or a Master Clear instruction. The following diagram lists the function of the Command register bits. See Figure 4 for Read and Write addresses. Mode Register - Each channel has a 6-bit Mode register associated with it. When the register is being written to by the microprocessor in the Program condition, bits 0 and 1 determine which channel Mode register is to be written. When the processor reads a Mode register, bits 0 and 1 will Command Register

76543210 B I T N U M B E R

X Channel 0 address hold disable Channel 0 address hold enable If bit 0 = 0 Controller enable Controller disable X Normal timing Compressed timing If bit 0 = 1 Fixed priority Rotating priority X Late write selection Extended write selection If bit 3 = 1 DREQ sense active high DREQ sense active low DACK sense active low DACK sense active high 82C37A

10 FN2967.2 March 20, 2006 82C37A both be ones. See the following diagram and Figure 4 for Mode register functions and addresses. Request Register - The 82C37A can respond to requests for DMA service which are initiated by software as well as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request register. These are non-maskable and subject to prioritization by the Priority Encoder network. Each register bit is set or reset separately under software control. The entire register is cleared by a Reset or Master Clear instruction. To set or reset a bit, the software loads the proper form of the data word. See Figure 4 for register address coding, and the following diagram for Request register format. A software request for DMA operation can be made in block or single modes. For memory-to-memory transfers, the software request for channel 0 should be set. When reading the Request register, bits 4-7 will always read as ones, and bits 0-3 will display the request bits of channels 0-3 respectively. Mask Register - Each channel has associated with it a mask bit which can be set to disable an incoming DREQ. Each mask bit is set when its associated channel produces an EOP if the channel is not programmed to Autoinitialize. Each bit of the 4-bit Mask register may also be set or cleared separately or simultaneously under software control. The entire register is also set by a Reset or Master clear. This disables all hardware DMA requests until a Clear Mask Register instruction allows them to occur. The instruction to separately set or clear the mask bits is similar in form to that used with the Request register. Refer to the following diagram and Figure 4 for details. When reading the Mask register, bits 4-7 will always read as logical ones, and bits 0-3 will display the mask bits of channels 0-3, respectively. The 4 bits of the Mask register may be cleared simultaneously by using the Clear Mask Register command (see software commands section). All four bits of the Mask register may also be written with a single command. Status Register - The Status register is available to be read out of the 82C37A by the microprocessor. It contains information about the status of the devices at this point. This information includes which channels have reached a terminal count and which channels have pending DMA requests. Bits 0-3 are set every time a TC is reached by that channel or an external EOP is applied. These bits are cleared upon RESET, Master Clear, and on each Status Read. Bits 4-7 are set whenever their corresponding channel is requesting service, regardless of the mask bit state. If the mask bits are set, software can poll the Status register to determine which channels have DREQs, and selectively clear a mask bit, thus allowing user defined service priority. Status bits 4-7 are updated while the clock is high, and latched on the falling Mode Register If bits 6 and 7 = 11 Autoinitialization disable Autoinitialization enable Address increment select Address decrement select Demand mode select Single mode select Block mode select Cascade mode select Request Register Don’t Care, Write Bits 4-7 All Ones, Read Mask Register Don’t Care Don’t Care, Write All Ones, Read 82C37A

read type commands, the data value is not guaranteed. address upper and lower bytes in the correct sequence. address and word count registers. is set. The 82C37A will enter the idle cycle. of all four channels, enabling them to accept DMA requests. then do consecutive reads until the desired channel is read. bits on all Mode registers will read as ones.

1 Channel 0 has reached TC

1 Channel 1 has reached TC

1 Channel 2 has reached TC

1 Channel 3 has reached TC

1 Channel 0 request

1 Channel 1 request

1 Channel 2 request

1 Channel 3 request

FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES

12 FN2967.2 March 20, 2006 82C37A External EOP Operation The EOP pin is a bidirectional, open drain pin which may be driven by external signals to terminate DMA operation. Because EOP is an open drain pin an external pull-up resistor to VCC is required. The value of the external pull-up resistor used should guarantee a rise time of less than 125ns. It is important to note that the 82C37A will not accept external EOP signals when it is in a SI (Idle) state. The controller must be active to latch EXT EOP. Once latched, the EXT EOP will be acted upon during the next S2 state, unless the 82C37A enters an idle state first. In the latter case, the latched EOP is cleared. External EOP pulses occurring between active DMA transfers in demand mode will not be recognized, since the 82C37A is in an SI state.

Application Information

Figure 6 shows an application for a DMA system utilizing the 82C37A DMA controller and the 80C88 Microprocessor. In this application, the 82C37A DMA controller is used to improve system performance by allowing an I/O device to transfer data directly to or from system memory. Components The system clock is generated by the 82C84A clock driver and is inverted to meet the clock high and low times required by the 82C37A DMA controller. The four OR gates are used to support the 80C88 Microprocessor in minimum mode by producing the control signals used by the processor to access memory or I/O. A decoder is used to generate chip select for the DMA controller and memory. The most significant bits of the address are output on the address/data bus. Therefore, the 82C82 octal latch is used to demultiplex the address. Hold Acknowledge (HLDA) and Address Enable (AEN) are “ORed” together to insure that the DMA controller does not have bus contention with the microprocessor. Operation A DMA request (DREQ) is generated by the I/O device. After receiving the DMA request, the DMA controller will issue a Hold request (HRQ) to the processor. The system busses are not released to the DMA controller until a Hold Acknowledge signal is returned to the DMA controller from the 80C88 processor. After the Hold Acknowledge has been CHANNEL REGISTER OPERATION SIGNALS FIRST/LAST FLIP-FLOP STATE DATA BUS DB0-DB7CS IOR IOW A3 A2 A1 A0

0 B a s e a n d C u r r e n t A d d r e s s W r i t e 0100000 0 A 0 - A 7

C u r r e n t A d d r e s s R e a d 0010000 0 A 0 - A 7 0010000 1 A 8 - A 1 5 Base and Current Word Count W r i t e 0100001 0 W 0 - W 7 0100001 1 W 8 - W 1 5 Current Word Count Read 0010001 0 W 0 - W 7 0010001 1 W 8 - W 1 5

1 B a s e a n d C u r r e n t A d d r e s s W r i t e 0100010 0 A 0 - A 7

C u r r e n t A d d r e s s R e a d 0010010 0 A 0 - A 7 0010010 1 A 8 - A 1 5 Base and Current Word Count W r i t e 0100011 0 W 0 - W 7 0100011 1 W 8 - W 1 5 Current Word Count Read 0010011 0 W 0 - W 7 0010011 1 W 8 - W 1 5

2 B a s e a n d C u r r e n t A d d r e s s W r i t e 0100100 0 A 0 - A 7

C u r r e n t A d d r e s s R e a d 0010100 0 A 0 - A 7 0010100 1 A 8 - A 1 5 Base and Current Word Count W r i t e 0100101 0 W 0 - W 7 0100101 1 W 8 - W 1 5 Current Word Count Read 0010101 0 W 0 - W 7 0010101 1 W 8 - W 1 5

3 B a s e a n d C u r r e n t A d d r e s s W r i t e 0100110 0 A 0 - A 7

C u r r e n t A d d r e s s R e a d 00101100 A 0 - A 7

00101101 A 8 - A 1 5

W r i t e 01001110 W 0 - W 7

01001111 W 8 - W 1 5

Current Word Count Read 00101110 W 0 - W 7

00101111 W 8 - W 1 5

FIGURE 5. WORD COUNT AND ADDRESS REGISTER COMMAND CODES

FIGURE 6. APPLICATION FOR DMA SYSTEM NOTE: The address lines need pull-up resistors.

15 FN2967.2 March 20, 2006 82C37A Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) oC to +150oC Maximum Lead Temperature Package (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -40oC to +85oC (I82C37A) TA = -55oC to +125oC (M82C37A) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2 - v C82C37A, I82C37A 2.2 - V M82C37A VIL Logical Zero Input Voltage - 0.8 V VIHC CLK Input Logical One Voltage V CC -0.8 - V VILC CLK Input Logical Zero Voltage - 0.8 V VOH Output HIGH Voltage 3.0 - V IOH = -2.5mA VCC -0.4 - V IOH = -100 µA VOL Output LOW Voltage - 0.4 V IOL = +2.5mA all output except EOP , IOL = +3.2mA for EOP pin 36 only. II Input Leakage Current -1 +1 µA VIN = GND or V CC, Pins 6, 7, 11-13, 16-19 IO Output Leakage Current -10 +10 µA VOUT = GND or V CC, Pins 1-4, 21-23, 26-30, 32-40 ICCSB Standby Power Supply Current -1 0 µAV CC = 5.5V, VIN = VCC or GND, Outputs Open ICCOP Operating Power Supply Current -2 m A / M H z V CC = 5.5V, CLK FREQ = Maximum, VIN = VCC or GND, Outputs Open Capacitance TA = +25oC SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 25 pF FREQ = 1MHz, All measurements are referenced to device GND COUT Output Capacitance 40 pF CI/O I/O Capacitance 25 pF

16 FN2967.2 March 20, 2006 82C37A TA = -40oC to +85oC (I82C37A), TA = -55oC to +125oC (M82C37A) SYMBOL PARAMETER 82C37A-5 82C37A 82C37A-12 UNITSMIN MAX MIN MAX MIN MAX DMA (MASTER) MODE (1)TAEL AEN HIGH from CLK LOW (S1) Delay Time - 175 - 105 - 50 ns (2)TAET AEN LOW from CLK HIGH (SI) Delay Time - 130 - 80 - 50 ns (3)TAFAB ADR Active to Float Delay from CLK HIGH -9 0 -5 5-5 5 n s (4)TAFC READ or WRITE Float Delay from CLK HIGH - 120 - 75 - 50 ns (5)TAFDB DB Active to Float Delay from CLK HIGH - 170 - 135 - 90 ns (6)TAHR ADR from READ HIGH Hold Time TCY-100 - TCY-75 - TCY-65 - ns (7)TAHS DB from ADSTB LOW Hold Time TCL-18 - TCL-18 - TCL-18 - ns (8)TAHW ADR from WRITE HIGH Hold Time TCY-65 - TCY-65 - TCY-50 - ns (9)TAK DACK Valid from CLK LOW Delay Time - 170 - 105 - 69 ns EOP HIGH from CLK HIGH Delay Time - 170 - 105 - 90 ns EOP LOW from CLK HIGH Delay Time - 100 - 60 - 35 ns (10)TASM ADR Stable from CLK HIGH - 110 - 60 - 50 ns (11)TASS DB to ADSTB LOW Setup Time TCH-20 - TCH-20 - TCH-20 - ns (12)TCH CLK HIGH Time (Transitions 10ns) 70 - 55 - 30 - ns (13)TCL CLK LOW Time (Transitions 10ns) 50 - 43 - 30 - ns (14)TCY CLK Cycle Time 200 - 125 - 80 - ns (15)TDCL CLK HIGH to READ or WRITE LOW Delay - 190 - 130 - 120 ns (16)TDCTR READ HIGH from CLK HIGH (S4) Delay Time - 190 - 115 - 80 ns (17)TDCTW WRITE HIGH from CLK HIGH (S4) Delay Time - 130 - 80 - 70 ns (18)TDQ HRQ Valid from CLK HIGH Delay Time - 120 - 75 - 30 ns (19)TEPH EOP Hold Time from CLK LOW (S2) 90 - 90 - 50 - ns (20)TEPS EOP LOW to CLK LOW Setup Time 40 - 25 - 0 - ns

17 FN2967.2 March 20, 2006 82C37A (21)TEPW EOP Pulse Width 220 - 135 - 50 - ns (22)TFAAB ADR Valid Delay from CLK HIGH - 110 - 60 - 50 ns (23)TFAC READ or WRITE Active from CLK HIGH - 150 - 90 - 50 ns (24)TFADB DB Valid Delay from CLK HIGH - 110 - 60 - 45 ns (25)THS HLDA Valid to CLK HIGH Setup Time 75 - 45 - 10 - ns (26)TIDH Input Data from MEMR HIGH Hold Time 0- 0-0- n s (27)TIDS Input Data to MEMR HIGH Setup Time 155 - 90 - 45 - ns (28)TODH Output Data from MEMW HIGH Hold Time 15 - 15 - TCY-50 - ns (29)TODV Output Data Valid to MEMW HIGH TCY-35 - TCY-35 - TCY-10 - ns (30)TQS DREQ to CLK LOW (SI, S4) Setup Time 0- 0-0- n s (31)TRH CLK to READY LOW Hold Time 20 - 20 - 10 - ns (32)TRS READY to CLK LOW Setup Time 60 - 35 - 15 - ns (33)TCLSH ADSTB HIGH from CLK LOW Delay Time -8 0 -7 0-7 0 n s (34)TCLSL ADSTB LOW from CLK LOW Delay Time - 120 - 120 - 60 ns (35)TWRRD READ HIGH Delay from WRITE H I G H 0- 0-5- n s (36)TRLRH READ Pulse Width, Normal Timing 2TCY-60 - 2TCY-60 - 2TCY-55 - ns (37)TSHSL ADSTB Pulse Width TCY-80 - TCY-50 - TCY-35 - ns (38)TWLWHA Extended WRITE Pulse Width 2TCY-100 - 2TCY-85 - 2TCY-80 - ns (39)TWLWH WRITE Pulse Width TCY-100 - TCY-85 - TCY-80 - ns (40)TRLRHC READ Pulse Width, Compressed TCY-60 - TCY-60 - TCY-55 - ns (56)TAVRL ADR Valid to READ LOW 17 - 17 - 17 - ns (57)TAVWL ADR Valid to WRITE LOW 7 - 7 - 7 - ns (58)TRHAL READ HIGH to AEN LOW 15 - 15 - 15 - ns (59)TRHSH READ HIGH to ADSTB HIGH 13 - 13 - 13 - ns (60)TWHSH WRITE HIGH to ADSTB HIGH 15 - 15 - 15 - ns (61)TDVRL DACK Valid to READ LOW 25 - 25 - 25 - ns TA = -40oC to +85oC (I82C37A), TA = -55oC to +125oC (M82C37A) (Continued) SYMBOL PARAMETER 82C37A-5 82C37A 82C37A-12 UNITSMIN MAX MIN MAX MIN MAX 82C37A

18 FN2967.2 March 20, 2006 82C37A (62)TDVWL DACK Valid to WRITE LOW 25 - 25 - 25 - ns (63)TRHDI READ HIGH to DACK Inactive 12 - 12 - 12 - ns (64)TAZRL ADR Float to READ LOW -2.5 - -2.5 - -2.5 - ns PERIPHERAL (SLAVE) MODE (41)TAR ADR Valid or CS LOW to READ LOW 10 - 10 - 0 - ns (42)TAWL ADR Valid to WRITE L O W S e t u p T i m e 0- 0-0- n s (43)TCWL CS LOW to WRITE LOW Setup Time 0 - 0 - 0 - ns (44)TDW Data Valid to WRITE HIGH Setup Time 150 - 100 - 60 - ns (45)TRA ADR or CS Hold from READ H I G H 0- 0-0- n s (46)TRDE Data Access from READ - 140 - 120 - 80 ns (47)TRDF DB Float Delay from READ H I G H 58 5 58 555 5 n s (48)TRSTD Power Supply HIGH to RESET LOW Setup Time 500 - 500 - 500 - ns (49)TRSTS RESET to First IOR or IOW 2TCY - 2TCY - 2TCY - ns (50)TRSTW RESET Pulse Width 300 - 300 - 300 - ns (51)TRW READ Pulse Width 200 - 155 - 85 - ns (52)TWA ADR from WRITE H I G H H o l d T i m e 0- 0-0- n s (53)TWC CS HIGH from WRITE HIGH Hold Time 0- 0-0- n s (54)TWD Data from WRITE HIGH Hold Time 10 - 10 - 10 - ns (55)TWWS WRITE Pulse Width 150 - 100 - 45 - ns TA = -40oC to +85oC (I82C37A), TA = -55oC to +125oC (M82C37A) (Continued) SYMBOL PARAMETER 82C37A-5 82C37A 82C37A-12 UNITSMIN MAX MIN MAX MIN MAX 82C37A

FIGURE 10. DMA TRANSFER

23 FN2967.2 March 20, 2006 82C37A Burn-In Circuits MD82C37A CERDIP MR82C37A CLCC NOTES: 1. V CC = 5.5V ± 0.5V 3. VIL = -0.2V to 0.4V 4. GND = 0V 5. R1 = 1.2k Ω ±5% 6. R2 = 47k Ω ±5% 7. C1 = 0.01 µF minimum 8. C2 = 0.1 µF minimum 9. D1 = 1N4002 10. F0 = 100kHz ±10% 12. DO0 - DO6 are outputs from the 82C82 Octal Latching Bus Driver DO5 VCC/2 VCC/2 VCC/2 A DO5 VCC/2 VCC/2 VCC/2 DO5 DO6 VCC/2 F12 F13 F14 F15 GND VCC VCC/2 VCC/2 VCC/2 A VCC DO1 VCC DO0 B DO2 DO3 DO4 F10 VCC/2 VCC/2 DO4 VCC/2 VCC/2 F9 VCC/2 VCC/2 F14 F13 F12 VCC/2 F15 GND DO4 OPEN DO5 VCC/2 VCC/2 DO5 D06 VCC/2 OPEN VCC/2 46 3 1 4041424344 A VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 A VCC DO1 B DO2 DO3 DO4 F10 VCC VCC/2 VCC DO5 OPEN OPEN DO4 2827262524232221201918 VCC VCC C1C1 AB 82C37A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2967.2 March 20, 2006 Die Characteristics DIE DIMENSIONS: 148 x 159 x 19 ±1mils (3760- x 4040 x 525µm) METALLIZATION: Type: SiAlCu Thickness: Metal 1: 8kÅ ± 0.75kÅ Thickness: Metal 2: 12kÅ ± 1.0kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å ± 3kÅ WORST CASE CURRENT DENSITY: 0.6 x 105 A/cm2 Metallization Mask Layout 82C37A 82C37A82C37A