CS82C237

82C237 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• Fully Compatible with Intersil 82C37A - 82C237 May be Used in 8MHz and 12.5MHz 82C37A Sockets
• Optimized for 10MHz and 12.5MHz 80C286 Systems
• Special Mode Permits 16-Bit, Zero Wait State DMA Transfers
• High Speed Data Transfers: - Up to 6.25MBytes/sec with 12.5MHz Clock in Normal Mode - Up to 12.5MBytes/sec with 12.5MHz Clock in 16-Bit Mode
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial- ization Capability
• Cascadable to any Number of Channels
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation - ICCSB = 10µA Maximum - ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software

Description

The 82C237 is a modified version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the 82C37A but provides an additional mode for 16-bit DMA transfers, as well as enhanced speed. Each channel may be individually programmed for 8-bit or 16-bit data transfers. The 82C237 controller can improve system performance by allowing external devices to transfer data directly to or from system memory. Memory-to-memory transfer capability is also provided, along with a memory block initialization fea- ture. DMA requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for flexible operation. The 82C237 is designed to be used with an external address latch, such as the 82C82, to demultiplex the most significant 8 bits of address. An additional latch is required to temporarily store the most significant 8 bits of data if 16-bit memory-to-memory transfers are desired. The 82C237 can be used with industry standard microprocessors such as 80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and others. Multimode programmability allows the user to select from three basic types of DMA services, and reconfiguration under program control is possible even with the clock to the controller stopped. Each channel has a full 64K address and word count range, and may be programmed to autoinitialize these registers following DMA termination (end of process).

Ordering Information

RANGE 8MHz 12.5MHz PKG. NO. PDIP 0 oC to +70oC CP82C237 CP82C237-12 E40.6 -40oC to +85oC IP82C237 IP82C237-12 E40.6 PLCC 0 oC to +70oC CS82C237 CS82C237-12 N44.65 -40oC to +85oC IS82C237 IS82C237-12 N44.65 SBDIP 0 oC to +70oC CD82C237 CD82C237-12 F40.6 -40oC to +85oC ID82C237 ID82C237-12 F40.6 -55oC to +125oC MD82C237/B MD82C237-12/B F40.6 SMD# 5962-9054304MQA 5962-9054305MQA F40.6 CLCC -55 oC to +125oC MR82C237/B MR82C237-12/B J44.A SMD# 5962-9054304MXA 5962-9054305MXA J44.A File Number 2965.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

82C237 (DIP) TOP VIEW 82C237 (CLCC/PLCC) TOP VIEW IOR IOW MEMR MEMW DWLE READY HLDA ADSTB AEN HRQ CS CLK RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 (GND) VSS EOP V CC DB0 DB1 DB2 DB3 DB4 DACK0 DACK1 DB5 DB6 DB7 (NOTE) 46 3 1 4041424344 2827262524232221201918 CS DACK2 NC NC CLK HRQ NC VCC DB0 DB1 DB2 DB3 NC DB4 READY DWLE MEMW EOP DACK3 DREQ3 DREQ2 DREQ1 DREQ0 GND DB5 DACK1 DB7 DACK0 DB6 MEMR ADSTB AEN IOW RESET HLDA IOR NOTE: See Pin Description. (NOTE) A4 - A7 EOP RESET CS READY CLK AEN ADSTB MEMR MEMW IOR IOW TIMING AND CONTROL DREQ0 - HLDA HRQ DACK0 - PRIORITY ENCODER AND ROTATING PRIORITY LOGIC DACK3 DREQ3

4 COMMAND

(8) MASK (4) REQUEST (4) MODE (4 x 6) STATUS (8) TEMPORARY (8) INTERNAL DATA BUS DECREMENTOR COUNT REG (16) TEMP WORD INC DECREMENTOR REG (16) TEMP ADDRESS BUFFER IO 16-BIT BUS READ BUFFER ADDRESS BASE (16) WORD BASE COUNT (16) READ WRITE BUFFER ADDRESS CURRENT (16) WORD CURRENT COUNT (16) 16-BIT BUS BUFFER WRITE BUFFER READ A8 - A15 BUFFER OUTPUT CONTROL COMMAND D0 - D1 A0 - A3 BUFFER IODB0 - DB7 DWLE DATA-WIDTH (4)

VCC 31 V CC : is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for decoupling. GND 20 Ground CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C237 operations. This input may be driven from DC to 12.5MHz for the 82C237-12 or from DC to 8MHz for the 82C237. The Clock may be stopped in either state for standby operation. CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU communications. RESET 13 I RESET: This is an active high input which clears the Command, Status, Request, and Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. The Data-Width register is set to perform 8-bit transfers on all channels (82C237 only). Following a Reset, the controller is in an idle cycle. READY 6 I READY: This signal can be used to extend the memory read and write pulses from the 82C237 to accommodate slow memories or I/O devices. READY must not make transitions during its specified set-up and hold times. See Figure 14 for timing. READY is ignored in verify transfer mode. HLDA 7 I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has relinquished control of the system busses. HLDA is a synchronous input and must not transition during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of clock, during which time HLDA must not transition. DREQ0- DREQ3 16-19 I DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is programmable. RESET initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. In 16-bit Transfer mode (82C237 only), each DREQ channel may be programmed to perform either 8-bit or 16-bit DMA transfers. DB0-DB7 21-23 26-30 I/O DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled in the Program condition during the I/O Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is programming the 82C237 control registers. During DMA cycles, the most signifi- cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory enters the 82C237 on the data bus during the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new memory location. IOR 1 I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con- trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used by the 82C237 to access data from the peripheral during a DMA Write transfer. IOW 2 I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con- trol signal used by the CPU to load information into the 82C237. In the Active cycle, it is an output control signal used by the 82C237 to load data to the peripheral during a DMA Read transfer.

EOP 36 I/O END OF PROCESS: End of Process ( EOP) is an active low bidirectional signal. Information concerning the completion of DMA services is available at the bidirectionalEOP pin. The 82C237 allows an external signal to terminate an active DMA service by pulling theEOP pin low. A pulse is generated by the 82C237 when terminal count (TC) for any channel is reached, except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will be output when the TC for channel 1 occurs. The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor to VCC . When an EOP pulse occurs, whether internally or externally generated, the 82C237 will terminate the service, and if autoinitialize is enabled, the base registers will be written to the current registers of that channel. The mask bit and TC bit in the status word will be set for the currently active channel by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear. A0-A3 32-35 I/O ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle cycle, they are inputs and are used by the 82C237 to address the control register to be loaded or read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address. When in 16-bit mode (82C237 only), and the active channel is a 16-bit channel (as defined by the Data- Width register), then A0 will remain low during the entire transfer (i.e. an even word address will al- ways be generated). A4-A7 37-40 O ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of address. These lines are enabled only during the DMA service. HRQ 10 O HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus. When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the 82C237 issues HRQ. The HLDA signal then informs the controller when access to the system busses is permitted. For stand-alone operation where the 82C237 always controls the busses, HRQ may be tied to HLDA. This will result in one S0 state before the transfer. DACK0- DACK3 14, 15 24, 25 O DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them to active low. AEN 9 O ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits onto the system address bus. AEN can also be used to disable other system bus drivers during DMA transfers. AEN is active HIGH. ADSTB 8 O ADDRESS STROBE: This is an active high signal used to control latching of the upper address byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82. During block operations, ADSTB will only be issued when the upper address byte must be updated, thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling edge of the 82C237 clock. MEMR 3 O MEMORY READ: The Memory Read signal is an active low three-state output used to access data from the selected memory location during a DMA Read or a memory-to-memory transfer. MEMW 4 O MEMORY WRITE: The Memory Write is an active low three-state output used to write data to the selected memory location during a DMA Write or a memory-to-memory transfer. DWLE 5 O DATA-WIDTH, LATCH ENABLE: In normal 8-bit transfer mode (16-bit transfer mode not enabled), this output is always high impedance three-stated. In 16-bit transfer mode (82C237 only), this output serves a dual purpose. During S1 cycles, the DWLE output indicates the data width (0 = 16-bit, 1 = 8-bit) of the active channel. During memory-to-memory transfers, the DWLE output is used to enable an external latch which temporarily stores the 8 most significant bits of data during the read-from- memory transfer. DWLE enables this byte of data onto the data bus during the write-to-memory transfer of a memory-to-memory operation. Pin Description (Continued) SYMBOL PIN NUMBER TYPE DESCRIPTION

The 82C237 can assume seven separate states, each composed of one full CLK period. State I (SI) is the idle state. It is entered when the 82C237 has no valid DMA requests pending, at the end of a transfer sequence, or when a RESET or Master Clear has occurred. While in SI, the DMA controller is inactive but may be in the Program Condition (being programmed by the processor). State 0 (S0) is the first state of a DMA service. The 82C237 has requested a hold but the processor has not yet returned an acknowledge. The 82C237 may still be programmed until it has received HLDA from the CPU. An acknowledge from the CPU will signal the DMA transfer may begin. S1, S2, S3, and S4 are the working state of the DMA service. If more time is needed to complete a transfer than is available with normal timing, wait states (SW) can be inserted between S3 and S4 in normal transfers by the use of the READY line on the 82C237. For compressed transfers, wait states can be inserted between S2 and S4. See timing Figures 14 and 15. Note that the data is transferred directly from the I/O device to memory (or vice versa) with IOR and MEMW (or MEMR and IOW) being active at the same time. The data is not read into or driven out of the 82C237 in I/O-to-memory or memory-to-I/O DMA transfers. Memory-to-memory transfers require a read-from and a write- to memory to complete each transfer. The States, which resemble the normal working states, use two-digit numbers for identification. Eight states are required for a single transfer. The first four states (S11, S12, S13, S14) are used for the read-from-memory half and the last four states (S21, S22, S23, S24) for the write-to-memory half of the transfer. Idle Cycle When no channel is requesting service, the 82C237 will enter the idle cycle and perform “SI” States. In this cycle, the 82C237 will sample the DREQ lines on the falling edge of every CLK cycle to determine if any channel is requesting a DMA service. Note that for standby operation where the clock has been stopped, DMA requests will be ignored. The device will respond to CS (chip select), in case of an attempt by the microprocessor to write or read the internal registers of the 82C237. When CS is low and HLDA is low, the 82C237 enters the Program Condition. The CPU can now establish, change or inspect the internal definition of the part by read- ing from or writing to the internal registers. The 82C237 may be programmed with the clock stopped, provided that HLDA is low and at least one rising CLK edge has occurred after HLDA was driven low, so the controller is in an SI state. Address lines A0-A3 are inputs to the device and select which registers will be read or written. The IOR and IOW lines are used to select and time the read or write operations. Due to the number and size of the internal regis- ters, an internal flip-flop called the First/Last Flip-Flop is used to generate an additional bit of address. The bit is used to determine the upper or lower byte of the 16-bit Address and Work Count registers. The flip-flop is reset by Master Clear or RESET. Separate software commands can also set or reset this flip-flop. Special software commands can be executed by the 82C237 in the Program Condition. These commands are decoded as sets of addresses with CS, IOR, andIOW. The commands do not make use of the data bus. Instructions include Set and Clear First/Last Flip-Flop, Master Clear, Clear Mode Register Counter, and Clear Mask Register. Active Cycle When the 82C237 is in the Idle cycle, and a software request or an unmasked channel requests a DMA service, the device will issue HRQ to the microprocessor and enter the Active cycle. It is in this cycle that the DMA service will take place, in one of four modes: Single Transfer Mode -In single transfer mode, the device is programmed to make one transfer only. The word count will be decremented and the address decremented or incremented following each transfer. When the word count “rolls over” from zero to FFFFH, a terminal count bit in the status register is set, an EOP pulse is generated, and the channel will autoinitialize if this option has been selected. If not programmed to autoinitialize, the mask bit will be set, along with the TC bit and EOP pulse. DREQ must be held active until DACK becomes active. If DREQ is held active throughout the single transfer, HRQ will go inactive and release the bus to the system. It will again go active and, upon receipt of a new HLDA, another single transfer will be performed, unless a higher priority channel takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this will ensure one full machine cycle execution between DMA transfers. Details of timing between the 82C237 and other bus control protocols will depend upon the characteristics of the microprocessor involved. Block Transfer Mode -In Block Transfer mode, the device is activated by DREQ or software request and continues making transfers during the service until a TC, caused by word count going to FFFFH, or an external End of Process EOP) is encountered. DREQ need only be held active until DACK becomes active. Again, an Autoinitialization will occur at the end of the service if the channel has been programmed for that option. Demand Transfer Mode -In Demand Transfer mode the device continues making transfers until a TC or external EOP is encountered, or until DREQ goes inactive. Thus, transfer may continue until the I/O device has exhausted its data capacity. After the I/O device has had a chance to catch up, the DMA service is reestablished by means of a DREQ. During the time between services when the microprocessor is allowed to operate, the intermediate values of address and word count are stored in the 82C237 Current Address and Current Word Count registers. Higher priority channels may intervene in the demand process, once DREQ has gone inactive. Only an EOP can cause an Autoinitialization at the end of service.EOP is generated either by TC or by an external signal. Cascade Mode -This mode is used to cascade more than one 82C237 for simple system expansion. The HRQ and HLDA signals from the additional 82C237 are connected to the DREQ and DACK signals respectively of a channel for

autoinitialize, even if the Mode register is programmed for autoinitialization. An externalEOP will autoinitialize the channel 1 registers, if so programmed. Data comparators in block search schemes may use the EOP input to terminate the service when a match is found. The timing of memory-to- memory transfers in found in Figure 13. Memory-to-memory operations can be detected as an active AEN with no DACK outputs. Priority -The 82C237 has two types of priority encoding available as software selectable options. The first is Fixed Priority which fixes the channels in priority order based upon the descending value of their numbers. The channel with the lowest priority is 3 followed by 2, 1 and the highest priority channel, 0. After the recognition of any one channel for ser- vice, the other channels are prevented from interfering with the service until it is completed. The second scheme is Rotating Priority. The last channel to get service becomes the lowest priority channel with the others rotating accordingly. The next lower channel from the channel serviced has highest priority on the following request. Priority rotates every time control of the system busses is returned to the processor. Rotating Priority With Rotating Priority in a single chip DMA system, any device requesting service is guaranteed to be recognized after no more than three higher priority services have occurred. This prevents any one channel from monopolizing the system. Regardless of which priority scheme is chosen, priority is evaluated every time a HLDA is returned to the 82C237. Compressed Timing -In order to achieve even greater throughput where system characteristics permit, the 82C237 can compress the transfer time to two clock cycles. From Figure 12 it can be seen that state S3 is used to extend the access time of the read pulse. By removing state S3, the read pulse width is made equal to the write pulse width and a transfer consists only of state S2 to change the address and state S4 to perform the read/write. S1 states will still occur when A8-A15 need updating (see Address Generation). Timing for compressed transfers is found in Fig- ure 15. EOP will output in S2 if compressed timing is selected. Compressed timing is not allowed for memory-to- memory transfers. Address Generation -In order to reduce pin count, the 82C237 multiplexes the eight higher order address bits on the data lines. State S1 is used to output the higher order address bits to an external latch from which they may be placed on the address bus. The falling edge of Address Strobe (ADSTB) is used to load these bits from the data lines to the latch. Address Enable (AEN) is used to enable the bits onto the address bus through a three-state enable. The lower order address bits are output by the 82C237 directly. Lines A0-A7 should be connected to the address bus. Figure 12 shows the time relationships between CLK, AEN, ADSTB, DB0-DB7 and A0-A7. During Block and Demand Transfer mode service, which include multiple transfers, the addresses generated will be sequential. For many transfers the data held in the external address latch will remain the same. This data need only change when a carry or borrow from A7 to A8 takes place in the normal sequence of addresses. To save time and speed transfers, the 82C237 executes S1 states only when updating of A8-A15 in the latch is necessary. This means for long services, S1 states and Address Strobes may occur only once every 256 transfers, a savings of 255 clock cycles for each 256 transfers. Programming The 82C237 will accept programming from the host processor anytime that HLDA is inactive, and at least one rising CLK edge has occurred after HLDA went low. It is the responsibility of the host to assure that programming and HLDA are mutually exclusive. Note that a problem can occur if a DMA request occurs on an unmasked channel while the 82C237 is being pro- grammed. For instance, the CPU may be starting to repro- gram the two byte Address register of channel 1 when channel 1 receives a DMA request. If the 82C237 is enabled (bit 2 in the Command register is 0), and channel 1 is unmasked, a DMA service will occur after only one byte of the Address register has been reprogrammed. This condi- tion can be avoided by disabling the controller (setting bit 2 in the Command register) or masking the channel before programming any of its registers. Once the programming is complete, the controller can be enabled/unmasked. After power-up it is suggested that all internal locations be loaded with some known value, even if some channels are unused. This will aid in debugging. Register Description Current Address Register -Each channel has a 16-bit Current Address register. This register holds the value of the address used during DMA transfers. The address is auto- matically incremented or decremented by one after each transfer and the values of the address are stored in the Cur- rent Address register during the transfer. This register is writ- ten or read by the microprocessor in successive 8-bit bytes. See Figure 6 for programming information. It may also be reinitialized by an Autoinitialize back to its original value. Autoinitialize takes place only after an EOP . In memory-to- memory mode, the channel 0 Current Address register can be prevented from incrementing or decrementing by setting the address hold bit in the Command register. 1ST SERVICE Highest Lowest 2nd SERVICE Service 3rd SERVICE Service Request Service

Current Word Count Register - Each channel has a 16-Bit Current Word Count register. This register determines the number of transfers to be performed. The actual number of transfers will be one more than the number programmed in the Current Word Count register (i.e., programming a count of 100 will result in 101 transfers). The word count is decremented after each transfer. When the value in the register goes from zero to FFFFH, a TC will be generated. This register is loaded or read in successive 8-bit bytes by the microprocessor in the Program Condition. See Figure 6 for programming information. Following the end of a DMA service it may also be reinitialized by an Autoinitialization back to its original value. Autoinitialization can occur only when an EOP occurs. If it is not Autoinitialized, this register will have a count of FFFFH after TC. Base Address and Base Word Count Registers - Each Channel has a pair of Base Address and Base Word Count registers. These 16-bit registers store the original value of their associated current registers. During Autoinitialize these values are used to restore the current registers to their original values. The base registers are written simulta- neously with their corresponding current register in 8-bit bytes in the Program Condition by the microprocessor. See Figure 6 for programming information. These registers can- not be read by the microprocessor. Command Register - This 8-bit register controls the opera- tion of the 82C237. It is programmed by the microprocessor and is cleared by RESET or a Master Clear instruction. The following diagram lists the function of the Command register bits. See Figure 4 for Read and Write addresses. Mode Register - Each channel has a 6-bit Mode register associated with it. When the register is being written to by the microprocessor in the Program condition, bits 0 and 1 determine which channel Mode register is to be written. When the processor reads a Mode register, bits 0 and 1 will both be ones. See the following diagram and Figure 4 for Mode register functions and addresses. Request Register - The 82C237 can respond to requests for DMA service which are initiated by software as well as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request register. These are non-maskable and subject to prioritization by the Priority Encoder network. Each register bit is set or reset separately under software control. The entire register is cleared by a RESET or Master Clear instruction. To set or reset a bit, the software loads the proper form of the data word. See Figure 4 for register address coding, and the following diagram for Request register format. A software request for DMA operation can be made in block or single modes. For memory-to-memory transfers, the software request for channel 0 should be set. When reading the Request register, bits 4-7 will always read as ones, and bits 0-3 will display the request bits of channels 0-3 respectively. Command Register

76543210 BIT NUMBER

X Channel 0 address hold disable Channel 0 address hold enable If bit 0 = 0 Controller enable Controller disable X Normal timing Compressed timing If bit 0 = 1 Fixed priority Rotating priority X Late write selection Extended write selection If bit 3 = 1 DREQ sense active high DREQ sense active low DACK sense active low DACK sense active high Mode Register If bits 6 and 7 = 11 Autoinitialization disable Autoinitialization enable Address increment select Address decrement select Demand mode select Single mode select Block mode select Cascade mode select Mode Register Don’t Care, Write Bits 4-7 All Ones, Read

ister command (see software commands section). 4-7 are cleared upon RESET or Master Clear. ation, unless cleared by a RESET or Master Clear.

1 Channel 0 has reached TC

1 Channel 1 has reached TC

1 Channel 2 has reached TC

1 Channel 3 has reached TC

1 Channel 0 request

1 Channel 1 request

1 Channel 2 request

1 Channel 3 request

FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES

There are special software commands which can be executed by reading or writing to the 82C237. These com- mands do not depend on the specific data pattern on the data bus, but are activated by the I/O operation itself. On read type commands, the data value is not guaranteed. These commands are: Clear First/Last Flip-Flop - This command is executed prior to writing or reading new address or word count information to the 82C237. This command initializes the flip-flop to a known state (low byte first) so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence. Set First/Last Flip-Flop - This command will set the flip-flop to select the high byte first on read and write operations to address and word count registers. Master Clear - This software instruction has the same effect as the hardware RESET. The Command, Status, Request, and Temporary registers, and Internal First/Last Flip-Flop and mode register counter are cleared and the Mask register is set. The 82C237 will enter the idle cycle. Clear Mask Register - This command clears the mask bits of all four channels, enabling them to accept DMA requests. Clear Mode Register Counter - Since only one address location is available for reading the Mode registers, an inter- nal two-bit counter has been included to select Mode regis- ters during read operation. To read the Mode registers, first execute the Clear Mode Register Counter command, then do consecutive reads until the desired channel is read. Read order is channel 0 first, channel 3 last. The lower two bits on all Mode registers will read as ones. ExternalEOP Operation The EOP pin is a bidirectional, open drain pin which may be driven by external signals to terminate DMA operation. Because EOP is an open drain pin an external pull-up resis- tor to VCC is required. The value of the external pull-up resistor used should guarantee a rise time of less than 125ns. It is important to note that the 82C237 will not accept external EOP signals when it is in an SI (Idle) state. The controller must be active to latch EXTEOP . Once latched, the EXT EOP will be acted upon during the next S2 state, unless the 82C237 enters an idle state first. In the latter case, the latched EOP is cleared. ExternalEOP pulses occurring between active DMA transfers in demand mode will not be recognized, since the 82C237 is in an SI state. 16-Bit Transfer Mode The 82C237 is fully software and pin for pin compatible with the 82C37A. Therefore, the 82C237 may be used as a faster 82C37A without modifications to software or hardware. The 82C237 may be used as an 82C37A, however, the 82C237 has an additional feature in that it may be programmed to perform 16-bit DMA transfers, thus doubling data transfer rate. In 16-bit transfer mode the device operates the same as in normal (8-bit) transfer mode with exceptions noted in this section. 16-Bit Transfer Mode Initialization - To initialize the 82C237 to 16-bit Transfer Mode, a specific sequence of soft- ware commands must be written to the device immediately after a hardware RESET or a Master Clear instruction. The sequence to initialize 16-bit Transfer Mode is as follows: 1) Hardware RESET or Master Clear 2) Set First/Last Flip-Flop 3) Clear First/Last Flip-Flop These software commands must occur sequentially with no communication to or from the 82C237 between commands. Once in 16-bit mode, the device will remain in this mode until a hardware RESET or Master Clear sets it back to normal (8-bit) transfer mode. If this initialization sequence is not fol- lowed exactly, the 82C237 will operate exactly like the 82C37A or the 82C237 in normal 8-bit mode. 16-Bit DMA Transfers - In 16-bit transfer mode, each DMA channel may be programmed to perform 8-bit or 16-bit trans- fers. Channels which are programmed to perform 8-bit trans- fers will operate like a normal 82C37A transfer. On channels programmed to perform 16-bit transfers, the Current Address register, which is normally incremented or decre- mented by one after each transfer, is incremented or decre- mented by two after each transfer. Also, the Current Word Count register, which is normally decremented by one after each transfer, is decremented by two after each transfer. 16-Bit Memory-to-Memory Transfers - 16-bit memory-to- memory transfers require an external latch to temporarily store the 8 most significant bits of data. When 16-bit transfer mode is enabled, Pin 5 (DWLE) becomes an active output which may be used to enable the external data latch during memory-to-memory operations. See Figure 9 for a 16-bit DMA application. Channels 0 and 1 operate as memory-to- memory transfer channels. IF either channel 0 or channel 1 is programmed to perform 16-bit transfers when a memory- to-memory transfer is initiated, the transfer will be a 16-bit transfer. If 8-bit memory-to-memory transfers are desired while the 82C237 is in 16-bit transfer mode, channels 0 and 1 must both be programmed for 8-bit transfers. Pin 5 DWLE Output - When the 82C237 is initialized to 16- bit transfer mode, pin 5 is always high impedance three- stated. This insures compatibility with the 82C37A pin 5 description. In 16-bit transfer mode, this output becomes active and serves a dual purpose. During the S1 cycle of a transfer, the DWLE output indicates the data width (0 = 16-bit, 1 = 8-bit) of the active channel. This signal may be used with the A0 output to generate a High Byte Enable signal for use in chip select decode logic. Since DWLE is a multiplexed pin, Data Width information needs to be captured in an external latch on the falling edge of ADSTB. See Figure 9 for a 16-bit DMA application. During memory-to-memory transfer, the DWLE output is used to enable an external latch which temporarily stores the 8 most significant bits of data during the read-from-memory half of the transfer. DWLE enables this byte of data onto the data bus during the write-to-memory half of the transfer. See Figure 9 for a 16-bit DMA application.

If an active channel is cascaded, as defined by its mode reg- ister, DWLE will be driven low at the start of the transfer, and will remain low for the entire transfer. This allows the DWLE signal from the slave 82C237 to control the system. To form the system DWLE signal for cascaded 82C237s, simply “OR” the individual DWLE outputs of the Master and Slaves. Registers Affected by 16-Bit Transfer Mode Current Address Register - Each channel has a 16-bit Cur- rent Address register. This register holds the value of the address used during DMA transfers. On channels pro- grammed to perform 8-bit DMA transfers, the address is automatically incremented or decremented by one after each transfer. On channels programmed for 16-bit DMA transfers, the address is automatically incremented or decre- mented by two after each transfer. During all 16-bit transfers, the A0 output will remain low for the entire transfer, even if an odd address is programmed into the channel’s Current Address register (i.e. only even word addresses will be generated). The Current Address register is written or read by the micro- processor in successive 8-bit bytes. See Figure 6 for pro- gramming information. It may also be reinitialized by an Autoinitialize back to its original value. Autoinitialize takes place only after an EOP . In memory-to-memory mode, the channel 0 Current Address register can be prevented from incrementing or decrementing by setting the address hold bit in the Command register. Current Word Count Register - Each channel has a 16-bit Current Word Count register. This register determines the number of transfers to be performed. On channels pro- grammed for 8-bit transfers, the actual number of transfers will be one more than the number programmed in the Cur- rent Word Count register (i.e. programming a count of 100 will result in 101 transfers). The word count is decremented by one after each transfer on 8-bit transfer channels. On channels programmed for 16-bit transfers, the word count is decremented by two after each transfer. This means that for even values in the Current Word Count register, the actual number of transfers will be n/2 + 1, where n is the value in the Current Word Count register. For odd values in this register, the actual number of transfers will be (n+1)/2. When the value in the Current Word Count register decre- ments past zero (i.e. 0 to FFFEH or 1 to FFFFH), a TC will be generated. This register is loaded or read in successive 8-bit bytes by the microprocessor in the Program Condition. See Figure 6 for programming information. Following the end of a DMA service it may also be reinitialized by an Autoinitialization back to its original value. Autoinitialization can occur only when an EOP occurs. If it is not Autoinitialized, this register will have a count of FFFFH after TC on 8-bit transfers, or FFFEH after TC on 16-bit transfers. Data-Width Register - When 16-bit transfer mode is enabled, the Data-Width register becomes accessible and is used to program each DMA channel to perform either 8-bit transfers or 16-bit transfers. Data bits 4-7 represent DREQ channels 0- 3 respectively and determine the data width (8-bit or 16-bit) of each channel during DMA transfers. When programming this register, bit 3 of the data must be set to “0”. Since the address of the Data-Width register is the same as the Mask register, bit 3 selects which register is actually written. Data-Width Register -16-bit transfer mode enabled Mask Register -In 16-bit transfer mode this register oper- ates the same as the previous Mask register description with the exception of bit 3 when writing the instruction to sepa- rately set or clear a mask bit. Bit 3 of the data must be “1” when writing a single mask bit. Bits 4-7 are ignored when this instruction is written. Refer to the following diagram for writing single mask bits. Mask Register -16-bit transfer mode enabled The software command to write all four bits of the Mask reg- ister has no effect on the state of the Data-Width bits. When reading the Mask/Data-Width register (they share the same address), bits 0-3 will always display the mask bits of channels 0-3, respectively. With 16-bit transfer mode not enabled, bits 4-7 will always read as logical ones. With 16-bit transfer mode enabled, bits 4-7 will display the data-width bits for channels 0-3 respectively. The Mask and Data-Width registers are set by RESET or Master Clear. This disables all hardware DMA requests until a clear mask bit instruction allows them to be recognized. RESET or Master Clear forces the Mask and Data-Width X Don’t Care

0 Must be 0 to write all

Channel 0 = 16-bit transfers Channel 0 = 8-bit transfers Channel 1 = 16-bit transfers Channel 1 = 8-bit transfers Channel 2 = 16-bit transfers Channel 2 = 8-bit transfers Channel 3 = 16-bit transfers Channel 3 = 8-bit transfers

1 Must be 1 to write single

Don’t Care 82C237

not accessible) until 16-bit transfer mode is again entered. of all four channels, enabling them to accept DMA requests.

1. The register to be written is determined by data bit 3.
2. Data-Width bits exist in 82C237, 16-bit mode only.

FIGURE 5. 16-BIT MODE SOFTWARE COMMAND CODES AND REGISTER CODES

0 Base and Current Address Write 0100000 0 A0-A7

1 Base and Current Address Write 0100010 0 A0-A7

2 Base and Current Address Write 0100100 0 A0-A7

3 Base and Current Address Write 0100110 0 A0-A7

FIGURE 6. WORD COUNT AND ADDRESS REGISTER COMMAND CODES

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) oC to +150oC Ceramic Package Plastic Package Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -40oC to +85oC (I82C237) TA = -55oC to +125oC (M82C237) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2 - V C82C237, I82C237 2.2 - V M82C237 VIL Logical Zero Input Voltage - 0.8 V VIHC CLK Input Logical One Voltage V CC -0.8 - V VILC CLK Input Logical Zero Voltage - 0.8 V VOH Output HIGH Voltage 3.0 - V IOH = -2.5mA VCC -0.4 - V IOH = -100 µA VOL Output LOW Voltage - 0.4 V IOL = +2.5mA all output except EOP, IOL = +3.2mA forEOP pin 36 only. II Input Leakage Current -1 +1 µA VIN = GND or V CC , Pins 6, 7, 11-13, 16-19 IO Output Leakage Current -10 +10 µA VOUT = GND or V CC , Pins 1-5, 21-23, 26-30, 32-40 ICCSB Standby Power Supply Current -1 0 µAV CC = 5.5V, VIN = VCC or GND, Outputs Open ICCOP Operating Power Supply Current - 2 mA/MHz V CC = 5.5V, CLK FREQ = Maximum, VIN = VCC or GND, Outputs Open Capacitance TA = +25oC SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 25 pF FREQ = 1MHz, All measurements are referenced to device GND COUT Output Capacitance 40 pF CI/O I/O Capacitance 25 pF

TA = -40oC to +85oC (I82C237), TA = -55oC to +125oC (M82C237) SYMBOL PARAMETER 82C237 82C237-12 UNITSMIN MAX MIN MAX DMA (MASTER) MODE (1)TAEL AEN HIGH from CLK LOW (S1) Delay Time - 105 - 50 ns (2)TAET AEN LOW from CLK HIGH (SI) Delay Time - 80 - 50 ns (3)TAFAB ADR Active to Float Delay from CLK HIGH - 55 - 55 ns (4)TAFC READ or WRITE Float Delay from CLK HIGH - 75 - 50 ns (5)TAFDB DB Active to Float Delay from CLK HIGH - 135 - 90 ns (6)TAHR ADR from READ HIGH Hold Time TCY-75 - TCY-65 - ns (7)TAHS DB from ADSTB LOW Hold Time TCL-18 - TCL-18 - ns (8)TAHW ADR from WRITE HIGH Hold Time TCY-65 - TCY-50 - ns (9)TAK DACK Valid from CLK LOW Delay Time - 105 - 69 ns EOP HIGH from CLK HIGH Delay Time - 105 - 90 ns EOP LOW from CLK HIGH Delay Time - 60 - 35 ns (10)TASM ADR Stable from CLK HIGH - 60 - 50 ns (11)TASS DB to ADSTB LOW Setup Time TCH-20 - TCH-20 - ns (12)TCH CLK HIGH Time (Transitions 10ns) 55 - 30 - ns (13)TCL CLK LOW Time (Transitions 10ns) 43 - 30 - ns (14)TCY CLK Cycle Time 125 - 80 - ns (15)TDCL CLK HIGH to READ or WRITE LOW Delay - 130 - 120 ns (16)TDCTR READ HIGH from CLK HIGH (S4) Delay Time - 115 - 80 ns (17)TDCTW WRITE HIGH from CLK HIGH (S4) Delay Time - 80 - 70 ns (18)TDQ HRQ Valid from CLK HIGH Delay Time - 75 - 30 ns (19)TEPH EOP Hold Time from CLK LOW (S2) 90 - 50 - ns (20)TEPS EOP LOW to CLK LOW Setup Time 25 - 0 - ns (21)TEPW EOP Pulse Width 135 - 50 - ns (22)TFAAB ADR Valid Delay from CLK HIGH - 60 - 50 ns (23)TFAC READ or WRITE Active from CLK HIGH - 90 - 50 ns (24)TFADB DB Valid Delay from CLK HIGH - 60 - 45 ns (25)THS HLDA Valid to CLK HIGH Setup Time 45 - 10 - ns (26)TIDH Input Data from MEMR HIGH Hold Time 0 - 0 - ns (27)TIDS Input Data to MEMR HIGH Setup Time 90 - 45 - ns (28)TODH Output Data from MEMW HIGH Hold Time 15 - TCY-50 - ns (29)TODV Output Data Valid to MEMW HIGH TCY-35 - TCY-10 - ns (30)TQS DREQ to CLK LOW (SI, S4) Setup Time 0 - 0 - ns (31)TRH CLK to READY LOW Hold Time 20 - 10 - ns (32)TRS READY to CLK LOW Setup Time 35 - 15 - ns (33)TCLSH ADSTB HIGH from CLK LOW Delay Time - 70 - 70 ns (34)TCLSL ADSTB LOW from CLK LOW Delay Time - 120 - 60 ns

(35)TWRRD READ HIGH Delay fromWRITE HIGH 0 - 5 - ns (36)TRLRH READ Pulse Width, Normal Timing 2TCY-60 - 2TCY-55 - ns (37)TSHSL ADSTB Pulse Width TCY-50 - TCY-35 - ns (38)TWLWHA Extended WRITE Pulse Width 2TCY-85 - 2TCY-80 - ns (39)TWLWH WRITE Pulse Width TCY-85 - TCY-80 - ns (40)TRLRHC READ Pulse Width, Compressed TCY-60 - TCY-55 - ns (56)TAVRL ADR Valid to READ LOW 17 - 17 - ns (57)TAVWL ADR Valid to WRITE LOW 7 - 7 - ns (58)TRHAL READ HIGH to AEN LOW 15 - 15 - ns (59)TRHSH READ HIGH to ADSTB HIGH 13 - 13 - ns (60)TWHSH WRITE HIGH to ADSTB HIGH 15 - 15 - ns (61)TDVRL DACK Valid to READ LOW 25 - 25 - ns (62)TDVWL DACK Valid to WRITE LOW 25 - 25 - ns (63)TRHDI READ HIGH to DACK Inactive 12 - 12 - ns (64)TAZRL ADR Float to READ LOW -2.5 - -2.5 - ns (65)TOEV Output Enable Valid Before WRITE HIGH TCY+20 - TCY+20 - ns (66)TOEH Output Enable Hold Time from WRITE HIGH TCY-50 - TCY-50 - ns PERIPHERAL (SLAVE) MODE (41)TAR ADR Valid or CS LOW to READ LOW 10 - 0 - ns (42)TAWL ADR Valid to WRITE LOW Setup Time 0 - 0 - ns (43)TCWL CS LOW to WRITE LOW Setup Time 0 - 0 - ns (44)TDW Data Valid to WRITE HIGH Setup Time 100 - 60 - ns (45)TRA ADR or CS Hold fromREAD HIGH 0 - 0 - ns (46)TRDE Data Access from READ - 120 - 80 ns (47)TRDF DB Float Delay from READ HIGH 5 85 5 55 ns (48)TRSTD Power Supply HIGH to RESET LOW Setup Time 500 - 500 - ns (49)TRSTS RESET to First IOR orIOW 2TCY - 2TCY - ns (50)TRSTW RESET Pulse Width 300 - 300 - ns (51)TRW READ Pulse Width 155 - 85 - ns (52)TWA ADR from WRITE HIGH Hold Time 0 - 0 - ns (53)TWC CS HIGH fromWRITE HIGH Hold Time 0 - 0 - ns (54)TWD Data from WRITE HIGH Hold Time 10 - 10 - ns (55)TWWS WRITE Pulse Width 100 - 45 - ns TA = -40oC to +85oC (I82C237), TA = -55oC to +125oC (M82C237) (Continued) SYMBOL PARAMETER 82C237 82C237-12 UNITSMIN MAX MIN MAX

FIGURE 12. DMA TRANSFER and remain low for the entire transfer.

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TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Die Characteristics DIE DIMENSIONS: 148 x 159 x 19 ±1mils METALLIZATION: Type: 51Al Thickness: 8k Å ± 0.75kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å ± 3kÅ WORST CASE CURRENT DENSITY: 0.6 x 105 A/cm2 Metallization Mask Layout 82C237 82C237