AK5351 AKM | Alldatasheet
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ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 1 - AK5351 Enhanced Dual bit DS 20bit ADC GENERAL DESCRIPTION The AK5351 is a 20-bit, 64x oversampling rate(64fs), 2-channel A/D converter for stereo digital systems. The DS modulator in the AK5351 uses the new developed Enhanced Dual bit architecture. This new architecture achieves the wider dynamic range, while keeping much the same superior distortion characteristics as the conventional Single bit way. The AK5351 is suitable for digital surround and Hi-Fi audio application such as Car-audio, MD, etc. Analog inputs of the AK5351 are normally Full-differential inputs, while they are also acceptable Single-ended inputs. The AK5351 is available in a small 24pin VSOP package which will reduce your system space.
FEATURES
Full-differential / Single-ended inputs S/(N+D): 97dB DR, S/N: 103dB Linear phase digital filter Pass band: 0~22kHz(@fs=48kHz) Pass band ripple: ±0.005dB Stop band attenuation: 80dB Digital HPF for DC-offset cancel Master clock: 256fs/384fs Power supply: 5V±10% Small package: 24pinVSOP
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 2 - Ordering Guide AK5351-VF -40~85°C 24pin VSOP AKD5351/2 Evaluation Board Pin Layout Replacement from AK5350 to AK5351 AK5350 AK5351 Package 28VSOP 24VSOP *)Interchangeable with AK5350 Analog Inputs Voltage ±3.47Vp-p ±2.10Vp-p *)Acceptable Single-ended fc of HPF(@fs=48kHz) 7Hz 1Hz SCLK ~64fs ~128fs
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 3 - PIN/FUNCTION No. Pin Name I/O FUNCTION
1 AINR+ I Right channel analog positive input pin
2 AINR- I Right channel analog negative input pin
3 VREF O Voltage Reference output pin (VA-2.6V) Normally connected to VA with a 0.1uF ceramic capacitor in parallel with a 10uF electrolytic capacitor.
4 VA - Analog section Analog Power Supply, +5V
5 AGND - Analog section Analog Ground
6 AINL+ I Left channel analog positive input pin
7 AINL- I Left channel analog negative input pin
T est pin (Pull-down pin) Should be left floating.
9 HPFE I High Pass Filter Enable pin (Pull-up pin)
"H": ON "L": OFF
12 VD - Digital section Digital Power Supply pin, +5V
13 DGND - Digital section Digital Ground pin
16 PD I Power Down pin
"L" brings the device into power-down mode. Must be done once after power-on.
17 MCLK I Master Clock input pin
CMODE="H":384fs CMODE="L":256fs
18 SCLK I/O Serial Data Clock pin
Data is clocked out at the falling edge of SCLK. Slave mode: 64fs clock is input usually. Master mode: SCLK outputs a 64fs clock. SCLK stays low during the power-down mode(PD="L").
19 LRCK I/O L/R Channel Clock Select pin
Slave mode: An fs clock is fed to this LRCK pin. Master mode: LRCK output an fs clock. LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset when SMODE1 "H".
20 FSYNC I/O Frame Synchronization Signal pin
Slave mode: When "H", data bits are clocked out on SDA TA. As I S slave mode ignores FSYNC, it should hold "L" or "H". Master mode: FSYNC outputs 2fs clock. Stay low during the power-down mode(PD="L").
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 4 -
21 SDA TA O Serial Data Output pin
Data are output with MSB first, in 2's complement format. After 20 bits are output it turns to "L". It also remains "L" at a power-down mode(PD="L").
22 CMODE I Master Clock Selection pin
"L": MCLK=256fs "H": MCLK=384fs SMODE1 SMODE2 I I Serial Interface Mode Select pin Defines the directions of LRCK, SCLK and FSYNC pins and Output Data Format. SMODE2 is pull-down pin. SMODE1 SMODE2 MODE LRCK L L Slave mode: MSB justified : H/L H L Master mode: Similar to I S : H/L L H Slave mode: I S : L/H H H Master mode: I S : L/H
24 VB - Substrate Power Supply, +5V
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 5 - ABSOLUTE MAXIMUM RATINGS (AGND,DGND=0V; Note 1 ) Parameter Symbol min max Units DC Power Supply:Analog Power(VA pin) Digital Power(VD pin) (Note 2 ) Substrate Power(VB pin) VA VD VB -0.3 -0.3 -0.3 6.0 6.0/VB+0.3 6.0 V V Input Current (Any pin except supplies) IIN - ±10 mA Analog Input Voltage AINL+,AINL-,AINR+,AINR-pins (Note 2 ) VINA -0.3 6.0/VA+0.3 V Digital Input Voltage (Note 2 ) VIND -0.3 6.0/VB+0.3 V Ambient Temperature T a -40 85 °C Storage Temperature Tstg -65 150 °C Note 1 : All voltage with respect to ground. Note 2 : Absolute maximum value is the highest voltage in 6.0V , VA+0.3V and VB+0.3V . WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND,DGND=0V; Note 1 ) Parameter Symbol min typ max Units DC Power Supplies: Analog Power Digital Power(VD pin) (VB pin) (Note 3 ) VA VD VB 4.50 4.50 4.50 5.0 5.0 5.0 5.50 VB 5.50 V V V Note 1 : All voltages with respect to ground. Note 3 : The VA and VB are connected together through the chip substrate and have several ohms resistance. The VA and VB should be powered at the same time or earlier than VD. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 6 - ANALOG CHARACTERISTICS (T a=25°C; VA,VD,VB=5.0V; fs=48kHz; 20bit; Input signal frequency=1kHz, Measurement Bandwidth=10Hz~20kHz; unless otherwise specified.) Parameter min typ max Units Resolution 20 Bits Analog Input Characteristics (Analog source impedance: 330W ) S/(N+D) (Note 4 ) 88 97 dB Dynamic Range (A-weighted) (Note 5 ) 97 103 dB S/N (A-weighted) (Note 6 ) 97 103 dB Interchannel Isolation (f=1kHz) 100 120 dB Interchannel Gain Mismatch 0.1 0.3 dB Gain drift ±200 ppm/°C Input Voltage Range ±1.97 ±2.10 ±2.23 Vp-p Input Impedance 30 50 kW Power Supplies Power Supply Current (Note 7 ) Normal Operation (PD="H") VA+VB VD Power-Down mode (PD="L") VA+VB VD mA mA uA uA Power Consumption (Note 7 ) Normal Operation Power-Down mode 105 150 170 mW uW Power Supply Rejection Ratio 50 dB Note 4 : The ratio of the rms value of the signal to the sum of all other spectral components up to 20kHz except for the signal (included harmonic component, excluded DC component, analog input signal is -0.5dB). Inversed of THD+N. Note 5 : S/(N+D) with an input signal of 60dB below full-scale. Note 6 : When using only 20kHzLPF , S/N and DR are 99dB(typ.). When using CCIR-ARM filter, S/N is 99dB(typ.) Note 7 : Almost no current is supplied from VB pin.
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 7 - DIGITAL FILTER CHARACTERISTICS (T a=25°C; VA,VD,VB=5.0V±10%; fs=48kHz) Low Pass Filter characteristics Symbol min typ max Units Passband -0.005dB (Note 8 ) -0.02dB -0.06dB PB 0 21.5 21.768 22.0 kHz Stopband (Note 9 ) SB 26.5 kHz Passband Ripple (Note 10 ) PR ±0.005 dB Stopband Attenuation (Note 9 ,Note 11 ) SR 80 dB Group Delay Distortion D GD 0u s Group Delay (Note 12 ) GD 29.3 1/fs High Pass Filter characteristics Frequency Response -3dB(Note 8 ) -0.5dB -0.1dB FR 1.0 2.9 6.5 Hz Hz Hz Note 8 : These frequencies scale with the sampling frequency(fs). Note 9 : Stopband is 26.5kHz to 3.0455MHz at fs=48kHz. Note 10 : Passband is DC to 21.5kHz at fs=48kHz. Note 11 : The analog modulator samples the input at 3.072MHz for a system sampling rate of fs=48kHz. These is no rejection of input signals at those bandwidths which are multiples of the sampling frequency (n x 3.072MHz ±22kHz ;n=0,1,2,3…). Note 12 : The calculation delay time occurred by digital filtering. This is the time from the input of analog signal to setting the 20bit data of both channels to the output registers. GD=29.3/fs.
ELECTRICAL CHARACTERISTICS
Digital Characteristics (T a=25°C; VA,VD,VB=5.0V±10%) Parameter Symbol min typ max Units High-Level Input voltage Low-Level Input voltage VIH VIL 70%VD 30%VD V V High-Level Output voltage Iout=-20uA Low-Level Output voltage Iout=20uA VOH VOL VD-0.1 0.1 V V Input Leakage Current (Note 13 ) Iin - - ±10 uA Note 13 : Except for pull-down and pull-up pins. TST1, TST2, TST3, TST4, SMODE2 pins have internal pull-down device, HPFE pin has internal pull-up devive(T yp. 50kW )
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 8 - SWITCHING CHARACTERISTICS (T a=25°C; VA,VD,VB=5.0V±10%; CL=20pF) Parameter Symbol min typ max Unit Control Clock Frequency Master Clock 256fs: Pulse width Low Pulse width High 384fs: Pulse width Low Pulse width High Serial Data Output Clock Channel Select Clock(Sampling Frequency) Duty Cycle f CLK tCLKL tCLKH fCLK tCLKL tCLKH fSLK fs 2.048 30.0 30.0 3.072 20.0 20.0 12.288 18.432 3.072 13.824 20.736 6.912 MHz ns ns MHz ns ns MHz kHz Serial Interface Timing (Note 14 ) Slave Mode(SMODE1="L") SCLK Period SCLK Pulse width Low Pulse width High SCLK Rising to LRCK Edge (Note 15 ) LRCK Edge to SCLK Rising (Note 15 ) LRCK Edge to SDA TA MSB Valid SCLK Falling to SDA TA Valid SCLK Rising to FSYNC Edge(Note 15 ) FSYNC Edge to SCLK Rising(Note 15 ) Master Mode(SMODE1="H") SCLK Frequency Duty Cycle FSYNC Frequency Duty Cycle SCLK Falling to LRCK Edge LRCK Edge to FSYNC Rising SCLK Falling to SDA TA Valid SCLK Falling to FSYNC Edge t SLK tSLKL tSLKH tSHLR tLRSH tDLR tDSS tSHF tFSH fSLK fFSYNC tSLR tLRF tDSS tSF 144.7 -20 -20 64fs 2fs ns ns ns ns ns ns ns ns ns Hz Hz ns tslk ns ns Power down timing PD Pulse width PD Rising to SDA TA Valid (Note 16 ) tPDW tPDV 150 516 ns 1/fs Note 14 : Refer to Serial Data Interface. Note 15 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK. Note 16 : The number of LRCK rising edges after PD brought high. The value is in master mode. In slave mode it becomes one LRCK clock(1/fs) longer.
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 9 - Timing Chart
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 10 - OPERATION OVERVIEW System clock In slave mode, MCLK(256fs/384fs), LRCK(fs) and SCLK(64fs) are required for AK5351. Use a signal divided from the MCLK for LRCK. In master mode, only MCLK is needed. A LRCK clock rate meets standard audio rates (32kHz, 44.1kHz, 48kHz). In slave mode, the MCLK should be synchronized with LRCK but the phase is free of care. The AK5351 includes the phase detect circuit for LRCK clock, the AK5351 is reset automatically when the synchronization is out of phase by changing the clock frequencies. (Please refer to the "Asynchronization - reset."). When changing sampling frequency(fs) after power-up, AK5351 should be reset. During the operation (PD="H") following external clocks should never be stopped : CLK in master mode and MCLK, SCLK and LRCK in slave mode. When the clocks stop there is a possibility that the device comes into a malfunction because of over currents in the dynamic logic. If the external clocks are not present, the AK5351 should be in the power-down mode. (PD="L") Master Clock (MCLK) fs 256fs 384fs SCLK(64fs) 32.0kHz 8.1920MHz 12.2880MHz 2.0480MHz 44.1kHz 11.2896MHz 16.9344MHz 2.8224MHz 48.0kHz 12.2880MHz 18.4320MHz 3.0720MHz T able 1 . System Clock Clock Circuit CMODE MCLK L 256fs H 384fs AK5351 has an internal divider as shown in the above figure. The device can interface either or an external MCLK(256fs or 384fs) by controlling CMODE pin.
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 12 -
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 13 - Power-down mode The AK5351 has to be reset once by bringing PD "L" upon power-up. All internal registers of the digital filter and so on in the AK5351 are reset by this operation. When exiting the power-down mode(PD="H"), the internal timing starts clocking by first MCLK "›"(rising edge). In master mode internal counter starts at once, in slave mode internal counter starts after synchronizing with the first rising edge of LRCK. The serial output data is available after 516 counting clock of LRCK cycle. Asynchronization-reset In slave mode, if the phase difference between LRCK and internal control signals is larger than +1/16~-1/16 of word period(1/fs), the synchronization of internal control signals with LRCK is done automatically at the first rising edge of LRCK. High Pass Filter(HPFE pin) The AK5351 has a Digital High Pass Filter(HPF) for DC-offset cancel. When HPFE pin goes "H", HPF is enabled. The cut-off frequency of the HPF is 1Hz(@fs=48kHz). It also scales with the sampling frequency(fs). The HPF can be disabled by bringing HPFE pin "L". In this case, the AK5351 has the DC-offset of a few mV .
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 16 - Digital Connections T o minimize digital originated noise, connect the ADC digital outputs only to CMOS inputs. Logic families of 4000B, 74HC, 74AC, 74ACT and 74HCT series are suitable. Multiple AK5351 In systems where multiple ADC's are required, care must be taken to insure the internal clocks are synchronized between converters to make simultaneous sampling. In slave mode, synchronous sampling is achieved by supplying the same MCLK and LRCK to all converters. In master mode, the same PD signal is supplied to each ADC. The PD state is released at the first rising edge of MCLK after bringing PD into high. Hence, if the rising edge of PD and rising edge of MCLK coincides together the sampling difference among the ADC's modulator would occur. The difference could be 1/256fs in the sampling clock(64fs) of the modulator, typically 81ns at fs=48kHz.
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 17 - PACKAGE zzzz 24pin VSOP (Unit: mm) Material & Lead finish Package: Epoxy Lead-frame: Copper Lead-finish: Soldering plate
ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 18 - MARKING Contents of AAXXXX AA: Lot# XXXX: Date Code
zThese products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. zAKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. zAny export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. zAKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. zIt is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.