AK4368EG AKM | Alldatasheet
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ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 1 - GENERAL DESCRIPTION The AK4368 is 24-bit DAC with an integrated PLL and headphone amplifier. The PLL input frequency is synchronized to typical mobile phone clock frequencies. The AK4368 features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The AK4368 includes a 3-D stereo enhancement circuit that operates with both the headphone amplifier and the stereo lineout. The integrated headphone amplifier features “pop-free” power-on/off, a mute control, and it delivers 50mW of power into 16Ω. The AK4368 is packaged in a 41-pin BGA package, deal for portable applications. FEATURE Multi-bit ∆Σ DAC Sampling Rate - 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz On chip perfect filtering 8 times FIR interpolator - Passband: 20kHz - Passband Ripple: ±0.02dB - Stopband Attenuation: 54dB Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz PLL: - Input Frequency: 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz, 14.4MHz, 13MHz, 12MHz and 11.2896MHz - Input Level: AC Couple Input Available Audio I/F Format: MSB First, 2’s Compliment - I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified - Master/Slave Mode Mixing: LR, LL, RR, (L+R)/2 Digital ALC Digital ATT Analog Mixing Circuit 3D Stereo Enhancement Stereo Lineout µP Interface: 3-wire/I2C Bass Boost Function Headphone Amplifier - Output Power: 50mW x 2ch @16Ω, 3.3V - S/N: 92dB@3.3V - Pop Noise Free at Power-ON/OFF and Mute Power Supply: 1.6V ∼ 3.6V Power Supply Current: 4.0mA @2.4V (HP-AMP no output) Ta: −30 ∼ 85°C Small Package: 41pin BGA (4mm x 4mm, 0.5mm pitch) DAC with built-in PLL & HP-AMP AK4368EG
Figure 1. Block Diagram
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 3 - Ordering Information AK4368EG −30 ∼ +85°C 41pin BGA (0.5mm pitch) AKD4368 Evaluation board for AK4368 Pin Layout A Top View BC E DF G AK4368EG
7 NC HPR HVDD AVDD VCOM LOUT NC
6 HPL HVSS AVSS MUTET ROUT 3DCAP2 3DCAP3
5 MIN NC NC 3DCAP1
4 RIN NC Top
3 VCOC LIN NC NC CAD0/
2 PVDD PVSS DVSS I2C LRCK SDATA SCL/
1 NC MCKO DVDD MCKI BICK SDA/
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 4 - Comparison with AK4365 and AK4367 Parameter AK4365 AK4367 AK4368 PLL Input Frequency 19.8/19.68/19.2/15.36/ 14.4/13/12/11.2896MHz N/A MHz Sampling Frequency at PLL mode 2/44.1/48kHz Audio I/F Format 20bit Right justified 16/20bit Left justified I2S 24bit Right justified 16/20/24bit Left justified I2S Å Master mode Available N/A Available ALC N/A N/A Available 3D Stereo Enhancement N/A N/A Available Line Output Mono Mono Stereo µP I/F 3-wire 3-wire/I 2C Å Bass Boost +6dB +16dB Å Mixing (L+R)/2 (L+R)/2 LL, RR, (L+R)/2 HP-Amp Output Power 10mW 50mW 50mW Package 28QFN(5.2mm x 5.2mm) 20QFN(4.2mm x 4.2mm) 41BGA(4mm x 4mm)
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 5 - PIN/FUNCTION No. Pin Name I/O Function B1 MCKO O Master Clock Output C2 DVSS - Digital Ground C1 DVDD - Digital Power Supply D2 I2C I Control Mode Select “H”: I2C Bus, “L”: 3-wire Serial D1 MCKI I Master Clock Input E2 LRCK I/O L/R Clock This clock determines which audio channel is currently being input on SDATA pin. E1 BICK I/O Serial Bit Clock This clock is used to latch audio data. F2 SDATA I Audio Serial Data Input SDA I/O Control Data Input/Output (I2C pin = “H”) F1 CDTI I Control Data Input (I2C pin = “L”) SCL I Control Data Clock (I2C pin = “H”) G2 CCLK I Control Data Clock (I2C pin = “L”) CAD0 I Chip Address 0 Select (I2C pin = “H”) G3 CSN I Control Data Chip Select (I2C pin = “L”) F4 PDN I Power-down & Reset When “L”, the AK4368 is in power-down mode and is held in reset. The AK4368 should always be reset upon power-up. G5 3DCAP1 O Capacitor Connect Pin 1 for 3D Stereo Enhancement Connected to 3DCAP2 pin with 4.7nF capacitor in series. F6 3DCAP2 O Capacitor Connect Pin 2 for 3D Stereo Enhancement Connected to 3DCAP1 pin with 4.7nF capacitor in series and connected to 3DCAP3 pin with 470nF capacitor in series. G6 3DCAP3 O Capacitor Connect Pin 1 for 3D Stereo Enhancement Connected to 3DCAP2 pin with 470nF capacitor in series. F7 LOUT O Lch Analog Output E6 ROUT O Rch Analog Output E7 VCOM O Common Voltage Output Normally connected to AVSS pin with a 2.2µF electrolytic capacitor. D7 AVDD - Analog Power Supply C6 AVSS - Analog Ground D6 MUTET O Mute Time Constant Control Connected to AVSS pin with a capacitor for mute time constant. C7 HVDD - Power Supply Pin for Headphone Amp B6 HVSS - Ground for Headphone Amp B7 HPR O Rch Headphone Amp Output A6 HPL O Lch Headphone Amp Output A5 MIN I Mono Analog Input A4 RIN I Rch Analog Input B3 LIN I Lch Analog Input A3 VCOC O Output for Loop Filter of PLL Circuit This pin should be connected to AVSS with one resistor and one capacitor in series. B2 PVSS - Ground for PLL. Connected to AVSS. A2 PVDD - Power Supply for PLL. Normally connected to AVDD.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 6 - No. Pin Name I/O Function NC - No Connect Pin No internal bonding. These pins should be connected to ground or open. Note: All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not be left floating. Note: MCKI pin can be left floating only when PDN pin = “L”. Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Setting Analog LOUT, ROUT, MUTET, HPR, HPL, MIN, RIN, LIN These pins should be open. Digital CAD0 This pin should be connected to DVSS. MCKO This pin should be open.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 7 - ABSOLUATE MAXIMUM RATING (AVSS, DVSS, HVSS, PVSS=0V; Note 1) Parameter Symbol Min max Units Power Supplies Analog AVDD −0.3 4.6 V Digital DVDD −0.3 4.6 V PLL PVDD −0.3 4.6 V HP-Amp HVDD −0.3 4.6 V |AVSS – DVSS| (Note 2) ∆GND1 - 0.3 V |AVSS – HVSS| (Note 2) ∆GND2 - 0.3 V |AVSS – PVSS| (Note 2) ∆GND3 - 0.3 V Input Current (any pins except for supplies) IIN - ±10 mA Analog Input Voltage (Note 3) VINA −0.3 AVDD+0.3 or 4.6 V Digital Input Voltage (Note 4) VIND −0.3 DVDD+0.3 or 4.6 V Ambient Temperature Ta −30 85 °C Storage Temperature Tstg −65 150 °C Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS, HVSS and PVSS must be connected to the same analog ground plane. Note 3. MIN, LIN and RIN pins. Note 4. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN and I2C pins. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMEND OPERATING CONDITIONS (AVSS, DVSS, HVSS, PVSS=0V; Note 1) Parameter Symbol min typ Max Units Power Supplies Analog AVDD 1.6 2.4 3.6 V Digital DVDD 1.6 2.4 AVDD V PLL PVDD 1.6 2.4 3.6 V HP-Amp HVDD 1.6 2.4 3.6 V Difference1 AVDD−PVDD −0.3 0 +0.3 V Difference2 AVDD−HVDD −0.3 0 +0.3 V Note 1. All voltages with respect to ground. * AKM assumes no responsibility for usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 8 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD=PVDD=DVDD=HVDD=2.4V, AVSS=PVSS=DVSS=HVSS=0V; fs=44.1kHz; EXT mode; BOOST OFF; Slave Mode; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; Headphone-Amp: Load impedance is a serial connection with RL =16Ω and CL=220µF. (Refer to Figure 48); unless otherwise specified) Parameter min typ Max Units DAC Resolution - - 24 bit Headphone-Amp: (HPL/HPR pins) (Note 5) Analog Output Characteristics THD+N −3dBFS Output, 2.4V, Po=10mW@16Ω - −50 −40 dB −4.8dBFS Output, 3.3V, Po=50mW@16Ω HPG bit=”1” - −20 - dB −60dBFS Output, A-weighted 82 90 - dB D-Range −60dBFS Output, A-weighted, 3.3V - 92 - dB A-weighted, 2.4V 82 90 - dB S/N A-weighted, 3.3V - 92 - dB Interchannel Isolation 60 80 - dB DC Accuracy Interchannel Gain Mismatch - 0.3 0.5 dB Gain Drift - 200 - ppm/°C Load Resistance (Note 6) 16 - - Ω Load Capacitance - - 300 pF −3dBFS Output (Note 7) 1.01 1.13 1.25 Vpp Output Voltage −4.8dBFS Output, 3.3V, Po=50mW@16Ω HPG bit=”1” - 0.89 - Vrms Stereo Line Output: (LOUT/ROUT pins, RL=10kΩ) (Note 8) Analog Output Characteristics: THD+N 0dBFS Output - −60 −50 dB S/N A-weighted 80 87 - dB DC Accuracy Gain Drift - 200 - ppm/°C Load Resistance (Note 6) 10 - - kΩ Load Capacitance - - 25 pF Output Voltage 0dBFS Output (Note 9) 1.32 1.47 1.61 Vpp Output Volume: (LOUT/ROUT pins) Step Size 1 2 3 dB Gain Control Range −30 - 0 dB Note 5. DACHL=DACHR bits = “1”, MINHL=MINHR=LINHL=RINHR bits = “0”. Note 6. AC load. Note 7. Output voltage is proportional to AVDD voltage. Vout = 0.47 x AVDD(typ)@−3dBFS. Note 8. DACL=DACR bits = “1”, MINL=MINR=LINL=RINR bits = “0”. Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.61 x AVDD(typ)@0dBFS.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 9 - Parameter min typ max Units LINEIN: (LIN/RIN/MIN pins) Analog Input Characteristics Input Resistance (See Figure 23, Figure 24.) LIN pin LINHL bit = “1”, LINL bit = “1” 35 50 - kΩ LINHL bit = “1”, LINL bit = “0” - 100 - kΩ LINHL bit = “0”, LINL bit = “1” - 100 - kΩ RIN pin RINHR bit = “1”, RINR bit = “1” 35 50 - kΩ RINHR bit = “1”, RINR bit = “0” - 100 - kΩ RINHR bit = “0”, RINR bit = “1” - 100 - kΩ MIN pin MINHL=MINHR=MINL=MINR bits = “1” 17 25 - kΩ MINHL bit = “1”, MINHR=MINL=MINR bits = “0” - 100 - kΩ MINHR bit = “1”, MINHL=MINL=MINR bits = “0” - 100 - kΩ MINL bit = “1”, MINHL=MINHR=MINR bits = “0” - 100 - kΩ MINR bit = “1”, MINHL=MINHR=MINL bits = “0” - 100 - kΩ Gain LIN/MIN→LOUT, RIN/MINÆROUT −1 0 +1 dB LIN/MIN→HPL, RIN/MINÆHPR −0.24 +0.76 +1.76 dB Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) (Note 10) AVDD+PVDD+DVDD - 3.8 5.5 mA HVDD - 1.2 2.5 mA Power-Down Mode (PDN pin = “L”) (Note 11) - 1 100 µA Note 10. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, MCKO bit = “0” and HP-Amp output is off. When PMDAC=PMHPL=PMHPR bits = “1” and PMLO bit= “0”, total power supply current (AVDD+PVDD+DVDD+HVDD) is 4.0mA. Note 11. All digital input pins including clock pins (MCKI, BICK and LRCK) are held at DVSS.
Note 13. The passband and stopband frequencies scale with fs. data of both channels to the input registers to the output of the analog signal. Note 17. These frequency responses scale with fs. If high-level signal is input, the output clips at low frequency. Figure 2. Boost Frequency (fs=44.1kHz)
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 11 - DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V) Parameter Symbol Min typ max Units High-Level Input Voltage 2.2V ≤DVDD≤3.6V VIH 70 %DVDD - - V 1.6V ≤DVDD<2.2V VIH 80 %DVDD - - V Low-Level Input Voltage 2.2V ≤DVDD≤3.6V VIL - - 30 %DVDD V 1.6V ≤DVDD<2.2V VIL - - 20 %DVDD V Input Voltage at AC Coupling (Note 18) VAC 0.4 - - Vpp High-Level Output Voltage (Iout=−200µA) VOH DVDD−0.2 - - V Low-Level Output Voltage (Except SDA pin: Iout=200µA) VOL - - 0.2 V (SDA pin: Iout=3mA) VOL - - 0.4 V Input Leakage Current Iin - - ±10 µA Note 18. Only MCKI pin. (Figure 48)
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 12 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified) Parameter Symbol min typ max Units Master Clock Input Timing Frequency (PLL mode) fCLK 11.2896 - 27 MHz (EXT mode) fCLK 2.048 - 12.288 MHz Pulse Width Low (Note 19) tCLKL 0.4/fCLK - - ns Pulse Width High (Note 19) tCLKH 0.4/fCLK - - ns AC Pulse Width (Note 20) tACW 18.5 - - ns LRCK Timing Frequency fs 8 44.1 48 kHz Duty Cycle: Slave Mode Duty 45 - 55 % Master Mode Duty - 50 - % MCKO Output Timing (PLL mode) Frequency fCLKO 0.256 - 12.288 MHz Duty Cycle (Except fs=32kHz, PS1-0= “00”) dMCK 40 - 60 % (fs=32kHz, PS1-0= “00”) dMCK - 33 - % Serial Interface Timing (Note 21) Slave Mode (M/S bit = “0”): BICK Period tBCK 312.5 - - ns BICK Pulse Width Low tBCKL 100 - - ns Pulse Width High tBCKH 100 - - ns LRCK Edge to BICK “↑” (Note 22) tLRB 50 - - ns BICK “↑” to LRCK Edge (Note 22) tBLR 50 - - ns SDATA Hold Time tSDH 50 - - ns SDATA Setup Time tSDS 50 - - ns Master Mode (M/S bit = “1”): BICK Frequency (BF bit = “1”) fBCK - 64fs - Hz (BF bit = “0”) fBCK - 32fs - Hz BICK Duty dBCK - 50 - % BICK “↓” to LRCK tMBLR −50 - 50 ns SDATA Hold Time tSDH 50 - - ns SDATA Setup Time tSDS 50 - - ns Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 - - ns CCLK Pulse Width Low tCCKL 80 - - ns Pulse Width High tCCKH 80 - - ns CDTI Setup Time tCDS 40 - - ns CDTI Hold Time tCDH 40 - - ns CSN “H” Time tCSW 150 - - ns CSN “↑” to CCLK “↑” tCSS 50 - - ns CCLK “↑” to CSN “↑” tCSH 50 - - ns Note 19. Except AC coupling. Note 20. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground. (Refer to Figure 3.) Note 21. Refer to “Serial Data Interface”. Note 22. BICK rising edge must not occur at the same time as LRCK edge.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 13 - Parameter Symbol min typ max Units Control Interface Timing (I2C Bus mode): (Note 23) SCL Clock Frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - µs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - µs Clock Low Time tLOW 1.3 - - µs Clock High Time tHIGH 0.6 - µs Setup Time for Repeated Start Condition tSU:STA 0.6 - - µs SDA Hold Time from SCL Falling (Note 24) tHD:DAT 0 - - µs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - µs Rise Time of Both SDA and SCL Lines tR - - 0.3 µs Fall Time of Both SDA and SCL Lines tF - - 0.3 µs Setup Time for Stop Condition tSU:STO 0.6 - - µs Capacitive Load on Bus Cb - - 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 ns Power-down & Reset Timing PDN Pulse Width (Note 25) tPD 150 - - ns Note 23. I2C is a registered trademark of Philips Semiconductors. Note 24. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 25. The AK4368 can be reset by bringing PDN pin = “L” to “H” only upon power up.
mode. After exiting the reset state, the AK4368 goes to master mode by changing the M/S bit to “1”. Figure 11. PLL Master Mode When the AK4368 is used in the master mode, LRCK and BICK pins are in a floating state until the M/S bit becomes “1”. MCKO bit = “0”, MCKO pin outputs “L”. After the PLL is locked, LRCK and BICK start to output the clocks (Table 4).
Figure 12. PLL Slave Mode Note 26. Type 1-4 frequency is indicated in Table 2. Table 1. MCKI Input Frequency (PLL mode)
Table 2. Sampling Frequency (PLL mode) Table 3. MCKO frequency (PLL mode, MCKO bit = “1”) Table 4. Clock Operation in Master mode (PLL mode) Table 5. Clock Operation in Slave mode (PLL mode)
Table 6. Relationship between Sampling Frequency and MCKI Frequency (EXT mode) Table 7. MCKO frequency (EXT mode, MCKO bit = “1”) Table 8. Clock Operation in Master mode (EXT mode) Table 9. Clock Operation in Slave mode (EXT mode) frequency for MCKI. Table 10 shows DR and S/N when the DAC output is to the HP-amp. Table 10. Relationship between MCKI frequency and DR (and S/N) of HP-amp (2.4V)
of ALC block is fixed to 0dB. ALC limiter and recovery operation (Table 12). Then the volume is set to the same value for both channels. Table 12. ALC Recovery Operation Waiting Period, Zero Crossing Timeout Period Table 13. ALC Limiter ATT Step
The ALC recovery operation waits for the ROTM1-0 bits (Table 12) to be set after completing the ALC limiter operation. the ALC recovery operation waits until ROTM1-0 period and the next recovery operation is executed. exceeds the ALC limiter detection level (−6.0dBFS). the wait timer of the ALC recovery operation starts. faster than a normal recovery operation. Table 14. ALC Recovery GAIN Step Table 15. Reference Level for ALC Recovery operation
Table 16. Example of the ALC setting operation is finished by ALC bit = “0” or PMDAC bits = “0”.
- LMAT1-0, ROTM1-0, RATT, REF7-0 Note: WR: Write ALC = OFF WR (REF7-0) WR (LMAT1-0, RATT , ROTM1-0; ALC= “1”) Example: Recovery Cycle = 46ms@44.1kHz Limiter and Recovery Step = 1 Maximum Gain = +18dB ALC bit = “1” (1) Addr=0AH, Data=C1H (2) Addr=0BH, Data=30H ALC Operation
Figure 19. Registers set-up sequence at ALC operation
the left channel level and ATTR7-0 bits control the right channel level. Table 17. Digital Volume ATT values fade to their current value. The digital attenuator is independent of the soft mute function. Table 18. Transition time between set values of ATT7-0 bits
signal source without stopping the signal transmission. Figure 20. Soft Mute Function (2) The analog output corresponding to the digital input has a group delay, GD. and it is returned to the ATT level by the same cycle.
frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 19). Table 19. De-emphasis Filter Frequency Select Table 20. Low Frequency Boost Select MONO1-0 bits select the digital data mixing for the DAC (Table 21). Table 21. Mixer Setting
The power supply voltage for the headphone-amp is supplied from the HVDD pin and is centered on the MUTET voltage. and the outputs (HPL and HPR pins) go to HVSS. Table 22. Headphone-Amp Rise/Fall Time Rise time up to VCOM/2: tr = 70k x 1µ = 70ms(typ). Fall time down to VCOM/2: tf = 60k x 1µ = 60ms(typ). Figure 21. Power-up/Power-down Timing for the Headphone-Amp (1) Headphone-amp power-up (PMHPL and PMHPR bits = “1”). The outputs are still at HVSS. C(typ) when the capacitor value on MUTET pin is “C”. VCOM/2 is tf = 60k x C(typ) when the capacitor value on MUTET pin is “C”.
Figure 24. Summation circuit for stereo line output (LOG bit = “0”) noise occurs when ATTS3-0 bits are changed.
1 X MUTE Default
Table 24. LOUT/ROUT Volume ATT values (x: Don’t care)
for 50ms after 3D1-0 bits are changed.
- The load capacitance at 3DCAP1, 3DCAP2 and 3DCAP3 pins should be 20pF(max), respectively.
Table 25. 3D Function Power Management Table 26. 3D depth setting Figure 25. 3D Function External Circuit
Figure 26. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z) (1) PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes “H”. can be stopped. The headphone-amp can operate without these clocks. (4) DACHL and DACHR bits should be changed to “1” after the PMDAC bit is changed to “1”. VCOM/2 is tr = 70k x C(typ). When C=1µF, tr = 70ms(typ). VCOM/2 is tf = 60k x C(typ). When C=1µF, tf = 60ms(typ). DACL/DACR bits should be changed to “0” and 3D1-0 bits = “00”. (9) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499 µs@fs=44.1kHz). (10) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (11) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
Figure 27. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z) (1) PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM bit should be changed to “1” after the PDN pin goes “H”. (3) DACL and DACR bits should be changed to “1” after the PMVCM bit is changed to “1”. (4) When the 3D function is used, 3D1-0 bits should be changed to “01” after DACL and DACR bits are changed to “1”. 3D1-0 bits are changed to “01”. can be stopped. The LOUT/ROUT buffer can operate without these clocks. (7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. (8) Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499 µs@fs=44.1kHz). (9) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
Figure 28. Power-up/down sequence of LIN/RIN/MIN and HP-amp (2) PMVCM bit should be changed to “1” after PDN pin goes “H”. (3) LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINHL, MINHL, RINHR or MINHR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.475 x AVDD. and MINHR bits are changed to “1”. external capacitance at VCOM pin is 2.2µF) after LINHL, MINHL, RINHR and MINHR bits are changed to “1”. VCOM/2 is tr = 70k x C(typ). When C=1µF, tr = 70ms(typ). VCOM/2 is tf = 60k x C(typ). When C=1µF, tf = 60ms(typ). MINHL, RINHR and MINHR bits should be changed to “0”.
Figure 29. Power-up/down sequence of LIN/RIN/MIN and LOUT/ROUT (2) PMVCM bit should be changed to “1” after PDN pin goes “H”. (3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINL, MINL, RINR or MINR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.475 x AVDD. MINR bits are changed to “1”. (7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
Figure 30. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z) (1) PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after PDN pin goes “H”. (3) The PLL executes when the system clock is input to MCKI. (4) The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2. (5) Table 1. After the PLL is locked, the MCKO pin outputs the master clock. clocks can be stopped. The headphone-amp can operate without these clocks. (7) DACHL and DACHR bits should be changed to “1” after the PLL is locked. r = 70k x C(typ). When C=1µF, tr = 70ms(typ). VCOM/2 is tf = 60k x C(typ). When C=1µF, tf = 60ms(typ). DACL/DACR bits should be changed to “0” and 3D1-0 bits should be changed to “00”. (12) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499µs@fs=44.1kHz). (13) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (14) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
Figure 31. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z) (1) PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after PDN pin goes “H”. (3) The PLL executes when the system clock is input to MCKI. (4) The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2. (5) Table 1. After the PLL is locked, the MCKO pin outputs the master clock. clocks can be stopped. The LOUT/ROUT buffer can operate without these clocks. (8) When the 3D function is used, 3D1-0 bits should be changed to “01” after DACL and DACR bits are changed to “1”. (9) PMLO bit is changed to “1”. (10) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. (11) Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499µs@fs=44.1kHz). (12) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
Figure 32. Power-up/down sequence of LIN/RIN/MIN and HP-amp (2) PMVCM bit should be changed to “1” after PDN pin goes “H”. (3) LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINHL, MINHL, RINHR or MINHR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.475 x AVDD. external capacitance at VCOM pin is 2.2µF) after LINHL, MINHL, RINHR and MINHR bits are changed to “1”. VCOM/2 is tr = 70k x C(typ). When C=1µF, tr = 70ms(typ). VCOM/2 is tf = 60k x C(typ). When C=1µF, tf = 60ms(typ). MINHL, RINHR and MINHR bits should be changed to “0”.
Figure 33. Power-up/down sequence of LIN/RIN/MIN and LOUT/ROUT (2) PMVCM bit should be changed to “1” after PDN pin goes “H”. (3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINL, MINL, RINR or MINR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.475 x AVDD. (7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 42 - Power-Up/Down Sequence (PLL Master mode) 1) DAC → HP-Amp Power Supply PDN pin M/S, PMVCM, PMPLL, PMDAC, MCKO bits MCKI pin (3) SDTI pin DAC Internal State PD Normal Operation HPL/R pin PMHPL, PMHPR bits (9) ATTL7-0 ATTR7-0 bits 00H(MUTE) FFH(0dB) (11) GD (12) 1061/fs PD Normal Operation 00H(MUTE) FFH(0dB) (11)(12) (9)(10) (11) (12) Don’t care Don’t care (10) (11) (12) 00H(MUTE) Don’t care (13) (1) >150ns (2) >0 PD (8) >2ms(at 3D OFF), >50ms(at 3D ON) MUTEN bit DACHL, DACHR bits (6) >0 (6) >0 3D1-0 bits (when 3D is used) (8) >2ms, or >50ms MCKO pin Don’t care BICK, LRCK pins Don’t care Unstable Unstable Don’t care Unstable (4) ~20ms (5) (4) ~20ms Unstable Unstable Don’t care Unstable Don’t care “L” Unstable Figure 34 Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z) (1) PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDA, MCKO and M/S bits should be changed to “1” after PDN pin goes “H”. (3) The PLL executes when the system clock is input to MCKI. (4) The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2. (5) Table 1. After the PLL is locked, each clock is output from BICK, LRCK and MCKO pins. (6) DACHL and DACHR bits should be changed to “1” after the PLL is locked. (7) When the 3D function is used, 3D1-0 bits should be changed to “10” after DACHL and DACHR bits are changed to “1”. (8) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2µF) after the DACHL and DACHR bits are changed to “1”. When the 3D function is used, PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 50ms after 3D1-0 bits are changed to “10”. (9) Rise time of the headphone -amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is t r = 70k x C(typ). When C=1µF, tr = 70ms(typ). (10) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1µF, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the DACL/DACR bits should be changed to “0” and 3D1-0 bits should be changed to “00”. (11) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499µs@fs=44.1kHz). (12) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (13) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
Figure 35. Power-up/down sequence of DAC and LOUT/ROUT(Don’t care: except Hi-Z) (1) PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits s hould be changed to “1” after PDN pin goes “H”. (3) The PLL executes when the system clock is input to MCKI. (4) The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2. (5) Table 1. After the PLL is locked, each clock is output from BICK, LRCK and MCKO pins. (6) DACL and DACR bits should be changed to “1” after the PLL is locked. (7) When the 3D function is used, 3D1-0 bits should be changed to “01” after DACL and DACR bits are changed to “1”. (8) PMLO bit is changed to “1”. (9) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. (10) Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499µs@fs=44.1kHz). (11) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
Figure 36. Power-up/down sequence of LIN/RIN/MIN and HP-amp (2) PMVCM bit should be changed to “1” after PDN pin goes “H”. (3) LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINHL, MINHL, RINHR or MINHR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.475 x AVDD. external capacitance at VCOM pin is 2.2µF) after LINHL, MINHL, RINHR and MINHR bits are changed to “1”. VCOM/2 is tr = 70k x C(typ). When C=1µF, tr = 70ms(typ). VCOM/2 is tf = 60k x C(typ). When C=1µF, tf = 60ms(typ). MINHL, RINHR and MINHR bits should be changed to “0”.
Figure 37. Power-up/down sequence of LIN/RIN/MIN and LOUT/ROUT (2) PMVCM bit should be changed to “1” after PDN pin goes “H”. (3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINL, MINL, RINR or MINR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.475 x AVDD. (7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
operations, the data is latched after a low-to-high transition of the 16th CCLK. The clock speed of CCLK is 5MHz(max). The value of the internal registers is initialized at PDN pin = “L”. Figure 38. 3-wire Serial Control I/F Timing
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 50 - Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 PMPLL PMLO MUTEN PMHPR PMHPL PMDAC PMVCM 01H PLL Control FS3 FS2 FS1 FS0 PLL3 PLL2 PLL1 PLL0 02H Clock Control 0 0 M/S MCKAC BF PS0 PS1 MCKO 03H Mode Control 0 0 MONO1 MONO0 BCKP LRP DIF2 DIF1 DIF0 04H Mode Control 1 ATS DATTC LMUTE SMUTE BST1 BST0 DEM1 DEM0 05H DAC Lch ATT ATTL7 ATTL6 A TTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0 06H DAC Rch ATT ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0 07H Headphone Out Select 0 HPG MINHR MINHL RINHR LINHL DACHR DACHL 08H Lineout Select 0 LOG MINR MINL RINR LINL DACR DACL 09H Lineout ATT 0 0 0 0 ATTS3 ATTS2 ATTS1 ATTS0 0AH ALC Mode Control 1 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 0BH ALC Mode Control 2 0 0 ALC ROTM1 ROTM0 LMAT1 LMAT0 RATT 0CH 3D Control 0 0 0 0 DP1 DP0 3D1 3D0 All registers inhibit writing at PDN pin = “L”. PDN pin = “L” resets the registers to their default values. For addresses from 0DH to 1FH, data must not be written. Unused bits must contain a “0” value.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 51 - Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 PMPLL PMLO MUTEN PMHPR PMHPL PMDAC PMVCM R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMVCM: Power Management for VCOM Block 0: Power OFF (Default) 1: Power ON PMDAC: Power Management for DAC Blocks 0: Power OFF (Default) 1: Power ON When the PMDAC bit is changed from “0” to “1”, the DAC is powered-up to the current register values (ATT value, sampling rate, etc). PMHPL: Power Management for the left channel of the headphone-amp 0: Power OFF (Default). HPL pin goes to HVSS(0V). 1: Power ON PMHPR: Power Management for the right channel of the headphone-amp 0: Power OFF (Default). HPR pin goes to HVSS(0V). 1: Power ON MUTEN: Headphone Amp Mute Control 0: Mute (Default). HPL and HPR pins go to HVSS(0V). 1: Normal operation. HPL and HPR pins go to 0.475 x AVDD. PMLO: Power Management for Stereo Output 0: Power OFF (Default) LOUT/ROUT pins go to Hi-Z. 1: Power ON PMPLL: Power Management for PLL 0: Power OFF: EXT mode (Default) 1: Power ON: PLL mode Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all blocks are powered-down regardless as setting of this addr ess. In this case, register is initialized to the default value. When PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMPLL and MCKO bits are “0”, all blocks are powered-down. The register values rema in unchanged. Power supply current is 20 µA(typ) in this case. For fully shut down (typ. 1µA), PDN pin should be “L”. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H PLL Control FS3 FS2 FS1 FS0 PLL3 PLL2 PLL1 PLL0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 0 0 0 0 0 FS3-0: Select Sampling Frequency PLL mode: Table 2 EXT mode: Table 6 PLL3-0: Select MCKI Frequency PLL mode: Note 26. Type 1-4 frequency is indicated in Table 2. Table 1 EXT mode: Disable
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 52 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Clock Control 0 0 M/S MCKAC BF PS0 PS1 MCKO R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 MCKO: Control of MCKO signal 0: Disable (Default) 1: Enable PS1-0: MCKO Frequency PLL mode: Table 3 EXT mode: Table 7 BF: BICK Period setting in Master Mode. In slave mode, this bit is ignored. 0: 32fs (Default) 1: 64fs MCKAC: MCKI Input Mode Select 0: CMOS input (Default) 1: AC coupling input M/S: Master/Slave Mode Select 0: Slave mode (Default) 1: Master mode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Mode Control 0 0 MONO1 MONO0 BCKP LRP DIF2 DIF1 DIF0 R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 1 0 DIF2-0: Audio Data Interface Format Select (Table 11) Default: “010” (Mode 2) LRP: LRCK Polarity Select in Slave Mode 0: Normal (Default) 1: Invert BCKP: BICK Polarity Select in Slave Mode 0: Normal (Default) 1: Invert MONO1-0: Mixing Select (Table 21) Default: “00” (LR)
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 53 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Mode Control 1 ATS DATTC LMUTE SMUTE BST1 BST0 DEM1 DEM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 0 0 0 0 1 DEM1-0: De-emphasis Filter Frequency Select (Table 19) Default: “01” (OFF) BST1-0: Low Frequency Boost Function Select (Table 20) Default: “00” (OFF) SMUTE: Soft Mute Control 0: Normal operation (Default) 1: DAC outputs soft-muted LMUTE: Mute control for LOUT/ROUT (Table 24) 0: Normal operation. ATTS3-0 bits control attenuation value. 1: Mute. ATTS3-0 bits are ignored. (Default) DATTC: DAC Digital Attenuator Control Mode Select 0: Independent (Default) 1: Dependent At DATTC bit = “1”, ATTL7 -0 bits control both cha nnel attenuation levels, whil e register values of ATTL7-0 bits are not written to the ATTR7-0 bits. At DATTC bit = “0”, the ATTL7-0 bits control the left channel level and the ATTR7-0 bits control the right channel level. ATS: Digital attenuator transition time setting (Table 18) 0: 1061/fs (Default) 1: 7424/fs Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H DAC Lch ATT ATTL7 ATTL6 A TTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0 06H DAC Rch ATT ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ATTL7-0: Setting of the attenuation value of output signal from DACL (Table 17) ATTR7-0: Setting of the attenuation value of output signal from DACR (Table 17) Default: “00H” (MUTE)
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 54 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Headphone Out Select 0 HPG MINHR MINHL RINHR LINHL DACHR DACHL R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DACHL: DAC left channel output signal is added to the left channel of the headphone-amp. 0: OFF (Default) 1: ON DACHR: DAC right channel output signal is added to the right channel of the headphone-amp. 0: OFF (Default) 1: ON LINHL: Input signal to LIN pin is added to the left channel of the headphone-amp. 0: OFF (Default) 1: ON RINHR: Input signal to RIN pin is added to the right channel of the headphone-amp. 0: OFF (Default) 1: ON MINHL: Input signal to MIN pin is added to the left channel of the headphone-amp. 0: OFF (Default) 1: ON MINHR: Input signal to MIN pin is added to the right channel of the headphone-amp. 0: OFF (Default) 1: ON HPG: DAC Æ HPL/R Gain 0: 0.76dB (Default) 1: +6.76dB
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 55 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Lineout Select 0 LOG MINR MINL RINR LINL DACR DACL R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DACL: DAC left channel output is added to the LOUT buffer amp. 0: OFF (Default) 1: ON DACR: DAC right channel output is added to the ROUT buffer amp. 0: OFF (Default) 1: ON LINL: Input signal to the LIN pin is added to the LOUT buffer amp. 0: OFF (Default) 1: ON RINR: Input signal to the RIN pin is added to the ROUT buffer amp. 0: OFF (Default) 1: ON MINL: Input signal to the MIN pin is added to the LOUT buffer amp. 0: OFF (Default) 1: ON MINR: Input signal to the MIN pin is added to the ROUT buffer amp. 0: OFF (Default) 1: ON LOG: DAC Æ LOUT/ROUT Gain 0: 0dB (Default) 1: +6dB Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H Lineout ATT 0 0 0 0 ATTS3 ATTS2 ATTS1 ATTS0 R/W RD RD RD RD R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ATTS3-0: Analog volume control for LOUT/ROUT (Table 24) Default: LMUTE bit = “1”, ATTS3-0 bits = “0000” (MUTE) Setting of ATTS3-0 bits is enabled at LMUTE bit is “0”.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 56 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH ALC Mode Control 1 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 1 0 0 0 1 REF7-0: Reference Value for ALC Recovery Operation, 0.375dB step, 81 level, Default: “91H” (Table 15) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH ALC Mode Control 2 0 0 ALC ROTM1 ROTM0 LMAT1 LMAT0 RATT R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 0 0 0 RATT: ALC Recovery GAIN Step (Table 14) LMAT1-0: ALC Limiter ATT Step (Table 13) ROTM1-0: ALC Recovery Waiting Period, Limiter/Recovery Operation Zero Crossing Timeout Period (Table 12) ALC: ALC Enable 0: ALC Disable (Default) 1: ALC Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0CH 3D Control 0 0 0 0 DP1 DP0 3D1 3D0 R/W RD RD RD RD R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 3D1-0: 3D Stereo Enhancement Enable (Table 25) Default: “00” (Disable) DP1-0: 3D Depth (Table 26) Default: “00” (0%)
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 58 - 1. Grounding and Power Supply Decoupling The AK4368 requires careful attention to power supply and grounding arrangements. AVDD, PVDD and HVDD are usually supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10Ω resistor. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. When AVDD and HVDD are supplied separately, AVDD is powered-up at the same time or earlier than HVDD. When the AK4368 is powered-down, HVDD is powered-down at the same time or later than AVDD. The power up sequence of PVDD is not critical. AVSS, DVSS, PVSS and HVSS must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4368 as possible, with the small value ceramic capacitors being the nearest. 2. Voltage Reference The input voltage to AVDD sets the analog output range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor are connected between AVDD and AVSS. VCOM is a signal ground of this chip (0.475 x AVDD). An electrolytic 2.2µF attached between VCOM and AVSS eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be kept away from AVDD and VCOM in order to avoid unwanted coupling into the AK4368. 3. Analog Outputs The analog outputs are single-ended outputs, and 0.47 x AVDD Vpp(typ)@-3dBFS for headphone-amp and 0.61xAVDD Vpp(typ) @0dBFS for LOUT/ROUT centered on the VCOM voltage. The input data format is 2’s compliment. The output voltage is a positive full scale for 7FFFFFH(@24bit) and negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM plus a few mV.
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 59 - PACKAGE 4.0 ± 0.1 4.0 ± 0.1 0.5 A B C E F G 7 6 5 3 2 41 - φ 0.3 ± 0.05 0.08 S S φ 0.15 ABS B 0.5 M A 3.0 1.0MAX 0.23 ± 0.05 D 3.0 Package & Lead frame material Package molding compound: Epoxy I n t e r p o s e r m a t e r i a l : B T r e s i n Solder ball material: SnAgCu
ASAHI KASEI [AK4368EG] MS0529-E-00 2006/07 - 60 - MARKING 4368 XXXX XXXX: Date code (4 digit) Pin #1 indication
Revision History
Date (YY/MM/DD) Revision Reason Page Contents 06/07/25 00 First Edition IMPORTANT NOTICE
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