AK4342 AKM | Alldatasheet
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ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 1 - GENERAL DESCRIPTION The AK4342 is a 24-bit stereo DAC with 2Vrms lineout, an integrated headphone amplifier, and an auxiliary line output. The AK4342 features an analog mixing circuit that enables a simple interface to external analog audio sources. The integrated headphone amplifier features “click-free” power-on/off, a mute control and delivers 62.5mW of power at 16Ω @ 3.3V. The AK4342 is controlled via an I2C or 3-wire interface, and is available in a 32-pin QFN package. FEATURE Multi-bit 24-bit ∆Σ DAC Sampling Rate: 8kHz to 96kHz 8 times Oversampling FIR interpolator - Passband: 20kHz - Passband Ripple: ±0.02dB - Stopband Attenuation: 54dB Audio I/F Format: MSB First, 2’s Complement - I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified Master Clock: - Normal Speed Mode: 256fs/384fs/512fs/768fs - Double Speed Mode: 128fs/192fs/256fs/384fs - Half Speed Mode: 512fs/768fs Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz Analog volume control: - Headphone: +6dB to – 48dB, Variable Step Size - Lineout: 0dB to – 31dB, 1dB step Digital Linear Attenuator Digital Soft Mute Analog Mixing Circuit µP Interface: 3-wire/I 2C (400kHz mode) Pop Noise Free at Power-ON/OFF and Mute DAC Performance (Lineout) - THD+N: -88dB - Dynamic Range: 100dB - Output Level: 2Vrms DAC Performance (Aux-Out) - THD+N: -87dB - Dynamic Range: 95dB Headphone Amplifier (Cap-less) - Output Power: 62.5mW x 2ch @16Ω, 3.3V - THD+N: -60dB @ 25mW - Dynamic Range: 95dB Power Supply: - DAC & Output Buffers: 2.7V ∼ 3.6V - Digital Interface: 1.6V ∼ 3.6V Power Supply Current: 30.5mA (Headphone amp off) Ta: −30 ∼ 85°C Package: 32pin QFN AK4342 24-Bit Stereo DAC with HP-AMP & 2V Line-Out
Figure 1. AK4342 Block Diagram
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 3 - Ordering Guide AK4342EN −30 ∼ +85°C 32pin QFN (0.5mm pitch) AKD4342 Evaluation board for AK4342 Pin Layout MUTET VCOM AVDD AVSS DVSS DVDD TVDD I2C RIN LIN RAUX LAUX ROUT LOUT HVSS HVDD SDA/CDTI SCL/CCLK CAD0/CSN MCLK BICK LRCK SDATA PDN HPR HPL HVEE PVEE PVSS PVDD CN CP AK4342EN Top View
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 4 - PIN/FUNCTION No. Pin Name I/O Function SDA I/O Control Data Input/Output Pin (I2C pin = “H”) An external pull-up resister is required. 1 CDTI I Control Data Input Pin (I2C pin = “L”) SCL I Control Data Clock Pin (I2C pin = “H”) An external pull-up resistor is required. 2 CCLK I Control Data Clock Pin (I2C pin = “L”) CAD0 I Chip Address 0 Select Pin (I2C pin = “H”) (Internal Pull-up Pin to TVDD pin) 3 CSN I Control Data Chip Select Pin (I2C pin = “L”) (Internal Pull-up Pin to TVDD pin)
4 MCLK I Master Clock Input Pin
5 BICK I Serial Bit Clock Pin
This clock is used to latch audio data.
6 LRCK I L/R Clock Pin
This clock determines which audio channel is currently being input on SDATA pin.
7 SDATA I Audio Serial Data Input Pin
8 PDN I
Power-down & Reset Pin When at “L”, the AK4342 is in power-down mode and is held in reset. The AK4342 must be reset once upon power-up.
9 CP O Positive Charge Pump Capacitor Terminal Pin
10 CN I Negative Charge Pump Capacitor Terminal Pin
11 PVDD - Charge Pump Circuit Positive Power Supply Pin
12 PVSS - Charge Pump Circuit Ground Pin
13 PVEE O Charge Pump Circuit Negative Voltage Output Pin
14 HVEE - Headphone Amp Negative Power Supply Pin
15 HPL O Lch Headphone Amp Output Pin
16 HPR O Rch Headphone Amp Output Pin
17 HVDD - Headphone Amp Positive Power Supply Pin
18 HVSS - Headphone Amp Ground Pin
19 LOUT O Lch Lineout Output Pin
20 ROUT O Rch Lineout Output Pin
21 LAUX O Lch Auxiliary Output Pin
22 RAUX O Rch Auxiliary Output Pin
23 LIN I Lch Analog Input Pin
24 RIN I Rch Analog Input Pin
25 MUTET O Mute Time Constant Control Pin
Connected to AVSS pin through a 1µF capacitor for mute time constant.
26 VCOM O
Normally connected to AVSS pin with 0.1µF ceramic capacitor in parallel with a 2.2µF electrolytic capacitor.
27 AVDD - Analog Power Supply Pin
28 AVSS - Analog Ground Pin
29 DVSS - Digital Ground Pin
30 DVDD - Digital Power Supply Pin
31 TVDD - Digital Interface Power Supply Pin
32 I2C I Control Mode Select Pin (Internal Pull-up Pin to TVDD pin)
“H”: I2C Bus, “L”: 3-wire Serial Note: Do not allow digital input pins except analog input pins (RIN and LIN) and internal pull-up pins (CAD0/CSN and I2C) to float.
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 5 - Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Setting Analog MUTET, HPL, HPR, LOUT, ROUT, LAUX, RAUX, RIN, LIN These pins should be open.
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 6 - ABSOLUTE MAXIMUM RATING (AVSS, DVSS, HVSS, PVSS = 0V; Note 1) Parameter Symbol min max Units Analog AVDD −0.3 4.0 V Digital DVDD −0.3 4.0 V HP-Amp HVDD −0.3 4.0 V Charge Pump PVDD −0.3 4.0 V Digital I/F TVDD −0.3 4.0 V |AVSS – DVSS | (Note 2) ∆GND1 0.3 V |AVSS – HVSS | (Note 2) ∆GND2 0.3 V Power Supplies |AVSS – PVSS | (Note 2) ∆GND3 0.3 V Input Current (any pins except for supplies) IIN - ±10 mA Analog Input Voltage (Note 3) AVIN −0.3 AVDD+0.3 or 4.0 V Digital Input Voltage (Note 4) DVIN −0.3 TVDD+0.3 or 4.0 V Ambient Temperature Ta −30 85 °C Storage Temperature Tstg −65 150 °C Maximum Power Dissipation (Note 5) Pd - 700 mW Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS, HVSS and PVSS must be connected to the same analog plane. Note 4. MCLK, BICK, LRCK, SDATA, CAD0/CSN, SCL/CCLK, SDA/CDTI, I2C and PDN pins. The maximum value is low value either “TVDD+0.3V” or “4.0V”. Pull-up resistors at SDA and SCL pins should be connected to (TVDD+0.3)V or less voltage. Note 5. In case that PCB wiring density is 100%. This power is the AK4342 internal dissipation that does not include power of externally connected headphone. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMEND OPERATING CONDITIONS (AVSS, DVSS, HVSS, PVSS = 0V; Note 1) Parameter Symbol min typ max Units Analog AVDD 2.7 3.3 3.6 V Digital DVDD 2.7 3.3 3.6 V HP-Amp HVDD 2.7 3.3 3.6 V Charge Pump PVDD 2.7 3.3 3.6 V Digital I/F TVDD 1.6 1.8 DVDD V Power Supplies ( Note 6) Difference DVDD – AVDD DVDD – HVDD DVDD – PVDD -0.3 -0.3 -0.3 0.3 0.3 0.3 V V V Note 1. All voltages with respect to ground. Note 6. Power up sequence among AVDD, DVDD, HVDD, PVDD and TVDD is not critical. But PDN pin must keep “L” until all power supply pins are applied. After that, PDN pin should be set to “H”. Each power supply cannot be partially powered OFF. * AKM assumes no responsibility for usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 7 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=HVDD=PVDD=3.3V, TVDD=1.8V, AVSS=DVSS=HVSS=PVSS=0V; fs=44.1kHz; Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Headphone-Amp: RL =16Ω; Line output: RL =10kΩ, Aux output: RL =10kΩ; Charge Pump Circuit External Capacitance: C1=C2= 2.2µF (see Figure 2); unless otherwise specified) Parameter min typ max Units DAC Resolution - - 24 bit LINEIN: (LIN/RIN pins) Analog Input Characteristics: Maximum Input Voltage (Note 7) - - 1.98 Vpp Feedback Resistance 14 20 26 kΩ Gain (LIN/RIN pins: External resistor = 20kΩ) (Note 8) Vin = 1Vpp LIN/RIN → HPL/HPR (Note 9) −1.5 1.5 4.5 dB LIN/RIN → LOUT/ROUT (Note 10) 4.5 7.5 10.5 dB LIN/RIN → LAUX/RAUX −4.7 −1.7 1.3 dB Headphone-Amp: (DAC Æ HPL/HPR pins) (Note 11) Analog Output Characteristics THD+N fs=44.1kHz 0dBFS Output, Po=62.5mW - −40 - dB BW=20kHz −4dBFS Output, Po=25mW - −60 −50 dB fs=96kHz 0dBFS Output, Po=62.5mW - −40 - dB BW=40kHz −4dBFS Output, Po=25mW - −60 −50 dB Dynamic Range (−60dBFS Output, A-weighted) 87 95 - dB S/N (A-weighted) 87 95 - dB Interchannel Isolation 60 80 - dB DC Accuracy Interchannel Gain Mismatch - 0.2 1.0 dB Gain Drift - 200 - ppm/°C Load Resistance 16 - - Ω Load Capacitance - - 300 pF Output Voltage (0dBFS Output) (Note 12) 0.9 1.0 1.1 Vrms Line Output: (DAC Æ LOUT/ROUT pins) (Note 13) Analog Output Characteristics THD+N fs=44.1kHz 0dBFS Output - −88 −78 dB BW=20kHz -60dBFS Output - −37 - dB fs=96kHz 0dBFS Output - −88 −78 dB BW=40kHz -60dBFS Output - −35 - dB Dynamic Range (−60dBFS Output, A-weighted) 92 100 - dB S/N (A-weighted) 92 100 - dB Interchannel Isolation 80 100 - dB DC Accuracy Interchannel Gain Mismatch - 0.2 0.8 dB Gain Drift - 200 - ppm/°C Load Resistance 10 - - kΩ Load Capacitance (C3 in Figure 3) - - 25 pF Output Voltage (Note 14) 1.8 2.0 2.2 Vrms
Note 18. PMVCM=PMDAC=PMHP=PMLO=PMAUX bits = “1” and HP-Amp output is off. at DVSS. I2C and CSN/CAD0 pins are held at TVDD. Figure 4. Aux-out circuit example
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 10 - FILTER CHARACTERISTICS Parameter Symbol min typ max Units DAC Digital Filter: Passband ±0.05dB (Note 20) PB 0 - 20.0 kHz −6.0dB - 22.05 - kHz Stopband (Note 20) SB 24.1 - - kHz Passband Ripple PR - - ±0.02 dB Stopband Attenuation SA 54 - - dB Group Delay (Note 21) GD - 21 - 1/fs Group Delay Distortion ∆GD - 0 - µs Digital Filter + Analog Filter: (Note 22) Frequency Response 20.0kHz (fs=44.1kHz) FR - −0.5 - dB 40.0kHz (fs=96kHz) FR - −1.5 - dB Analog Filter: (Note 23) Frequency Response 20.0kHz FR - ±1.0 - dB 40.0kHz FR - ±1.0 - dB Note 20. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.05dB), SB=0.546*fs(@−54dB). Note 21. Delay time caused by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal. Note 22. DAC Æ HPL/HPR/LOUT/ROUT/LAUX/RAUX Note 23. LIN Æ HPL/LOUT/LAUX, RIN Æ HPR/ROUT/RAUX DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=1.6 ∼ 3.6V) Parameter Symbol min typ max Units High-Level Input Voltage (2.7V ≤ TVDD ≤ 3.6V) VIH 70%TVDD - - V (1.6V ≤ TVDD < 2.7V) VIH 80%TVDD - - V Low-Level Input Voltage (2.7V ≤ TVDD ≤ 3.6V) VIL - - 30%TVDD V (1.6V ≤ TVDD < 2.7V) VIL - - 20%TVDD V Low-Level Output Voltage (Iout = 3mA) VOL - - 0.4 V Input Leakage Current (Note 24) Iin - - ±10 µA Note 24. Except I2C and CSN/CAD0 pins. These pins have internal pull-up device, nominally 100kΩ.
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 11 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=1.6 ∼ 3.6V) Parameter Symbol min typ max Units Master Clock Timing (2.7V ≤ TVDD ≤ 3.6V) Half Speed Mode (512/768fs) Normal Speed Mode (256/384/512/768fs) Double Speed Mode (128/192/256/384fs) fCLK fCLK fCLK 4.096 2.048 6.144 18.432 36.864 36.864 MHz MHz MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns Master Clock Timing (1.6V ≤ TVDD < 2.7V) Half Speed Mode (512/768fs) Normal Speed Mode (256/384fs) Double Speed Mode (128/192fs) fCLK fCLK fCLK 4.096 2.048 6.144 18.432 18.432 18.432 MHz MHz MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Timing Frequency Half Speed Mode (DFS1-0 bits = “10”) Normal Speed Mode (DFS1-0 bits = “00”) Double Speed Mode (DFS1-0 bits = “01”) fsh fsn fsd kHz kHz kHz Duty Cycle Duty 45 - 55 % Serial Interface Timing (Note 25) BICK Period Half Speed Mode tBCK 1/128fsh - - ns Normal Speed Mode tBCK 1/128fsn - - ns Double Speed Mode tBCK 1/64fsd - - ns BICK Pulse Width Low tBCKL 70 - - ns Pulse Width High tBCKH 70 - - ns LRCK Edge to BICK “↑” (Note 26) tLRB 40 - - ns BICK “↑” to LRCK Edge (Note 26) tBLR 40 - - ns LRCK Edge to BICK “↓” (Note 27) tLRB 40 - - ns BICK “↓” to LRCK Edge (Note 27) tBLR 40 - - ns SDATA Hold Time tSDH 40 - - ns SDATA Setup Time tSDS 40 - - ns Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 - - ns CCLK Pulse Width Low tCCKL 80 - - ns Pulse Width High tCCKH 80 - - ns CDTI Setup Time tCDS 40 - - ns CDTI Hold Time tCDH 40 - - ns CSN “H” Time tCSW 150 - - ns CSN “↓” to CCLK “↑” tCSS 50 - - ns CCLK “↑” to CSN “↑” tCSH 50 - - ns Power-down & Reset Timing PDN Pulse Width (Note 28) tPD 150 - - ns Note 25. Refer to “Serial Data Interface”. Note 26. When BCKP bit is set to “0”, BICK rising edge must not occur at the same time as LRCK edge. Note 27. When BCKP bit is set to “1”, BICK falling edge must not occur at the same time as LRCK edge. Note 28. The AK4342 can be reset by bringing PDN pin = “L” to “H” only upon power up.
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 12 - SWITCHING CHARACTERISTICS (Continued) (Ta=25°C; AVDD, DVDD, HVDD, PVDD=2.7 ∼ 3.6V; TVDD=2.7 ∼ 3.6V) Parameter Symbol min typ max Units Control Interface Timing (I2C Bus mode): (Note 29) SCL Clock Frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - µs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - µs Clock Low Time tLOW 1.3 - - µs Clock High Time tHIGH 0.6 - - µs Setup Time for Repeated Start Condition tSU:STA 0.6 - - µs SDA Hold Time from SCL Falling (Note 30) tHD:DAT 0 - µs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - µs Rise Time of Both SDA and SCL Lines tR - - 0.3 µs Fall Time of Both SDA and SCL Lines tF - - 0.3 µs Setup Time for Stop Condition tSU:STO 0.6 - - µs Capacitive load on bus Cb - 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 ns Note 29. I2C is a registered trademark of Philips Semiconductors. TVDD voltage must be 2.7V ∼ 3.6V in I2C mode. Note 30. Data must be held long enough to bridge the 300ns-transition time of SCL.
Table 1. System Clock Example Table 2. Set up of Sampling Frequency Table 3. Relationship between Clock Mode and S/N of Lineout, Headphone and Aux-out circuit and lineout amp should be in the power-down mode (PMDAC bit = PMHP bit = PMLO bit = PMCP bit = “0”).
Figure 15. Mode 3 Timing (BCKP bit = “0”, LRP bit = “0”)
The AK4342 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. executed via soft changes without any pop noise. The transition time of 1 level and all 256 levels is shown in Table 7. not written to ATTR7-0 bits. At DATTC bit = “0”, ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level.
- 20 log10 (ATT_DATA / 255) 01H 00H Mute
Table 6. Digital Volume Gain Table Table 7. Transition Time for Digital Volume
source without stopping the signal transmission. Figure 16. Soft Mute Function (2) Analog output corresponding to digital input has group delay (GD). and returned to ATT level by the same cycle. the AK4342 is half speed mode or double speed mode, the DEM1-0 bits are ignored and the de-emphasis filter is disabled. Table 8. De-emphasis Filter Frequency control
BICK and LRCK) should be supplied. The power up time of charge pump circuit depends on FS3-0 bits (See Table 9). Table 9. Power up time of Charge Pump Circuit Signal level from LIN/RIN is adjusted by an external resistor (Ri). Internal feedback resistance (Rf) is 20k ± 30% Ω. path (LINL, LINR, RINL and RINR bits) should not be changed during the transition. Figure 17. Block diagram of LIN/RIN inputs
removed. The minimum load resistance is 16 Ω. not written to PGAR4-0 bits. At PGAC bit = “0”, PGAL4-0 bits control Lch level and PGAR4-0 bits control Rch level. should be changed after the transition time passes. bit”), the gain of right channel is changed to the last register setting which is written into PGAR4-0 bits.
- • 1AH +1 19H 0 Default 18H -1
- • 10H -9 1dB 16 0FH -10 0EH -12
- • 06H -28 05H -30 2dB 11 04H -32 03H -36 02H -40 01H -44 00H -48 4dB 5
Table 10. Volume Setting for headphone amplifier frequency(FS3-0 bits). When HMUTEL/HMUTER bit is set to “0”, the outputs are in normal operation. should be done in the mute state (HMUTEL bit = HMUTER bit = “1”).
0dBFS). The minimum load resistance is 10kΩ.
- Analog volume for lineout
frequency (See Table 2 and Table 15).
- • 18H -29 01H -30 00H -31 1dB 32
Table 11. Volume Setting for Lineout depends on the setting of PTS1-0 bits and sampling frequency(FS3-0 bits). This function is common to L/R channels. When LMUTE bit is set to “0”, the outputs are in normal operation. Figure 18. External 1st order LPF Circuit Example
typically 700mVrms (@ AVDD = 3.3V, 0dBFS). The minimum load resistance is 10kΩ. power-up. Rise/Fall time constant is in proportional to AVDD voltage and the capacitor at MUTET pin. voltage. When the AMUTE bit is set to “0”, the outputs are in normal operation. Figure 19. Power-up/Power-down Timing for Aux-out amplifier (1) Aux-out amplifier power-up (PMAUX bit = “1”). The outputs are still AVSS. Aux-out amplifier is powered-down before the common voltage goes to AVSS, some pop noise occurs.
interval time depends on the transition time. The setting of transition time should not be changed during transition. Table 12. Registers with transition time (PUT1-0 bits) Table 13. Transition Time (PUT1-0 bits) Table 14. Registers with transition time (PTS1-0 bits) Table 15. Transition Time (PTS1-0 bits)
register are maintained until the reset is done. and the internal timing starts clocking by LRCK edge. DAC is in power-down mode until MCLK and LRCK are input. Figure 20. Example of Power-up/down Sequence “L” time (1) of 150ns or more is needed to reset the AK4342. PDN pin must keep “L” until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied. After they are applied, PDN pin must be set to “H”. period before the DAC and charge pump circuit are powered-up.
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 28 - (4) Power Up the charge pump circuit, DAC and VCOM; PMCP bit = PMDAC bit = PMVCM bit = “0” Æ “1” PVEE pin goes to PVEE voltage according to the setting of FS3-0 bits (See Table 9). (5) When PMCP bit and PMHP bit (PMLO bit) are set to “1” at the same time or PMHP bit (PMLO bit) is set to “1” during the charge pump circuit is powered-up, headphone (lineout) amplifier is powered-up after the charge pump circuit is powered-up. (6) Power Up the headphone (lineout) amplifiers; PMHP bit (PMLO bit) = “0” Æ “1” The headphone (lineout) amplifiers are in mute state and have some DC offset. The power up time of headphone (lineout) amplifiers depends on PUT1-0 bits and FS3-0 bits. PMHP and PMLO bits should not be changed during this period. (7) Release the mute state of headphone (lineout) amplifiers; HMUTEL bit = HMUTER bit (LMUTE bit) = “1” Æ “0” The headphone (lineout) amplifiers are in the normal state after the trans ition time passes. The transition is executed via soft changes. The transition time depends on PTS1-0 bits and FS3-0 bits. LPGA4-0, PGAL4-0, PGAR4-0 and PGAC bits should not be changed during this period. (8) Mute headphone (lineout) amplifiers: HMUTEL = HMUTER (LMUTE bit) = “0” Æ “1” The headphone (lineout) amplifiers are in the mute state after the transition time passes. The transition is executed via soft changes. The transition time depends on PTS1-0 bits and FS3-0 bits. LPGA4-0, PGAL4-0, PGAR4-0 and PGAC bits should not be changed during this period. (9) Power-down the headphone (lineout) amp; PMHP bit (PMLO bit) = “1” Æ “0” The headphone (lineout) amplifiers are powered-down. The power-down time of headphone (lineout) amplifiers depend on PUT1-0 bits and FS3-0 bits. PMHP and PMLO bits should not be changed during this period. (10) Power down the charge pump circuit, DAC and VCOM; PMCP bit = PMDAC bit = PMVCM bit = “1” Æ “0” PVEE pin becomes “0V” according to the time constant of internal resistor and capacitor of PVEE and HVEE pins. Internal resistor is typically 17.5kΩ. The charge pump circuit may be powered-up during this period.
- 3-wire Serial Control Mode (I2C pin = “L”)
Figure 21. Serial Control I/F Timing
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 33 - Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 0 PMAUX PMLO PMCP PMHP PMDAC PMVCM 01H Mode Control 0 AMUTE SMUTE AVCMN DIF2 DIF1 DIF0 DFS1 DFS0 02H Mode Control 1 0 0 FS3 FS2 FS1 FS0 DEM1 DEM0 03H Mode Control 2 PGAC PTS1 PTS0 STS1 STS0 DATTC BCKP LRP 04H HP Lch PGA Control 0 0 HMUTEL PGAL4 PGAL3 PGAL2 PGAL1 PGAL0 05H HP Rch PGA Control 0 0 HMUTER PGAR4 PGAR3 PGAR2 PGAR1 PGAR0 06H Output Select PUT1 PUT0 RINR RINL LINR LINL DACLR 0 07H Lineout PGA control 0 0 LMUTE LPGA4 LPGA3 LPGA2 LPGA1 LPGA0 08H DAC Lch ATT ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0 09H DAC Rch ATT ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0 All registers inhibit writing at PDN pin = “L”. PDN pin = “L” resets the registers to their default values. Note 31: The bits indicated to “0” in the register map must contain a “0” value. Note 32: Only write to address 00H to 09H.
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 34 - Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 0 PMAUX PMLO PMCP PMHP PMDAC PMVCM R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMVCM: Power Management for VCOM Block 0: Power OFF (Default) 1: Power ON PMDAC: Power Management for DAC Blocks 0: Power OFF (Default) 1: Power ON When PMDAC bit is changed from “0” to “1”, DAC is powered-up with the current register values (ATT value, sampling rate, etc). PMHP: Power Management for Headphone Amp 0: Power OFF (Default). HPL/HPR pins become HVSS (0V). 1: Power ON PMCP: Power Management for Charge Pump Circuit 0: Power OFF (Default) 1: Power ON PMLO: Power Management for Line-out Amp 0: Power OFF (Default). LOUT/ROUT pins become HVSS (0V). 1: Power ON PMAUX: Power Management for Aux Out 0: Power OFF (Default) LAUX and RAUAX pins become AVSS (0V). 1: Power ON All blocks can be powered-down by setting the PDN pin to “L” regardless of register values setup. All blocks can be also powered-down by setting all bits of this address to “0”. In this case, control register values are maintained.
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 35 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Mode Control 0 AMUTE SMUTE AVCMN DIF2 DIF1 DIF0 DFS1 DFS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 0 1 0 0 0 DFS1-0: Sampling Speed Select (See Table 1) Default: “00” (Normal Speed Mode) DIF2-0: Audio Data Interface Format Select (See Table 4) Default: “010” (Mode 2; 24bit, MSB justified) AVCMN: Common Voltage control for LAUX/RAUX 0: LAUX/RAUX pins become AVSS (0V). (Default) 1: LAUX/RAUX pins become “0.45 x AVDD”. SMUTE: Soft Mute Control 0: Normal operation (Default) 1: DAC outputs soft-muted AMUTE: Mute control for LAUX/RAUX 0: Normal operation 1: Mute. LAUX/RAUX pins output common voltage. (Default) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Mode Control 1 0 0 FS3 FS2 FS1 FS0 DEM1 DEM0 R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 DEM1-0: De-emphasis Filter Frequency Select (See Table 8) Default: “01” (OFF) FS3-0: Sampling Frequency Select (Table 2) Default: “0000” (fs=44.1kHz)
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 36 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Mode Control 2 PGAC PTS1 PTS0 STS1 STS0 DATTC BCKP LRP R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 0 0 0 LRP: LRCK Polarity Select 0: Normal (Default) 1: Invert BCKP: BICK Polarity Select 0: Normal (Default) 1: Invert DATTC: DAC Digital Attenuator Control Mode Select 0: Independent (Default) 1: Dependent At DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation level, while register values of ATTL7-0 bits are not written to ATTR7-0 bits. At DATTC bit = “0”, ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. STS1-0: Soft mute cycle setting (See Table 7) Default: “01” (1020LRCK at Normal Speed Mode) PTS1-0: Select Transition time for AMUTE, LINL, LINR, RINL, RINR, DACLR, LPGA4-0, PGAL4-0, PGAR4-0, LMUTE, HMUTEL and HMUTER (See Table 15) Default: “00” PGAC: PGA Control Mode Select 0: Independent (Default) 1: Dependent At PGAC bit = “1”, PGL4-0 bits control both Lch and Rch attenuation level, while register values of PGAL4-0 bits are not written to PGAR4-0 bits. At PG AC bit = “0”, PGAL4-0 bits control Lch level and PGAR4-0 bits control Rch level. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Lch PGA Control 0 0 HMUTEL PGAL4 PGAL3 PGAL2 PGAL1 PGAL0 05H Rch PGA Control 0 0 HMUTER PGAR4 PGAR3 PGAR2 PGAR1 PGAR0 R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 1 1 1 0 0 1 PGAL4-0: Setting of analog volume for Lch (See Table 10) HMUTEL: Mute control for HPL 0: Normal operation PGAL4-0 bits control attenuation value. 1: Mute. (Default) PGAL4-0 bits are ignored. PGAR4-0: Setting of analog volume for Rch (See Table 10) HMUTER: Mute control for HPR 0: Normal operation PGAR4-0 bits control attenuation value. 1: Mute. (Default) PGAR4-0 bits are ignored.
DACLR: DAC output signal is added to MIX amp. LINL: Input signal to LIN pin is added to Lch of MIX amp. LINR: Input signal to LIN pin is added to Rch of MIX amp. RINL: Input signal to RIN pin is added to Lch of MIX amp. RINR: Input signal to RIN pin is added to Rch of MIX amp. Figure 31. Analog Mixing Circuit
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 38 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Lineout PGA Control 0 0 LMUTE LPGA4 LPGA3 LPGA2 LPGA1 LPGA0 R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 1 1 1 1 1 1 LPGA4-0: Setting of the analog volume for Lineout Default: “1FH” (0dB) (See Table 11) LMUTE: Mute control for LOUT/ROUT 0: Normal operation LPGA4-0 bits control attenuation value. 1: Mute. (Default) LPGA4-0 bits are ignored. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H DAC Lch ATT ATTL7 ATTL6 A TTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0 09H DAC Rch ATT ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 ATTL7-0: Setting of the attenuation value of output signal from DAC Lch ATTR7-0: Setting of the attenuation value of output signal from DAC Rch ATT = 20 log10 (ATT_DATA / 255) [dB] FFH: 0dB (Default) 00H: Mute
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 40 - PACKAGE 32pin QFN (Unit: mm)4.75 ± 0.10 5.00 ± 0.10 4.75 ± 0.10 5.00 ± 0.10 0.500.23 24 17 0.01 0.85 ± 0.05 0.08 0.40 ± 0.10 +0.07 -0.05 0.20 + 0.04 - 0.01 C Exposed Pad 3.5 3.5 C0.42 B A C M0.10 AB Note) The exposed pad on the bottom surface of the package must be connected to the ground. Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 41 - MARKING 4342 XXXX XXXXX : Date code identifier (4 digits)
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 42 -
Revision History
Date (YY/MM/DD) Revision Reason Page Contents 06/04/26 00 First Edition 06/05/09 01 Change
description
39 SYSTEM DESIGN:
Figure 32: A 2Ω resistor was added between PVDD and HVDD pins and power supply line. Note: “A 2Ω resistor should be added in series ∼ the current.” was added. 06/07/07 02 Error Correct 7 ANALOG CHARACTERISTICS: Headphone-Amp; THD+N (fs=44.1kHz, 0dBFS output): typ. -20dB Î -40dB THD+N (fs=96kHz, 0dBFS output): typ. -20dB Î -40dB Line Output; THD+N (fs=96kHz, 0dBFS output): typ. -85dB Î -88dB
23 Headphone Output
- Analog output volume; See Table 12 and Table 15 Î See Table 2 and Table 15
24 Lineout amp
- Analog volume for lineout; See Table 12 and Table 15 Î See Table 2 and Table 15
25 Aux-out amp
Figure 19: (2) [AVCMN bit = “0”] Î [AVCMN bit = “1”] (3) [AVCMN bit = “1”] Î [AVCMN bit =“0”]
27 Power-Up/Down Sequence:
Figure 20; The location of (4) in Figure 20 was changed. 29 3-wire Serial Control Mode: ∼ 2-bit Chip address (Fixed to “10”) Î ∼ 2-bit Chip address (Fixed to “01”)
30 I2C –bus Control Mode:
a. [The AK4342 supports ∼ (max.100kHz).] was deleted. b. [The AK4342 does not support a fast-mode I2C-bus system (max.400kHz).] Î [The AK4342 supports a fast-mode I2C-bus system (max.400kHz).] c. WRITE Operations; [If the address exceeds 08H prior to ∼. ] Î [If the address exceeds 09H prior to ∼.]
37 Addr=06H, PUT1-0:
See Table 12 Î See Table 13
ASAHI KASEI [AK4342] MS0506-E-02 2006/07 - 43 - IMPORTANT NOTICE
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