AK4331

Asahi Kasei Microsystem...

Low-Power Advanced 32-bit DAC with HP/SRC

Manufacturer: Asahi Kasei Microsystem...

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[AK4331] 018006903-E-00 2018/07 - 1 - 1. General Description The AK4331 is an advanced 32-bit high sound quality stereo audio DAC with a built-in ground-referenced headphone amplifier. The AK4331 has four types of 32-bit digital filters for better sound quality, achieving low distortion characteristics and wide dynamic range. The AK4331 also has a jitter cleaner with a built-in SRC and a X’tal. The AK4331 is available in a 36 -pin CSP package, utilizing less board space than competitive offerings. 2. Features 1. High Sound Quality Low Power Advanced 32-bit Stereo DAC - 4 types of Digital Filter for Sound Color Selection - Short Delay Sharp Roll-off, GD = 5.5 / fs - Short Delay Slow Roll-off, GD = 4.5 / fs - Sharp Roll-off - Slow Roll-off 2. Ground-referenced Class-G Stereo Headphone Amplifier - Output Power: 70 mW @ 8Ω - THD+N: 100 dB - S/N: 109 dB - Output Noise Level: 114 dBV (Analog Volume = 10 dB) - Analog Volume: +4 to 10 dB, 2 dB Step - Ground Loop Noise Cancellation 3. Low Power Consumption: 4.4 mW (Play back, fs = 48 kHz, External Slave Mode) 5.0 mW (Play back, fs = 48 kHz, PLL Slave Mode) 4. Headphone Amplifier Output Pins Comply with IEC61000-4-2 ESD Protection - ±8 kV Contact Discharge 5. Digital Audio interface - Master / Slave Mode - Sampling Frequency (Slave Mode / Master Mode): 8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 64 k, 88.2 k, 96 k, 128 k, 176.4 k, 192 kHz - Interface Format: 32/24/16-bit I2S/MSB justified 6. Asynchronous Sample Rate Converter - Up sample: up to ×6.02 7. Stereo Digital Microphone Interface 8. Power Management 9. PLL 10. Jitter Cleaner with a built-in SRC and X’tal Oscillator 11. μP Interface: I2C-bus (400 kHz) 12. Operation Temperature Range: Ta = 40 to 85 C 13. Power Supply:  AVDD (DAC, PLL): 1.7 to 1.9 V  CVDD (Headphone Amplifier, Charge Pump): 1.7 to 1.9 V  LVDD (LDO2 for Digital Core): 1.7 to 1.9 V (built-in LDO)  TVDD (Digital Interface): 1.65 to 3.6 V 14. Pin Compatible and Register Backward Compatible with the AK4375A 15. Package: 36-pin CSP (2.533 × 2.371 mm, 0.4 mm pitch) Low-Power Advanced 32-bit DAC with HP/SRC AK4331

[AK4331] 018006903-E-00 2018/07 - 2 - 3. Table of Contents

[AK4331] 018006903-E-00 2018/07 - 3 -

Block Diagram and Functions

Figure 1. AK4331 Block Diagram

[AK4331] 018006903-E-00 2018/07 - 5 - 5. Pin Configurations and Functions 5-1. Pin Configurations 36-pin CSP

6 VDD12 LVDD CN1 CP1 CVDD CN2B

5 VSS3 SDTI VEE1 VSS2 CP2B CN2A

4 TVDD LRCK SDA SCL CP2A VEE2

3 MCKI

/XTI BCLK PDN TEST1 VCC2 HPR

2 XTO DMDAT TEST2 VSS1 HPL HPGND

1 SDTO DMCLK RVEE RAVDD AVDD VCOM

[AK4331] 018006903-E-00 2018/07 - 6 - 5-2. Pin Function Difference with AK4375A Pin No. AK4375A AK4331 Pin Name Function Pin Name Function A1 XTI X’tal Oscillator Input Pin Left floating when not in use. SDTO Audio Serial Data Output Pin Left floating when not in use. A3 MCKI External Master Clock Input Pin Connect to VSS3 when not in use. MCKI/XTI External Master Clock Input / X’tal Oscillator Input Pin Connect to VSS3 and set PMOSC bit to “0” when not in use. B1 TESTO Test Output Pin Left floating when not in use. DMCLK Digital MIC Clock Output Pin Left floating when not in use. B2 LDO2E LDO2 Enable pin This pin must be tied “H”. DMDAT Digital MIC Data Input Pin Connect to VSS1 or AVDD when not in use. C2 VSS4 Ground4 pin This pin must be tied “L”. TEST2 Test Input pin This pin must be tied “L”.

[AK4331] 018006903-E-00 2018/07 - 7 - 5-3. Pin Functions No. Pin Name I/O Function Protection Diode Power Domain Power Supply E1 AVDD - Analog Power Supply Pin - AVDD D2 VSS1 - Ground 1 Pin - - E6 CVDD - Headphone Amplifier / Charge Pump Power Supply Pin - CVDD D5 VSS2 - Ground 2 Pin - - B6 LVDD - Digital Core & LDO2 Power Supply Pin - LVDD A5 VSS3 - Ground 3 Pin - - A4 TVDD - Digital Interface Power Supply Pin - TVDD F1 VCOM O Common Voltage Output Pin Connect a 2.2 μF ±50% capacitor between this pin and the VSS1 pin. (Note 2) AVDD / VSS1 - A6 VDD12 - LDO2 (1.2 V) Output Power Supply Pin (Note 1) Connect a capacitor between this pin to the VSS3 pin. (Note 2) LVDD / VSS3 LVDD Note 1. Capacitor value connected to the VDD12 pin should be selected from 2.2 µF ±50% to 4.7µF ±50%. Note 2. Do not connect a load to the VCOM pin and the VDD12 pin.

[AK4331] 018006903-E-00 2018/07 - 8 - No. Pin Name I/O Function Protection Diode Power Domain Charge Pump & LDO D6 CP1 O Positive Charge Pump Capacitor Terminal 1 Pin Connect a 2.2 μF ±50% capacitor between this pin and the CN1 pin. CVDD / VSS2 CVDD C6 CN1 I Negative Charge Pump Capacitor Terminal 1 Pin Connect a 2.2 μF ±50% capacitor between this pin and the CP1 pin. CVDD CVDD C5 VEE1 O Charge Pump Circuit Negative Voltage (CVDD) Output 1 Pin Connect a 2.2 μF ±50% capacitor between this pin and the VSS2 pin. (Note 3) CVDD / VSS2 - D1 RAVDD O LDO1P (1.5 V) Output Pin (Note 4) Connect a capacitor between this pin and the VSS1 pin. (Note 3) AVDD / VSS1 - C1 RVEE O LDO1N (1.5 V) Output Pin (Note 4) Connect a capacitor between this pin and the VSS1 pin. (Note 3) AVDD / VSS1 - E3 VCC2 O Charge Pump Circuit Positive Voltage (CVDD or 1/2 × CVDD) Output Pin Connect a 2.2 μF ±50% capacitor between this pin and the VSS2 pin. (Note 3) CVDD / VSS2 CVDD E4 CP2A O Positive Charge Pump Capacitor Terminal 2A Pin Connect a 2.2 μF ±50% capacitor between this pin and the CN2A pin. CVDD / VSS2 CVDD F5 CN2A I Negative Charge Pump Capacitor Terminal 2A Pin Connect a 2.2 μF ±50% capacitor between this pin and the CP2A pin. CVDD CVDD E5 CP2B O Positive Charge Pump Capacitor Terminal 2B Pin Connect a 2.2 μF ±50% capacitor between this pin and the CN2B pin. CVDD / VSS2 CVDD F6 CN2B I Negative Charge Pump Capacitor Terminal 2B Pin Connect a 2.2 μF ±50% capacitor between this pin and the CP2B pin. CVDD CVDD F4 VEE2 O Charge Pump Circuit Negative Voltage (CVDD or 1/2 × CVDD) Output 2 Pin Connect a 2.2 μF ±50% capacitor between this pin and the VSS2 pin. (Note 3) CVDD / VSS2 - Note 3. Do not connect a load to the VEE1 pin, VCC2 pin, VEE2 pin, RAVDD pin and the RVEE pin. Note 4. Capacitor value connected to the RAVDD pin and the RVEE pin should be selected from 1.0 µF ±50% to 4.7 µF ±50%.

[AK4331] 018006903-E-00 2018/07 - 9 - No. Pin Name I/O Function Protection Diode Power Domain Control Interface D4 SCL I I2C Serial Data Clock Pin TVDD / VSS3 TVDD C4 SDA I/O I2C Serial Data Input/Output Pin TVDD / VSS3 TVDD Audio Interface MCKI I External Master Clock Input Pin (PMOSC bit = “0”) TVDD / VSS3 TVDD XTI I X’tal Oscillator Input Pin (PMOSC bit = “1”) A1 SDTO O Audio Serial Data Output Pin TVDD / VSS3 TVDD A2 XTO O X’tal Oscillator Output Pin TVDD / VSS3 TVDD B3 BCLK I/O Audio Serial Data Clock Pin TVDD / VSS3 TVDD B4 LRCK I/O Frame Sync Clock Pin TVDD / VSS3 TVDD B5 SDTI I Audio Serial Data Input Pin TVDD / VSS3 TVDD Analog Output E2 HPL O Lch Headphone Amplifier Output Pin CVDD / VEE2 CVDD / VEE2 F3 HPR O Rch Headphone Amplifier Output Pin CVDD / VEE2 CVDD / VEE2 F2 HPGND I Headphone Amplifier Ground Loop Noise Cancellation Pin - - Digital MIC Interface B1 DMCLK O Digital MIC Clock Output Pin AVDD / VSS1 AVDD B2 DMDAT I Digital MIC Data Input Pin AVDD / VSS1 AVDD Others C3 PDN I Power down Pin “L”: Power-Down, “H”: Power-Up TVDD / VSS3 TVDD D3 TEST1 I Test Input 1 Pin It must be tied “L”. TVDD VSS3 TVDD C2 TEST2 I Test Input 2 Pin It must be tied “L”. TVDD / VSS3 TVDD Note 5. The SCL pin, SDA pin, MCKI/XTI pin, BCLK pin, LRCK pin, SDTI pin, HPGND pin, DMDAT pin, PDN pin, TEST1 pin and the TEST2 pin must not be allowed to float.

[AK4331] 018006903-E-00 2018/07 - 10 - 5-4. Handing of Unused Pins Unused I/O pins must be connected appropriately. Classification Pin Name Setting Analog HPL, HPR Open Digital MCKI/XTI, TEST1, TEST2 Connect to VSS3 DMCLK, SDTO, XTO Open DMDAT Connect to VSS1 or AVDD

[AK4331] 018006903-E-00 2018/07 - 11 - 6. Absolute Maximum Ratings (VSS1 = VSS2 = VSS3 = 0 V; Note 7, Note 8) Parameter Symbol Min. Max. Unit Power Analog AVDD 0.3 4.3 V Supplies: Headphone Amplifier / Charge Pump CVDD 0.3 4.3 V (Note 6) LDO2 for Digital Core LVDD 0.3 4.3 V Digital Interface TVDD 0.3 4.3 V Input Current, Any Pin Except Supplies IIN - ±10 mA Digital Input Voltage 1 (Note 9) VIND1 0.3 AVDD+0.3 or 4.3 V Digital Input Voltage 2 (Note 10) VIND2 0.3 TVDD+0.3 or 4.3 V Ambient Temperature (powered applied) Ta 40 85 C Storage Temperature Tstg 65 150 C Note 6. Charge pump 1 & 2 are not in operation. In the case that charge pump 1 & 2 are in operation, the maximum values of AVDD and CVDD become 2.15 V. Note 7. All voltages with respect to ground. Note 8. VSS1, VSS2 and VSS3 must be connected to the same analog plane. Note 9. DMDAT pin The maximum value of input voltage is lower value between (AVDD+0.3) V and 4.3 V. Note 10. MCKI/XTI, BCLK, LRCK, SDTI, SCL, SDA, PDN, TEST1, TEST2 pins The maximum value of input voltage is lower value between (TVDD+0.3) V and 4.3 V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal Operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (VSS1 = VSS2 = VSS3 ＝ 0 V; Note 11) Parameter Symbol Min. Typ. Max. Unit Power Analog AVDD 1.7 1.8 1.9 V Supplies: Headphone Amplifier / Charge Pump CVDD 1.7 1.8 1.9 V (Note 12) LDO2 for Digital Core LVDD 1.7 1.8 1.9 V Digital Interface TVDD 1.65 1.8 3.6 V Note 11. All voltages with respect to ground. Note 12. Each power up/down sequence is shown below. <Power-Up> 1. PDN pin = “L” 2. TVDD, AVDD, LVDD and CVDD are powered up. (AVDD must be powered up before or at the same time of CVDD. The power-up sequence of TVDD and LVDD is not critical.) 3. The PDN pin is allowed to be “H” after all power supplies are applied and settled. <Power-down> 1. PDN pin = “L” 2. TVDD, AVDD, LVDD and CVDD are powered down. (CVDD must be powered down before or at the same time of AVDD. The power -down sequence of TVDD and LVDD is not critical.)

Electrical Characteristics

Figure 2. External Circuit for Headphone Amplifier

[AK4331] 018006903-E-00 2018/07 - 13 - Parameter Min. Typ. Max. Unit Interchannel Isolation 0 dBFS, HPG = 4 dB (Po = 10 mW) External Impedance = 0.09Ω (Note 14) 100 dB Interchannel Gain Mismatch - 0 0.8 dB Load Resistance 7.2 32 - Ω Load Capacitance - - 500 pF Load Inductance - - 0.375 µH PSRR (HPG = 4 dB) (Note 15)

217 Hz - 85 - dB

DC-offset (Note 16) HPG = 0 dB 0.15 0 +0.15 mV HPG = All gain 0.2 0 +0.2 mV Headphone Output Volume Characteristics: Gain Setting 10 - +4 dB Step Width Gain: +4 to 10 dB 1 2 3 dB Note 14. Impedance between the HPGND pin and the system ground. Note 15. PSRR is referred to all power supplies with 100 mVpp sine wave. Note 16. When there is no gain change and temperature drift after headphone amplifier is powered up. Parameter Value Unit ESD Immunity IEC61000-4-2 Level4, Contact (Note 17) ±8 kV Note 17. It is measured at the HPL and HPR pins on an evaluation board (AKD4331-SA Rev.1).

[AK4331] 018006903-E-00 2018/07 - 14 - 8-2. PLL Characteristics (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; unless otherwise specified) Parameter Min. Typ. Max. Unit PLL Characteristics Reference Clock (Note 15) 76.8 - 768 kHz PLLCLK Frequency (Note 15) 44.1 kHz × 256fs × 2 48.0 kHz × 256fs × 2 22.5792 24.576 MHz MHz Lock Time - - 2 msec 8-3. Charge Pump & LDO Circuit Power-Up Time (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; unless otherwise specified) Parameter Capacitor Min. Typ. Max. Unit Block Power-Up Time CP1 (Note 18) - - - 6.5 msec CP2 (Class-G) (Note 18, Note 19) - - - 4.5 msec LDO1P (Note 20) 1 μF @RAVDD - - 0.5 msec LDO1N (Note 20) 1 μF @RVEE - - 0.5 msec LDO2 (Note 18) - - - 1 msec Note 18. Power-up time is a fixed value that is not affected by a capacitor. Note 19. Power-up time is a value to 1/2 × CVDD, since CP2 starts with 1/2VDD Mode as part of Class-G operation. Note 20. Power-up time is proportional to a capacitor value. For instance, if a 2.2 μF capacitor is connected to the RAVDD pin, LDO1P power-up time is 1.1 msec at maximum.

Table 1. Power Consumption (Typ.) for Each Operation Mode

0 V; unless otherwise specified)

[AK4331] 018006903-E-00 2018/07 - 16 - 8-7. DAC Sharp Roll-Off Filter Characteristics (SRC Bypass Mode) 8-7-1. Sharp Roll-Off Filter (SRC Bypass Mode, fs = 48 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.006 to +0.23 dB PB 0 - 22.42 kHz (Note 23) 6.0 dB - 24.02 - kHz Stopband (Note 23) SB 26.2 - - kHz Passband Ripple PR 0.006 - +0.23 dB Stopband Attenuation (Note 24) SA 69.8 - - dB Group Delay (Note 25) GD - 25.8 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 20.0 kHz FR 0.12 - +0.10 dB Note 23. The passband and stopband frequencies scale with fs (system sampling rate). of 1 kHz. Note 24. The bandwidth of the stop band attenuation value is from stopband to fs (system sampling rate). Note 25. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog sig nal. The error of the delay at audio interface is within +1 [1/fs]. 8-7-2. Sharp Roll-Off Filter (SRC Bypass Mode, fs = 96 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 96 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.003 to +0.24 dB PB 0 - 44.85 kHz (Note 26) 6.0 dB - 48.04 - kHz Stopband (Note 26) SB 52.5 - - kHz Passband Ripple PR 0.003 - +0.24 dB Stopband Attenuation (Note 27) SA 69.8 - - dB Group Delay (Note 28) GD - 25.8 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 40.0 kHz FR 1.69 - +0.11 dB Note 26. The passband and stopband frequencies scale with fs (system sampling rate). of 1 kHz. Note 27. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 28. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 17 - 8-7-3. Sharp Roll-Off Filter (SRC Bypass Mode, fs = 192 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 192 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.002 to +0.24 dB PB 0 - 89.74 kHz (Note 29) 6.0 dB - 96.08 - kHz Stopband (Note 29) SB 104.9 - - kHz Passband Ripple PR 0.002 - +0.24 dB Stopband Attenuation (Note 30) SA 69.8 - - dB Group Delay (Note 31) GD - 25.8 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 80.0 kHz FR 8.23 - +0.35 dB Note 29. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 30. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 31. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 18 - 8-8. DAC Slow Roll-Off Filter Characteristics (SRC Bypass Mode) 8-8-1. Slow Roll-Off Filter (SRC Bypass Mode, fs = 48 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.005 dB PB 0 - 8.49 kHz (Note 32) 3.0 dB - 20.15 - kHz Stopband (Note 32) SB 42.59 - - kHz Passband Ripple PR 0.07 - +0.005 dB Stopband Attenuation (Note 33) SA 72.8 - - dB Group Delay (Note 34) GD - 25.8 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 20.0 kHz FR 3.21 - +0.03 dB Note 32. The passband and stopband frequencies scale with fs (system sampling rate). of 1 kHz. Note 33. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 34. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs]. 8-8-2. Slow Roll-Off Filter (SRC Bypass Mode, fs = 96 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 96 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.006 dB PB 0 - 17.02 kHz (Note 35) 3.0 dB - 40.3 - kHz Stopband (Note 35) SB 85.15 - - kHz Passband Ripple PR 0.07 - +0.006 dB Stopband Attenuation (Note 36) SA 72.8 - - dB Group Delay (Note 37) GD - 25.8 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 40.0 kHz FR 4.84 - +0.10 dB Note 35. The passband and stopband frequencies scale with fs (system sampling rate). of 1 kHz. Note 36. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 37. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 19 - 8-8-3. Slow Roll-Off Filter (SRC Bypass Mode, fs = 192 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 192 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.006 dB PB 0 - 34.17 kHz (Note 38) 3.0 dB - 80.65 - kHz Stopband (Note 38) SB 170.3 - - kHz Passband Ripple PR 0.07 - +0.006 dB Stopband Attenuation (Note 39) SA 72.8 - - dB Group Delay (Note 40) GD - 25.8 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 80.0 kHz FR 11.38 - +0.35 dB Note 38. The passband and stopband frequencies scale with fs (system sampling rate). of 1 kHz. Note 39. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 40. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 20 - 8-9. DAC Short Delay Sharp Roll-Off Filter Characteristics (SRC Bypass Mode) 8-9-1. Short Delay Sharp Roll-Off Filter (SRC Bypass Mode, fs = 48 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.009 to +0.232 dB PB 0 - 22.41 kHz (Note 41) 6.0 dB - 24.15 - kHz Stopband (Note 41) SB 26.23 - - kHz Passband Ripple PR 0.009 - +0.232 dB Stopband Attenuation (Note 42) SA 69.8 - - dB Group Delay (Note 43) GD - 5.5 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 20.0 kHz FR 0.12 - +0.10 dB Note 41. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 42. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 43. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs]. 8-9-2. Short Delay Sharp Roll-Off Filter (SRC Bypass Mode, fs = 96 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 96 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.004 to +0.238 dB PB 0 - 44.82 kHz (Note 44) 6.0 dB - 48.32 - kHz Stopband (Note 44) SB 52.5 - - kHz Passband Ripple PR 0.004 - +0.238 dB Stopband Attenuation (Note 45) SA 69.8 - - dB Group Delay (Note 46) GD - 5.5 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 40.0 kHz FR 1.69 - +0.11 dB Note 44. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 45. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 46. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 21 - 8-9-3. Short Delay Sharp Roll-Off Filter (SRC Bypass Mode, fs = 192 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 192 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.002 to +0.247 dB PB 0 - 89.68 kHz (Note 47) 6.0 dB - 96.64 - kHz Stopband (Note 47) SB 104.9 - - kHz Passband Ripple PR 0.002 - +0.247 dB Stopband Attenuation (Note 48) SA 69.8 - - dB Group Delay (Note 49) GD - 5.5 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 80.0 kHz FR 8.23 - +0.36 dB Note 47. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 48. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 49. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 22 - 8-10. DAC Short Delay Slow Roll-Off Filter Characteristics (SRC Bypass Mode) 8-10-1. Short Delay Slow Roll-Off Filter (SRC Bypass Mode, fs = 48 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.025 dB PB 0 - 9.82 kHz (Note 50) 3.0 dB - 20.57 - kHz Stopband (Note 50) SB 42.98 - - kHz Passband Ripple PR 0.07 - +0.025 dB Stopband Attenuation (Note 51) SA 75.1 - - dB Group Delay (Note 52) GD - 4.5 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 20.0 kHz FR 2.96 - +0.04 dB Note 50. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 51. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 52. The calculated delay time is resulting from digital filtering. This is the time fro m the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs]. 8-10-2. Short Delay Slow Roll-Off Filter (SRC Bypass Mode, fs = 96 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 96 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.027 dB PB 0 - 19.7 kHz (Note 53) 3.0 dB - 41.16 - kHz Stopband (Note 53) SB 85.97 - - kHz Passband Ripple PR 0.07 - +0.027 dB Stopband Attenuation (Note 54) SA 75.1 - - dB Group Delay (Note 55) GD - 4.5 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 40.0 kHz FR 4.59 - +0.10 dB Note 53. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 54. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 55. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the dela y at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 23 - 8-10-3. Short Delay Slow Roll-Off Filter (SRC Bypass Mode, fs = 192 kHz) (Ta = -40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 192 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.028 dB PB 0 - 39.54 kHz (Note 56) 3.0 dB - 82.37 - kHz Stopband (Note 56) SB 172 - - kHz Passband Ripple PR 0.07 - +0.028 dB Stopband Attenuation (Note 57) SA 75.1 - - dB Group Delay (Note 58) GD - 4.5 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 80.0 kHz FR 11.13 - +0.35 dB Note 56. The passband and stopband frequencies scale with fs (system sampling rate) that of 1 kHz. Note 57. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 58. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 24 - 8-11. DAC Sharp Roll-Off Filter Characteristics (SRC Mode) 8-11-1. Sharp Roll-Off Filter (SRC Mode, fs = 48 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.004 to +0.199 dB PB 0 - 22.28 kHz (Note 59) 6.0 dB - 24.00 - kHz Stopband (Note 59) SB 26.21 - - kHz Passband Ripple PR 0.004 - +0.199 dB Stopband Attenuation (Note 60) SA 70.4 - - dB Group Delay (Note 61) GD - 27.6 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 20.0 kHz FR 0.12 - +0.10 dB Note 59. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 60. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 61. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs]. 8-11-2. Sharp Roll-Off Filter (SRC Mode, fs = 96 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 96 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.001 to +0.202 dB PB 0 - 44.58 kHz (Note 62) 6.0 dB - 48.01 - kHz Stopband (Note 62) SB 52.45 - - kHz Passband Ripple PR 0.001 - +0.202 dB Stopband Attenuation (Note 63) SA 70.2 - - dB Group Delay (Note 64) GD - 27.6 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 40.0 kHz FR 1.72 - +0.11 dB Note 62. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 63. The bandwidth of the stopband attenuation value is from s topband to fs (system sampling rate). Note 64. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at a udio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 25 - 8-11-3. Sharp Roll-Off Filter (SRC Mode, fs = 192 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 192 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.000 to +0.210 dB PB 0 - 89.22 kHz (Note 65) 6.0 dB - 96.02 - kHz Stopband (Note 65) SB 104.92 - - kHz Passband Ripple PR 0.000 - +0.210 dB Stopband Attenuation (Note 66) SA 70.1 - - dB Group Delay (Note 67) GD - 27.6 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 80.0 kHz FR 8.27 - +0.35 dB Note 65. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 66. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 67. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 26 - 8-12. DAC Slow Roll-Off Filter Characteristics (SRC Mode) 8-12-1. Slow Roll-Off Filter (SRC Mode, fs = 48 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.011 dB PB 0 - 8.91 kHz (Note 68) 3.0 dB - 20.06 - kHz Stopband (Note 68) SB 42.57 - - kHz Passband Ripple PR 0.07 - +0.011 dB Stopband Attenuation (Note 69) SA 73.9 - - dB Group Delay (Note 70) GD - 27.6 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 20.0 kHz FR 3.21 - +0.03 dB Note 68. The passband and stopband frequencies scale with fs (system sampling rate). of 1 kHz. Note 69. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 70. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs]. 8-12-2. Slow Roll-Off Filter (SRC Mode, fs = 96 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 96 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.012 dB PB 0 - 17.88 kHz (Note 71) 3.0 dB - 40.15 - kHz Stopband (Note 71) SB 85.15 - - kHz Passband Ripple PR 0.07 - +0.012 dB Stopband Attenuation (Note 72) SA 73.9 - - dB Group Delay (Note 73) GD - 27.6 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 40.0 kHz FR 4.87 - +0.10 dB Note 71. The passband and stopband frequencies scale with fs (system sampling rate). of 1 kHz. Note 72. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 73. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 27 - 8-12-3. Slow Roll-Off Filter (SRC Mode, fs = 192 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 192 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.013 dB PB 0 - 35.89 kHz (Note 74) 3.0 dB - 80.34 - kHz Stopband (Note 74) SB 170.30 - - kHz Passband Ripple PR 0.07 - +0.013 dB Stopband Attenuation (Note 75) SA 73.9 - - dB Group Delay (Note 76) GD - 27.6 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 80.0 kHz FR 11.42 - +0.35 dB Note 74. The passband and stopband frequencies scale with fs (system sampling rate). of 1 kHz. Note 75. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 76. The calculated delay time is resulting from digital filtering. This i s the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 28 - 8-13. DAC Short Delay Sharp Roll-Off Filter Characteristics (SRC Mode) 8-13-1. Short Delay Sharp Roll-Off Filter (SRC Mode, fs = 48 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.004 to +0.198 dB PB 0 - 22.28 kHz (Note 77) 6.0 dB - 24.00 - kHz Stopband (Note 77) SB 26.21 - - kHz Passband Ripple PR 0.004 - +0.198 dB Stopband Attenuation (Note 78) SA 70.4 - - dB Group Delay (Note 79) GD - 7.3 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 20.0 kHz FR 0.12 - +0.10 dB Note 77. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 78. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 79. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs]. 8-13-2. Short Delay Sharp Roll-Off Filter (SRC Mode, fs = 96 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 96 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.001 to +0.202 dB PB 0 - 44.58 kHz (Note 80) 6.0 dB - 48.01 - kHz Stopband (Note 80) SB 52.44 - - kHz Passband Ripple PR 0.001 - +0.202 dB Stopband Attenuation (Note 81) SA 70.4 - - dB Group Delay (Note 81) GD - 7.3 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 40.0 kHz FR 1.72 - +0.11 dB Note 80. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 81. The bandwidth of the stopband attenuation value is from stopband to fs ( system sampling rate). Note 82. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 29 - 8-13-3. Short Delay Sharp Roll-Off Filter (SRC Mode, fs = 192 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 192 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.000 to +0.210 dB PB 0 - 89.22 kHz (Note 83) 6.0 dB - 96.02 - kHz Stopband (Note 83) SB 104.90 - - kHz Passband Ripple PR 0.000 - +0.210 dB Stopband Attenuation (Note 84) SA 70.4 - - dB Group Delay (Note 85) GD - 7.3 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 80.0 kHz FR 8.27 - +0.36 dB Note 83. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 84. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 85. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 30 - 8-14. DAC Short Delay Slow Roll-Off Filter Characteristics (SRC Mode) 8-14-1. Short Delay Slow Roll-Off Filter (SRC Mode, fs = 48 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.036 dB PB 0 - 10.19 kHz (Note 86) 3.0 dB - 20.48 - kHz Stopband (Note 86) SB 42.98 - - kHz Passband Ripple PR 0.07 - +0.036 dB Stopband Attenuation (Note 87) SA 76.3 - - dB Group Delay (Note 88) GD - 6.3 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 20.0 kHz FR 2.97 - +0.04 dB Note 86. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 87. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 88. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs]. 8-14-2. Short Delay Slow Roll-Off Filter (SRC Mode, fs = 96 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 96 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.038 dB PB 0 - 20.45 kHz (Note 89) 3.0 dB - 40.98 - kHz Stopband (Note 89) SB 85.80 - - kHz Passband Ripple PR 0.07 - +0.038 dB Stopband Attenuation (Note 90) SA 73.9 - - dB Group Delay (Note 91) GD - 6.3 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 40.0 kHz FR 4.63 - +0.10 dB Note 89. The passband and stopband frequencies scale with fs (system sampling rate). that of 1 kHz. Note 90. The bandwidth of the stopband attenuation value is fro m stopband to fs (system sampling rate). Note 91. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay a t audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 31 - 8-14-3. Short Delay Slow Roll-Off Filter (SRC Mode, fs = 192 kHz) (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 192 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”) Parameter Symbol Min. Typ. Max. Unit DAC Digital Filter (LPF): Passband 0.07 to +0.039 dB PB 0 - 41.05 kHz (Note 92) 3.0 dB - 82.02 - kHz Stopband (Note 92) SB 171.96 - - kHz Passband Ripple PR 0.07 - +0.039 dB Stopband Attenuation (Note 93) SA 76.2 - - dB Group Delay (Note 94) GD - 6.3 - 1/fs DAC Digital Filter (LPF) + DACANA (Headphone Amplifier): Frequency Response: 0 to 80.0 kHz FR 11.17 - +0.35 dB Note 92. The passband and stopband frequencies scale with fs (system sampling rate) that of 1 kHz. Note 93. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling rate). Note 94. The calculated delay time is resulting from digital filtering. This is the time from the input of MSB for L channel of SD TI to the output of an analog signal. The error of the delay at audio interface is within +1 [1/fs].

[AK4331] 018006903-E-00 2018/07 - 32 - 8-15. Digital Microphone Filter Characteristics (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; fs = 48 kHz) Parameter Symbol Min. Typ. Max. Unit Passband +0.18 to 0.09 dB PB 0 - 20.7 kHz (Note 95) 0.87 dB - 21.6 - kHz 3.0 dB - 22.8 - kHz Stopband (Note 95) SB 28.4 - - kHz Passband Ripple PR 0.09 - 0.18 dB Stopband Attenuation SA 65 - - dB Group Delay Distortion ΔGD - 0 - μsec Group Delay (Ts = 1/fs) (Note 96) GD - 12.5 - 1/fs Digital MIC HPF: HPFC[1:0] bits = “00” Frequency Response (Note 95) 3.0 dB FR - 29.8 - Hz Note 95. The passband and stopband frequencies scale with “fs” (system sampling rate). Each frequency response refers to that of 1 kHz. Note 96. The calculated delay time is resulting from digital filtering. This is the time from the 16/24/32-bit data is set to input register to the output of SDTO digital data.

[AK4331] 018006903-E-00 2018/07 - 33 - 8-16. DC Characteristics (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V, TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V, PMOSC bit = “0”) Note 97. MCKI/XTI, BCLK, LRCK, SDTI, SDTO, SCL, SDA, PDN, TEST1, TEST2, DMCLK, DMDAT pins. Note 98. Except for MCKI/XTI pin. Parameter Symbol Min. Typ. Max. Unit I/O Pins (Note 97) High-Level Input Voltage Except for DMDAT pin VIH1 70%TVDD - - V DMDAT pin VIH2 65%AVDD - - V Low-Level Input Voltage Except for DMDAT pin VIL1 - - 30%TVDD V DMDAT pin VIL2 - - 35%AVDD V High-Level Output Voltage Except for DMCLK pin (Iout = 200 μA) VOH1 TVDD  0.2 - - V DMCLK pin (Iout = 80 μA) VOH2 AVDD  0.4 - - V Low-Level Output Voltage Except for SDA pin, DMCLK pin (Iout = 200 μA) VOL1 - - 0.2 V DMCLK pin (Iout = 80 μA) VOL2 - - 0.4 V SDA pin 2 V < TVDD ≤ 3.6 V (Iout = 3 mA) VOL3 - - 0.4 V

1.65 V ≤ TVDD ≤ 2 V (Iout = 2 mA) VOL3 - - 20%TVDD V

Input Leakage Current (Note 98) Iin 5 - +5 μA

[AK4331] 018006903-E-00 2018/07 - 34 - 8-17. Switching Characteristics (Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V, TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; CL = 80 pF; unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit MCKI Input Frequency fMCK 0.256 - 24.576 MHz Pulse Width Low tMCKL 0.4 / fMCK - - nsec Pulse Width High tMCKH 0.4 / fMCK - - nsec X’tal Oscillator (XTI pin) Input Frequency fMCK 11.2896 - 24.576 MHz Audio Interface Timing Master Mode LRCK Output Timing Frequency (When not use Digital MIC) (Note 99) fs 8 - 192 kHz Frequency (When use Digital MIC) (Note 100) fs 8 - 96 kHz Duty LRDuty - 50 - % BCLK Output Timing Period (BCKO bit = “0”) tBCK - 1/(64fs) - nsec (BCKO bit = “1”) tBCK - 1/(32fs) - nsec Duty BCKDuty - 50 - % BCLK “↓” to LRCK Edge tBLR 20 - 20 nsec SDTI Setup Time tBDS 10 - - nsec SDTI Hold Time tBDH 10 - - nsec Delay time from BCLK Falling to SDTO tBOD 40 - 40 nsec Slave Mode LRCK Input Timing Frequency (When not use Digital MIC) (Note 99) fs 8 - 192 kHz Frequency (When use Digital MIC) (Note 100) fs 8 - 96 kHz Duty LRDuty 45 50 55 % BCLK Input Timing Frequency (When not use Digital MIC) (Note 101) fBCK 0.256 - 12.288 or 512fs MHz Frequency (When use Digital MIC) (Note 102) fBCK 0.256 - 6.144 or 512fs MHz Pulse Width Low tBCKL 0.4 / tBCK - - nsec Pulse Width High tBCKH 0.4 / tBCK - - nsec BCLK “↑” to LRCK Edge tBLR 20 - - nsec LRCK Edge to BCLK “↑” tLRB 20 - - nsec SDTI Setup Time tBDS 10 - - nsec SDTI Hold Time tBDH 10 - - nsec Delay time from BCLK Falling to SDTO tBOD - - 40 nsec Note 99. Supported sampling rate are 8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 64 k, 88.2 k, 96 k, 128 k, 176.4 k and 192 kHz. Note 100. Supported sampling rate are 8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 64 k, 88.2 k and 96 kHz. Note 101. The maximum value is lower frequency between “12.288 MHz” and “512fs”. Note 102. The maximum value is lower frequency between “6.144 MHz” and “512fs”.

[AK4331] 018006903-E-00 2018/07 - 35 - Parameter Symbol Min. Typ. Max. Unit Digital MIC Interface Timing: CL = 100 pF DMCLK Output Timing Period tSCK - 1/(64fs) - nsec Rising Time tSRise - - 10 nsec Falling Time tSFall - - 10 nsec Duty Cycle dSCK 45 50 55 % Audio Interface Timing (DMCLK, DMDAT pins) DMDAT Setup Time tDMS 50 - - nsec DMDAT Hold Time tDMH 0 - - nsec Control Interface Timing (I2C-bus mode): (Note 103) SCL Clock Frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - μsec Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - μsec Clock Low Time tLOW 1.3 - - μsec Clock High Time tHIGH 0.6 - - μsec Setup Time for Repeated Start Condition tSU:STA 0.6 - - μsec SDA Hold Time from SCL Falling (Note 104) tHD:DAT 0 - - μsec SDA Setup Time from SCL Rising tSU:DAT 0.1 - - μsec Rise Time of Both SDA and SCL Lines tR - - 0.3 μsec Fall Time of Both SDA and SCL Lines tF - - 0.3 μsec Setup Time for Stop Condition tSU:STO 0.6 - - μsec Capacitive Load on Bus Cb - - 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 nsec Power-Down & Reset Timing PDN Accept Pulse Width (Note 105) tPDN 1 - - msec PDN Reject Pulse Width (Note 105) tRPD - - 50 nsec PMDMx bit = “1” to SDTO Valid (Note 106) ADRST[1:0] bits = “00” ADRST[1:0] bits = “01” ADRST[1:0] bits = “10” ADRST[1:0] bits = “11” tPDV tPDV tPDV tPDV 1059 267 2115 531 1/fs 1/fs 1/fs 1/fs Note 103. I2C-bus is a registered trademark of NXP B.V. Note 104. Data must be held long enough to bridge the 300 nsec-transition time of SCL. Note 105. The AK4331 will be reset by bringing the PDN pin = “L”. The PDN pin must held “L” for longer period than or equal to tPDN (Min.). The AK4331 will not be reset by the “L” pulse shorter than or equal to tRPD (Max.). Note 106. This is the time from PMDMx bit = “1” to the output of SDTO digital data.

Figure 9. Digital Microphone Interface Timing

frequency are set by registers shown in Table 2. Table 2. Setting Registers for Master Clock Frequency and Sampling Frequency Table 3. Master / Slave Mode Select

0 Slave Mode (default)

1 Master Mode

frequency is changed or SRCMCLK / DACCLK is stopped.

SRC, DAC, Headphone Amplifier (PLL, Charge Pump) Power-Down
Clock Mode of ACPU Setting (In case clock mode of ACPU is master, switch to slave.)
Clock Mode of ACPU Setting (In case clock mode of ACPU is slave, switch to master.)
SRC, DAC, Headphone Amplifier (PLL, Charge Pump) Power-Up

Figure 10. Internal configure diagram of AK4331 Table 4. Setting of Clock Select (x: Do not Care, S: Slave, M: Master) Note 107. Operation is only guaranteed with clock combinations in Table 4.

Table 5. Setting of Master Clock Frequency (SRC Bypass Mode) Table 6. Setting of Sampling Frequency (SRC Bypass Mode, N/A: Not available)

Depending on setting of PLL’s divider, the sampling frequency may differ.

Please set PLD[15:0] and PLM[15:0] bits precisely.

Table 7. Setting of Master Clock Frequency (SRC Mode: FSI) Table 8. Setting of Sampling Frequency (SRC Mode, N/A: Not available)

Depending on setting of PLL’s divider, the sampling frequency may differ.

Please set PLD[15:0] and PLM[15:0] bits precisely.

Table 9. Setting of Master Clock Frequency (SRC Mode: FSO) Table 10. Setting of Sampling Frequency (SRC Mode: FSO, N/A: Not available)

Depending on setting of PLL’s divider, the sampling frequency may differ.

Please set PLD[15:0] and PLM[15:0] bits precisely. PMHPL, PMHPR, PMDML and PMDMR bits) must be “0” when PMTIM bit = “0”. Table 11. Master Counter Power Control

0 Disable (default)

1 Enable

the range from 76.8 kHz to 768 kHz. Table 12. PLLCLK Setting Figure 15. PLL Block Diagram PLL can be powered down by a control register setting. Table 13. PLL Power Control

0 Power-Down (default)

1 Power-Up

must be set at PMTIM bit = “0”. Table 14. PLL Clock Source Select

0 MCKI/XTI pin (default)

1 BCLK pin

reference clock by dividing by (PLD + 1). PLD[15:0] bits must be set at PMTIM bit = “0”. Table 15. PLL Reference Clock Divider Note 108. The reference clock divided by PLD should be set in the range from 76.8 kHz to 768 kHz. used as PLL feedback clock. PLM[15:0] bits must be set at PMTIM bit = “0”. Table 16. PLL Feedback Clock Divider must be set at PMPLL bit = “0”. Table 17. PLL Internal Mode Setting

MDIV[3:0] bits control PLLCLK divider. MDIV[3:0] bits must be set at PMTIM bit = “0”. Table 18. PLLCLK Divider Setting Note 109. When set each registers as following, divider value is set to 1.5 at MDIV[3:0] bits = 0H.

Table 19. PLL Setting Example (PLL reference source: MCKI) Note 110. At the case of CM[1:0] bits and CM2[1:0] bits are set to “01” (512fs).

Table 20. PLL Setting Example (PLL reference source: BCLK)

Connection to Digital Microphone

resistor (R) should be connected to the DMDAT pin to avoid floating state. not support quad speed mode (fs ≥ 128 kHz). Figure 19. Connection Example of Stereo Digital Microphone

Figure 20. Connection Example of Mono Digital Microphone input if DMCLK signal = “L”. The DMCLK pin outputs “L” when DCLKE bit = “0”, and only supports 64fs. bit must be set at PMDML/R bits = “0”. Table 21. Data Input/Output Timing with Digital Microphone

0 Rch Lch (default)

1 Lch Rch

Figure 21. Data Input/Output Timing with Digital Microphone (DCLKP bit = “0”) Figure 22. Data Input/Output Timing with Digital Microphone (DCLKP bit = “1”)

A digital High Pass Filter (HPF) is integrated for DC offset cancellation of th e digital microphone input. HPF enable). HPFC[1:0] bits must be set at PMDML/R bits = “0”. Table 22. Digital Microphone HPF Cut-Off Frequency PMDML and PMDMR bits set On/Off and mono/stereo operation of the digital microphone. Table 23. Digital Microphone Mono/Stereo Select must be set at PMDML/R bits = “0”. discard the initial data of the digital microphone if this offset causes a problem. Table 24. Digital Microphone Initialization Cycle

block or not. SV[2:0] bits and SVE bit must be set when PMDML/R bits = “0”. Table 25. Side Tone Control Table 26. Side Tone Volume Setting (N/A: Not available)

Mode, DADFSEL bit must be set to “0” . In case of SRC Mode, DADFSEL bit must be set to “1”. Table 27. DAC Digital Filter Setting (SRC Bypass Mode) Table 28. DAC Digital Filter Setting (SRC Mode) Table 29. DAC L/R Channel Input Signal Select Table 30. DAC L/R Channel Input Signal Polarity Select

0 Normal (default)

1 Inverting

immediately by setting registers. level. When OVOLCN bit = “0”, the OVL[4:0] bits control both L channel and R channel attenuation levels. Table 31. Digital Volume Setting

Table 32. Charge Pump Mode Setting (N/A: Not available) should be set before PMHPL bit or PMHPR bit is set to “1”. passed after VDD mode hold time is finished. Table 33. VDD Mode Holding Period Setting (x: Do not Care) VDD if the detection counter of 1/2VDD mode is finished and also the VDD mode hold period is passed.

Figure 25. Transition to 1/2VDD Mode from VDD Mode Table 34. 1/2VDD Detection Period (Minimum frequency that is not detected)

timeout period is set by HPTM[2:0] bits (Table 36). the next zero crossing point will be applied. Table 35. Headphone Amplifier Volume Setting Table 36. Headphone Volume Zero Cross Timeout Setting (x: Do not care) because there is a possibility that the headphone amplifier oscillates. Figure 26. Example of Headphone Amplifier Oscillation Prevention Circuit

PMHPL/R bits. A wait time from DAC power-up to headphone power-up is not necessary. executed. The gain setting (HPG[2:0] bits) should be made before PMHPL bit or PMHPR bit is set to “1”. PMHPL bit or PMHPR bit = “1” is not necessary. Table 37. Headphone Output Status (x: Do not Care) HPL pin and the HPR pin when CP1, CP2, LDO1P and LDO1N are powered down. To avoid pop noise, HPG[2:0] bits setting should be same at power-up and power-down of headphone. (HPGND) when the headphone amplifier is powered up. The power-down is executed immediately. Table 38. Headphone Power-Up Time state if all causes are cleared.

overcurrent protection will be off and the LDO1P and LDO1N circuits will return to normal operation. Table 39. Input/Output Voltage and Operation Block of the Charge Pump Table 40. Input/Output Voltage and Operation Block of the LDO

(FSO/FSI) is 0.98 to 6.02. PMSRC bit controls power up/down of the SRC. Examples of supported sampling rate are shown below. Table 41. Up-Sampling Examples the MCKI/XTI pin and PLLO. The SRC can be bypassed by setting SELDAIN bit = “0”. Table 42. SRC Power Management Table 43. DAC and Charge Pump Clock Mode Setting

0 PLLO (default)

1 MCKI/XTI pin

Table 44. SRC Clock Mode Setting Note 114. SRCCKS bit and XCKSEL bit must be same value at SRC Bypass Mode (SELDAIN bit = “0”).

oscillator, the master clock is set by CM2[1:0] bits and the sampling frequency is set by FS2[4:0] bits. SELDAIN bit. SELDAIN bit must be set at PMSRC bit = “0”. Figure 27. Input Selector for DAC Table 45. DAC Data Path Setting

0 SRC Bypass Mode (default)

1 SRC Mode

Figure 28. Sequence of Changing SRC System Clock

Table 46. Soft Mute Block Power Management (N/A: Not available) is effective for changing the signal source without stopping the signal transmission. Figure 29. Soft Mute Manual Mode level returns to 0 dB by the same cycle. Table 47. Soft Mute Cycle Setting

DL[1:0] bits must be set at PMTIM bit = “0”. Table 48. Digital Audio Interface Format Setting

0 I2S Compatible (default)

1 MSB justified

Table 49. Data Length Setting (x: Do not Care, N/A: Not available) Figure 32. I2S Compatible Format (DIF bit = “0”) Figure 33. MSB justified format (DIF bit= “1”)

Figure 42. Bit Transfer (I2C-bus)

[AK4331] 018006903-E-00 2018/07 - 76 - < Power-Up Sequence Example > (1) Set the PDN pin from “L” to “H” after turning on all power supplies. In this case, 1 msec or more “L” time is needed for a certain reset. (2) After all power supplies are On, MCKI, BCLK and LRCK should be input before powering up PLL or CP1. (3) Set the PDN pin = “H” to release the power -down. Register access will be va lid in 1 ms ec at maximum. However, a wait time of 2 msec is needed to access PMTIM bit and power management bits of the analog circuit (PMCP1 bit, PMCP2 bit, PMLDO1P bit, PMLDO1N bit, PMDA bit, PMHPL bit, PMHPR bit and PMPLL bit) until the analog circuit is powered up. (4) Set DAC initial settings. (Write 02H data into Address 26H and write C0H data into Address 27H) (5) Set sampling frequency (FS[4:0] bits) and the input signal path of the DAC. (LDACL bit = RDACR bit = “0” → “1”) (6) Set headphone amplifier volume by HPG[2:0] bits. (7) In case of using PLL, power -up PLL (PMPLL bit = “0” → “1”) and wait 2 ms ec for PLL output stabilization. (8) Start internal master counter. (PMTIM bit = “0” → “1”) PMCP1 bit, PMCP2 bit, PMLDO1P bit, PMLDO1N bit, PMDA bit, PMHPL bit and PMHPR bit must be powered up after PMTIM bit = “1”. (9) Power-up CP1 (PMCP1 bit = “0” → “1”) and wait 6.5 msec ( Note 115) for CP1 output voltage stabilization. (10) Power-up LDO1P and LDO1N (PMLDO1P bit = PMLDO1N bit = “0” → “1”) and wait 0.5 msec (Note 115) for each LDO output voltage stabilization. (11) Power-up DAC (PMDA bit = “0” → “1”) (12) Power-up CP2 (PMCP2 bit = “0” → “1”) and wait 4.5 msec (Note 115) for CP2 output voltage stabilization. (13) Power-up headphone amplifier (PMHPL bit = PMHPR bit = “0” → “1”) The power-up time of headphone amplifier is 23.9 msec (@ fs = 48 kHz). The HPL pin and the HPR pin output 0 V until the headphone amplifier is powered up. Note 115. Refer to “8-3. Charge Pump & LDO Circuit Power-Up Time”

[AK4331] 018006903-E-00 2018/07 - 78 - 9-22. Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 0 0 0 PMOSC 0 0 PMTIM PMPLL 01H Power Management 2 0 0 PMLDO1N PMLDO1P 0 0 PMCP2 PMCP1 02H Power Management 3 PMSRC 0 PMSM SELSM 0 0 0 PMDA 03H Power Management 4 0 LVDTM[2:0] CPMODE[1:0] PMHPR PMHPL 04H Output Mode Setting LVDSEL[1:0] VDDTM[3:0] HPRHZ HPLHZ 05H Clock Mode Select 0 CM[1:0] FS[4:0] 06H Digital Filter Select DASD DASL DADFSEL 0 0 0 0 0 07H DAC Mono Mixing INVR MDACR RDACR LDACR INVL MDACL RDACL LDACL 08H SRC Clock Select 0 CM2[1:0] FS2[4:0] 09H Soft Mute Setting 0 0 0 0 SMT[1:0] SAUTO SMUTE 0AH SRC Setting 0 XCKSEL 0 0 0 0 SELDAIN 0 0BH Lch Output Volume OVOLCN 0 0 OVL[4:0] 0CH Rch Output Volume 0 0 0 OVR[4:0] 0DH HP Volume Control HPTM[2:0] 1 0 HPG[2:0] 0EH PLL CLK Source Select 0 0 0 PLLMD 0 0 0 PLS 0FH PLL Ref CLK Divider 1 PLD[15:8] 10H PLL Ref CLK Divider 2 PLD[7:0] 11H PLL FB CLK Divider 1 PLM[15:8] 12H PLL FB CLK Divider 2 PLM[7:0] 13H SRC CLK Source Select 0 0 0 0 0 0 0 SRCCKS 14H PLLCLK Divider 0 0 0 0 MDIV[3:0] 15H Audio Interface Format DEVICEID[2:0] MS BCKO DIF DL[1:0] 16H Digital MIC PMDMR PMDML DCLKE DCLKP 0 0 ADRST[1:0] 17H Side Tone Volume Control SV[2:0] SVE 0 HPFC[1:0] HPFADN 26H DAC Adjustment 1 T8 T7 T6 T5 T4 T3 T2 T1 27H DAC Adjustment 2 T16 T15 T14 T13 T12 T11 T10 T9 29H Mode Control 0 0 0 0 0 0 HPMD[1:0] Note 116. PDN pin = “L” resets the registers to their default values. Note 117. The bits defined as “0” must contain a “0” value. Note 118. The bits defined as “1” must contain a “1” value. Note 119. Writing access to 18H to 25H, 28H, 2AH to FFH is prohibited.

[AK4331] 018006903-E-00 2018/07 - 79 - 9-23. Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 0 0 0 PMOSC 0 0 PMTIM PMPLL R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMPLL: PLL Power Management 0: Power-Down (default) 1: Power-Up PMTIM: Synchronization Control Power Management 0: Disable (default) 1: Enable PMOSC: Crystal Oscillator Power Management 0: Power-Down (default) 1: Power-Up Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Power Management 2 0 0 PMLDO1N PMLDO1P 0 0 PMCP2 PMCP1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMCP1: Charge Pump 1 Power Management 0: Power-Down (default) 1: Power-Up PMCP2: Charge Pump 2 Power Management 0: Power-Down (default) 1: Power-Up PMLDO1P: LDO1P Power Management 0: Power-Down (default) 1: Power-Up PMLDO1N: LDO1N Power Management 0: Power-Down (default) 1: Power-Up

[AK4331] 018006903-E-00 2018/07 - 80 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Power Management 3 PMSRC 0 PMSM SELSM 0 0 0 PMDA R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMDA: DAC Power Management 0: Power-Down (default) 1: Power-Up PMSM, SELSM: Soft Mute Power Management (Table 46) “0, 0”: Power-Down (default) “1, 1”: Power-Up PMSRC: SRC Power Management 0: Power-Down (default) 1: Power-Up Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Power Management 4 0 LVDTM[2:0] CPMODE[1:0] PMHPR PMHPL R/W R/W R/W R/W R/W R/W Default 0 000 00 0 0 PMHPL/R: Headphone Amplifier L/R Channel Power Management 0: Power-Down (default) 1: Power-Up CPMODE[1:0]: Charge Pump Mode Control (Table 32) Default: “00” (Automatic Switching Mode) LVDTM[2:0]: Class-G 1/2VDD Mode Detection Time Setting (Table 34) Default: “000” (64/fs)

[AK4331] 018006903-E-00 2018/07 - 81 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Output Mode Setting LVDSEL[1:0] VDDTM[3:0] HPRHZ HPLHZ R/W R/W R/W R/W R/W Default 00 0000 0 0 HPRHZ/HPLHZ: GND Switch Setting for Headphone Amplifier Output 0: Pull-Down by 4Ω (Typ.) (default) 1: Pull-Down by 95 kΩ (Typ.) VDDTM[3:0]: Class-G VDD Hold Time Setting (Table 33) Default: “0000” (1024/fs) LVDSEL[1:0]: Switching Threshold between VDD Mode and 1/2VDD Mode of CP2 00: VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 16Ω) 1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 16Ω) (Default: Assuming when connecting a 16Ω Headphone) 01: VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 32Ω) 1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 32Ω) (Assuming when connecting a 32Ω Headphone or more) 10: VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 11Ω) 1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 11Ω) (Assuming when connecting a 11Ω Headphone) 11: VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 8Ω) 1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 8Ω) (Assuming when connecting a 8Ω Headphone) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Clock Mode Select 0 CM[1:0] FS[4:0] R/W R/W R/W R/W Default 0 00 00000 FS[4:0]: Sampling Frequency Setting (Table 6 @SRC Bypass Mode, Table 8 @SRC Mode) Default: “00000” (fs = 8 kHz) CM[1:0]: Master Clock Frequency Setting (Table 5 @SRC Bypass Mode, Table 7 @SRC Mode) Default: “00” (256fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Digital Filter Select DASD DASL DADFSEL 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DADFSEL: Digital Filter Setting for DAC Compensation (Table 27, Table 28) 0: In case of SRC Bypass Mode (default) 1: In case of SRC Mode DASD, DASL: DAC Digital Filter Mode Setting (Table 27, Table 28) Default: “0, 0” (Sharp Roll-Off Filter)

[AK4331] 018006903-E-00 2018/07 - 82 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H DAC Mono Mixing INVR MDACR RDACR LDACR INVL MDACL RDACL LDACL R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 MDACL, RDACL, LDACL: DAC L Channel Input Signal Select (Table 29) Default: “0, 0, 0” (MUTE) MDACR, RDACR, LDACR: DAC R Channel Input Signal Select (Table 29) Default: “0, 0, 0” (MUTE) INVL/R: DAC Input Signal Polarity Select 0: Normal (default) 1: Inverting Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H SRC Clock Select 0 CM2[1:0] FS2[4:0] R/W R/W R/W R/W Default 0 00 00000 FS2[4:0]: Sampling Frequency Setting for SRC Output (Table 10) Default: “00000” (fs = 8 kHz) CM2[1:0]: Master Clock Frequency Setting for SRC Output (Table 9) Default: “00” (256fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H Soft Mute Setting 0 0 0 0 SMT[1:0] SAUTO SMUTE R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 00 0 0 SMUTE: Soft Mute Enable 0: Disable (default) 1: Enable SAUTO: Semi-Auto Mode Enable 0: Disable (default) 1: Enable SMT[1:0]: Soft Mute Cycle Setting (Table 47) Default: “00”, 1024/FSO

[AK4331] 018006903-E-00 2018/07 - 83 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH SRC Setting 0 XCKSEL 0 0 0 0 SELDAIN 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SELDAIN: DAC Input Data Select (Table 45) Default: “0” (SDTI pin; SRC Bypass Mode) XCKSEL: DAC and Charge Pump Operation Clock (Table 43) 0: PLLO (default) 1: MCKI/XTI pin Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH Lch Output Volume OVOLCN 0 0 OVL[4:0] 0CH Rch Output Volume 0 0 0 OVR[4:0] R/W R/W R/W R/W R/W Default 0 0 0 19H OVL[4:0]: DAC L Channel Digital Volume Control; +3 dB to 12 dB & Mute, 0.5 dB step (Table 31) OVR[4:0]: DAC R Channel Digital Volume Control; +3 dB to 12 dB & Mute, 0.5 dB step (Table 31) Default: 19H (0 dB) OVOLCN: Digital Volume Control 0: Dependent (default) 1: Independent OVL[4:0] bits control digital volume of both L and R channels when OVOLCN bit = “0”. In this case, the value of OVL[4:0] bits will not be written to OVR[4:0] bits. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH HP Volume Control HPTM[2:0] 1 0 HPG[2:0] R/W R/W R/W R/W R/W Default 011 1 0 101 HPG[2:0]: Headphone Amplifier Analog Volume Control; +4 dB to 10 dB, 2 dB step (Table 35) Default: “101” (0 dB) HPTM[2:0]: Zero Cross Time Output Period Setting for Analog Volume of Headphone Amplifier (Table 36) Default: “011” (1024/fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH PLL CLK Source Select 0 0 0 PLLMD 0 0 0 PLS R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PLS: PLL Clock Source Select (Table 14) Default: “0” (MCKI/XTI pin) PLLMD: PLL Internal Mode Setting (Table 17) Default: “0”

[AK4331] 018006903-E-00 2018/07 - 84 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH PLL Ref CLK Divider 1 PLD[15:8] 10H PLL Ref CLK Divider 2 PLD[7:0] R/W R/W Default 0000H PLD[15:0]: PLL Reference Clock Divider Setting (Table 15) Default: 0000H Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 11H PLL FB CLK Divider 1 PLM[15:8] 12H PLL FB CLK Divider 2 PLM[7:0] R/W R/W Default 0000H PLM[15:0]: PLL Feedback Clock Divider Setting (Table 16) Default: 0000H Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 13H SRC CLK Source Select 0 0 0 0 0 0 0 SRCCKS R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SRCCKS: SRC Clock Source Select (Table 44) 0: PLLO (default) 1: MCKI/XTI pin Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 14H PLLCLK Divider 0 0 0 0 MDIV[3:0] R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0H MDIV[3:0]: PLLCLK Divider Setting (Table 18) Default: 0H (Divided by 1)

[AK4331] 018006903-E-00 2018/07 - 85 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 15H Audio Interface Format DEVICEID[2:0] MS BCKO DIF DL[1:0] R/W R R/W R/W R/W R/W Default 111 0 0 0 00 DL[1:0]: Data Length Setting (Table 49) Default: “00” (24-bit linear) DIF: Digital Audio Interface Format Setting (Table 48) 0: I2S Compatible (default) 1: MSB justified BCKO: BCLK Output Frequency 0: 64fs (Default) 1: 32fs MS: Master/Slave Mode Setting (Table 3) 0: Slave Mode (default) 1: Master Mode DEVICEID[2:0]: Device ID Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 16H Digital MIC PMDMR PMDML DCLKE DCLKP 0 0 ADRST[1:0] R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 00 ADRST[1:0]: Digital Microphone Initialization Cycle Setting (Table 24) Default: “00” (1059/fs) DCLKP: Data Latching Edge Select (Table 21) 0: L channel data is latched on the DMCLK rising edge (“↑”). (default) 1: L channel data is latched on the DMCLK falling edge (“↓”). DCLKE: DMCLK pin Output Clock Control 0: “L” Output (default) 1: 64fs Output PMDML/R: Input Signal Select with Digital Microphone Power Management (Table 23) 0: Power-Down (default) 1: Power-Up

[AK4331] 018006903-E-00 2018/07 - 86 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 17H Side Tone Volume Control SV[2:0] SVE 0 HPFC[1:0] HPFADN R/W R/W R/W R/W R/W R/W Default 000 0 0 00 0 HPFADN: Digital Microphone HPF Control 0: On (default) 1: Off HPFC[1:0]: Cut-off frequency of Digital Microphone HPF (Table 22) Default: “00” (29.8 Hz @fs = 48 kHz) SVE: Side Tone Additional Control (Table 25) 0: Disable (default) 1: Enable SV[2:0]: Side Tone Volume Control; 0 dB to 24 dB, 6 dB step (Table 26) Default: “000” (0 dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 26H DAC Adjustment 1 T8 T7 T6 T5 T4 T3 T2 T1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 0 1 1 0 0 * 02H data must be written to DAC Adjustment 1 (Addr. 26H) before analog blocks (CP1, CP2, LDO1, DAC, headphone amplifier and PLL) are powered up. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 27H DAC Adjustment 2 T16 T15 T14 T13 T12 T11 T10 T9 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 0 0 0 0 0 0 * C0H data must be written to DAC Adjustment 2 (Addr. 27H) before analog blocks (CP1, CP2, LDO1, DAC, headphone amplifier and PLL) are powered up. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 29H Mode Control 0 0 0 0 0 0 HPMD[1:0] R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 00 HPMD[1:0]: Headphone Amplifier Operation Mode Setting (N/A: Not available) (Table 5, Table 9) 00: In case of fs = 8 to 48 kHz (SRC Bypass Mode) / FSO = 8 to 48 kHz (SRC Mode) (default) 01: N/A 10: N/A 11: In case of fs = 64 to 192 kHz (SRC Bypass Mode) / FSO = 64 to 192 kHz (SRC Mode)

Recommended External Circuits

Figure 45. System Connection Diagram (When using X’tal Oscillator and Digital Microphone) *1: When the AK4331 is in master mode, a pull-down resistor (e.g. 100 kΩ) is needed.

[AK4331] 018006903-E-00 2018/07 - 88 - 1. Grounding and Power Supply Decoupling The AK 4331 requires careful attention to power supply and grounding arrangements. The PDN pin should be held “L” when power supplies are tuning on. AVDD should be powered up before or at the same time of CVDD. Power-up sequence of TVDD and LVDD is not critical. The PDN pin is allowed to be “H” after all power supplies are applied and settled. To power down the AK4331, set the PDN pin to “L” and power down CVDD before or at the same time of AVDD. Pow er-down sequence of LVDD and TVDD is not critical. To avoid pop noise on analog output when power -up/down, the AK4331 should be operated along the following recommended power-up/down sequence. 1) Power-up - The PDN pin should be held “L” when power suppl ies are turning on. The AK 4331 can be reset by keeping the PDN pin “L” for 1 msec or longer after all power supplies are applied and settled. Then release the reset by setting the PDN pin to “H”. 2) Power-down - Each of power supplies can be powered OFF after the PDN pin is set to “L”. VSS1, VSS2 and VSS3 of the AK4331 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close the power supply pins as possible. Especially, the small value ceramic capacitor is to be closest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2 μF ceramic capacitor attached between the VCOM pin eliminates the effects of high frequency noise. No load current is allowed to be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4331. 3. Charge Pump and LDO Circuits Capacitors for CP1 block (connected between the CP1 pin and the CN1 pin, between the VEE1 pin and the VSS2 pin) and for CP2 block (connected between the CP2A pin and the CN2A pin, between the CP2B pin and the CN2B pin, between the VCC2 pin and the VSS2 pin, between the VEE2 pin and the VSS2 pin) should be low ESR 2.2 μF ±50%. Capacitors for LDO1P block (connected between the RAVDD pin and the VSS1 pin) and for LDO1N block (connected between the RVEE pin and the VSS1 pin) should be low ESR from 1.0 μF ±50% to 4.7 μF ±50%. These capacitors must be connected as close as possible to the pins. No load current may be drawn from the Positive / Negative Power Output pin (VEE1, RAVDD, RVEE, VCC2 and VEE2 pins). 4. Analog Outputs Headphone outputs are single-ended and centered at HPGND (0 V). They should be directly connected to a headphone without AC coupling.

[AK4331] 018006903-E-00 2018/07 - 89 - 11. Package 11-1. Outline Dimensions 36-pin CSP (Unit: mm) Bottom View Top View A C B D E F 36 x (0.204 ~ 0.264)  0.015 C M A B B A 0.4 0.2 0.4 0.2 (0.025 ±0.004) 2.533 ±0.025 2.371 ±0.025 C 0.107 ~ 0.167 0.519 0.046 0.382 0.016 A 0.03 C 11-2. Material and Lead Finish Package molding compound: Epoxy Resign, Halogen Free Solder ball material: SnAgCu

[AK4331] 018006903-E-00 2018/07 - 90 - 11-3. Marking 4331 XXXX A XXXX: Date code (4 digits) Pin #A1 indication 12. Ordering Guide AK4331ECB 40 to 85C 36-pin CSP (0.4 mm pitch) AKD4331 Evaluation board for AK4331

[AK4331] 018006903-E-00 2018/07 - 91 - 13. Revision History Date (Y/M/D) Revision Reason Page Contents 18/07/12 00 First Edition IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment use d in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices rela ted to electric power, and equipment used in finance -related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible fo r complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you sho uld comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM.

Product Information

AK4331 specifications and overview.

Summary

Low-Power Advanced 32-bit DAC with HP/SRC

Description

Low-Power Advanced 32-bit DAC with HP/SRC

Source title AK4331 Datasheet(PDF) - Asahi Kasei Microsystems

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