AK4385 AKM | Alldatasheet

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[AK4385] MS0246-E-00 - 1 - GENERAL DESCRIPTION The AK4385 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4385 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4385 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate make this part ideal for a wide range of applications including DVD-Audio. The AK4385 is offered in a space saving 16pin TSSOP package.

FEATURES

† Sampling Rate Ranging from 8kHz to 192kHz † 128 times Oversampling (Normal Speed Mode) † 64 times Oversampling (Double Speed Mode) † 32 times Oversampling (Quad Speed Mode) † 24-Bit 8 times FIR Digital Filter † On chip SCF † Digital de-emphasis for 32k, 44.1k and 48kHz sampling † Soft mute † Digital Attenuator (Linear 256 steps) † I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S † Master clock: 256fs, 384fs, 512fs or 768fs (Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (Double Speed Mode) 128fs, 192fs (Quad Speed Mode) † THD+N: -94dB † Dynamic Range: 108dB † High Tolerance to Clock Jitter † Power supply: 4.75 to 5.25V † Very Small Package: 16pin TSSOP (6.4mm x 5.0mm) † AK4381 Pin Compatible LRCK BICK SDTI Audio Data Interface MCLK PDN Modulator AOUTL+ Interpolator SCF AOUTR+ SCF VDD VSS De-emphasis Control µP Interface Clock Divider CSN CCLK CDTI DZFR Modulator Interpolator AOUTL- AOUTR- DZFL 108dB 192kHz 24-Bit 2ch ∆Σ DAC AK4385

[AK4385] MS0246-E-00 - 2 - „ Ordering Guide AK4385VT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch) AKD4385 Evaluation Board for AK4385 „ Pin Layout MCLK LRCK BICK CSN CCLK CDTI Top View DZFL DZFR VSS VDD AOUTL+ AOUTL- AOUTR+ AOUTR- PDN SDTI PIN/FUNCTION No. Pin Name I/O Function MCLK I Master Clock Input Pin An external TTL clock should be input on this pin. BICK I Audio Serial Data Clock Pin SDTI I Audio Serial Data Input Pin LRCK I L/R Clock Pin PDN I Power-Down Mode Pin When at “L”, the AK4385 is in the power-down mode and is held in reset. The AK4385 should always be reset upon power-up. CSN I Chip Select Pin CCLK I Control Data Input Pin CDTI I Control Data Input Pin in serial mode AOUTR- O Rch Negative Analog Output Pin AOUTR+ O Rch Positive Analog Output Pin AOUTL- O Lch Negative Analog Output Pin AOUTL+ O Lch Positive Analog Output Pin VSS Ground Pin VDD Power Supply Pin DZFR O Rch Data Zero Input Detect Pin DZFL O Lch Data Zero Input Detect Pin Note: All input pins should not be left floating.

[AK4385] MS0246-E-00 - 3 - ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 1) Parameter Symbol min max Units Power Supply VDD -0.3 6.0 V Input Current (any pins except for supplies) IIN ±10 mA Input Voltage VIND -0.3 VDD+0.3 V Ambient Operating Temperature Ta -40 Storage Temperature Tstg -65 150 Note: 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Symbol min typ max Units Power Supply VDD 4.75 5.0 5.25 V *AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4385] MS0246-E-00 - 4 - ANALOG CHARACTERISTICS (Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz ∼ 20kHz; RL ≥4kΩ; unless otherwise specified) Parameter min typ max Units Resolution Bits Dynamic Characteristics (Note 3) fs=44.1kHz BW=20kHz 0dBFS -60dBFS -94 -44 -84 dB dB fs=96kHz BW=40kHz 0dBFS -60dBFS -92 -41 dB dB THD+N fs=192kHz BW=40kHz 0dBFS -60dBFS -92 -41 dB dB Dynamic Range (-60dBFS with A-weighted) (Note 4) 100 108 dB S/N (A-weighted) (Note 5) 100 108 dB Interchannel Isolation (1kHz) 110 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Gain Drift 100 ppm/°C Output Voltage (Note 6) ±2.55 ±2.75 ±2.95 Vpp Load Resistance (Note 7) kΩ Power Supplies Power Supply Current (VDD) Normal Operation (PDN = “H”, fs≤96kHz) Normal Operation (PDN = “H”, fs=192kHz) Power-Down Mode (PDN = “L”) (Note 8) 100 mA mA µA Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual. 4. 100dB at 16bit data. 5. S/N does not depend on input bit length. 6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF, AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=±2.75Vpp × VREF/5. 7. For AC-load. 4kΩ for DC-load. 8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.

[AK4385] MS0246-E-00 - 5 - SHARP ROLL-OFF FILTER CHARACTERISTICS (Ta = 25°C; VDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Symbol min typ max Units Digital filter Passband ±0.05dB (Note 9) -6.0dB PB 22.05 20.0 kHz kHz Stopband (Note 9) SB 24.1 kHz Passband Ripple PR ± 0.02 dB Stopband Attenuation SA dB Group Delay (Note 10) GD 19.3 1/fs Digital Filter + SCF Frequency Response 20.0kHz 40.0kHz 80.0kHz fs=44.1kHz fs=96kHz fs=192kHz FR FR FR ± 0.2 ± 0.3 +0.1/-0.6 dB dB dB Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs. 10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. SLOW ROLL-OFF FILTER CHARACTERISTICS (Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”) Parameter Symbol min typ max Units Digital Filter Passband ±0.04dB (Note 11) -3.0dB PB 18.2 8.1 kHz kHz Stopband (Note 11) SB 39.2 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA dB Group Delay (Note 10) GD 19.3 1/fs Digital Filter + SCF Frequency Response 20.0kHz 40.0kHz 80.0kHz fs=44.kHz fs=96kHz fs=192kHz FR FR FR +0/-5 +0/-4 +0.1/-5 dB dB dB Note: 11. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs. DC CHARACTERISTICS (Ta=25°C; VDD=4.75 ∼ 5.25V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 0.8 V V High-Level Output Voltage (Iout=-80µA) Low-Level Output Voltage (Iout=80µA) VOH VOL VDD-0.4 0.4 V V Input Leakage Current Iin ± 10 µA

[AK4385] MS0246-E-00 - 6 - SWITCHING CHARACTERISTICS (Ta=25°C; VDD=4.75 ∼ 5.25V; CL=20pF) Parameter Symbol min typ max Units Master Clock Frequency Duty Cycle fCLK dCLK 2.048 11.2896 36.864 MHz LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 120 192 kHz kHz kHz Audio Interface Timing BICK Period Normal Speed Mode Double/Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK rising to LRCK Edge (Note 12) LRCK Edge to BICK rising (Note 12) SDTI Hold Time SDTI Setup Time tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/64fs ns ns ns ns ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 150 ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width (Note 13) tPD 150 ns Notes: 12. BICK rising edge must not occur at the same time as LRCK edge. 13. The AK4385 can be reset by bringing PDN= “L”.

[AK4385] MS0246-E-00 - 7 - „ Timing Diagram 1/fCLK tCLKL VIH tCLKH MCLK VIL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK tBCKL VIH tBCKH BICK VIL Clock Timing tLRB LRCK VIH BICK VIL tSDS VIH SDTI VIL tSDH VIH VIL tBLR Serial Interface Timing

[AK4385] MS0246-E-00 - 8 - tCSS CSN VIH CCLK VIL VIH CDTI VIL VIH VIL R/W tCCKL tCCKH tCDS tCDH WRITE Command Input Timing CSN VIH CCLK VIL VIH CDTI VIL VIH VIL tCSW tCSH WRITE Data Input Timing tPD VIL PDN Power-down Timing

the appropriate frequency (Table 6), it is not necessary to set DFS0/1. Table 1. Sampling Speed (Manual Setting Mode) Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)

with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off. Table 8. De-emphasis Filter Control (Normal Speed Mode) The AK4385 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. time of 1 level and all 256 levels is shown in Table 9.

1 Level

Table 9. ATT Transition Time

without stopping the signal transmission. (2) The analog output corresponding to the digital input has a group delay, GD. returned to ATT level by the same cycle. “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”. Figure 5. Soft Mute and Zero Detection

VCOM voltage and DZF pin goes to “H”. Figure 7 shows the example of reset by RSTN bit. (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage (VDD/2). (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”). (5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”. Figure 7. Reset Sequence Example

in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max). Figure 8. Control I/F Timing For addresses from 05H to 1FH, data must not be written. When PDN pin goes “L”, the registers are initialized to their default values. All data can be written to the register even if PW or RSTN bit is “0”.

[AK4385] MS0246-E-00 - 17 - „ Register Definitions Addr Register Name 00H Control 1 ACKS DIF2 DIF1 DIF0 PW RSTN default RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes, the AK4385 should be reset by PDN pin or RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF2-0: Audio data interface formats (see Table 7) Initial: “010”, Mode 2 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode. Addr Register Name 01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE default SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response (see Table 8) Initial: “01”, OFF DFS1-0: Sampling speed control 00: Normal speed 01: Double speed 10: Quad speed When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”.

[AK4385] MS0246-E-00 - 20 - PACKAGE 0-10° Detail A Seating Plane 0.10 0.17±0.05 0.22±0.1 0.65 *5.0±0.1 1.05±0.05 A 16pin TSSOP (Unit: mm) *4.4±0.1 6.4±0.2 0.5±0.2 0.1±0.1 NOTE: Dimension "*" does not include mold flash. 0.13 M „ Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder(Pb free) plate

[AK4385] MS0246-E-00 - 21 - MARKING AKM 4385VT XXYYY Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4385VT Asahi Kasei Logo IMPORTANT NOTICE

  • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
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