AKD4126-A

AKD4126-A AKM | Alldatasheet

Document overview

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• PDF pages: 29

Technical content

• DIR/DIT with optical input/output
• 10pin Header for AKM AD/DA evaluation board Opt In AK4114 10pin Header DSP Data 5V GND Opt OutAK4114 10pin Header DSP Data AK4126 COAX Regulator COAX

Figure 1. AKD4126-A Block Diagram

• Circuit diagram and PCB layout are attached at the end of this manual.

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 2 - „ Operation sequence [1] Set up lines of power supply [VDD] (Red) = +5[V] (Power supply for regulator REG1 and REG2. REG1 and REG2 supplies 3.3V to the AKD4126-A.) [GND] (Black) = 0[V] [2] Set up jumper pins of power supply (1). Set up AVDD1 and DVDD1 (Set up AVDD and DVDD of the AK4126) Power supply source of AVDD1 and DVDD1 is selected by JP23. (a) From VDD terminal (b) From REG1 VDD-AK4126VDD-AK4126 JP23JP23 VDD REG1 VDD REG1 (VDD) (REG1) (2). Set up VDD1 and VDD2 (Set up AVDD, DVDD and TVDD of the AK4114, VDD of logic IC and others) Power supply source of VDD1 and VDD2 is selected by JP24. (a) From VDD terminal (b) From REG2 VDD-LOGICVDD-LOGIC JP24JP24 VDD REG2 VDD REG2 (VDD) (REG2) [3] Evaluation modes (1). Input PORT (1)-1. DIR functions of the AK4114 (U2) are used. (Default) (1)-2. External equipments are connected via 10-pin connector (PORT2). (2). Output PORT (2)-1. DIT functions of the AK4114 (U3) are used. (Default) (2)-2. External equipments are connected via 10-pin connector (PORT4). [4] Set up jumper pins and DIP-switches of evaluation modes. (Refer to the following.) [5] Power on. Power down reset of the AK4126 (U1), the AK4114 (U2) and the AK4114 (U3) should be done once after power on. Method of power down reset of them is that after once put them on power-down bringing toggle switches SW6 and SW8 to “L”, release them from power-down bringing toggle switches SW6 and SW8 to “H”.

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 3 - „ Set up jumper pins and DIP-switches of evaluation modes (1). Set up jumper pins and DIP-switches of input PORT (1)-1. DIR functions of the AK4114 (U2) are used. (Default) (1)-1-1. Set up RX Select input connector of RX by JP7 (RX). (a) RX is input from PORT1 (OPT) (b) RX is input from J1 (COAX) RXRX JP7JP7 OPT COAX OPT COAX (OPT) (COAX) (1)-1-2. Set up IBICK, ILRCK and SDTI Clocks (IBICK and ILRCK) and data (SDTI) of the AK4126 (U1) are supplied from the AK4114 (U2). As 10-pin connector: PORT2 (INPUT) is not used, please don’t connect anything. JP9 XTE-RXXTI-RX JP8 (Open) (Short) JP10 IBICK1 JP12 SDTI JP11 ILRCKIMCLK JP13 (Open) (Short) (Short) (Short)

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 4 - (1)-1-3. Set up SDTI1, SDTI2 and SDTI3 Select input data to SDTI1, SDTI2 and SDTI3 of the AK4126 (U1). When these jumper pins are set to SDTI side, SDTO of the AK4114 (U2) is input to SDTI1, SDTI2 and SDTI3. When these jumper pins are set to GND side, “0” data is input to SDTI1, SDTI2 and SDTI3. (a) “0” data is input to SDTI1 (b) SDTO of the AK4114 (U2) is input to SDTI1 SDTI1 SDTI1 JP1 JP1 GND SDTI SDTI GND (GND) (SDTI) (a) “0” data is input to SDTI2 (b) SDTO of the AK4114 (U2) is input to SDTI2 SDTI2 JP3 SDTIGND (GND) SDTI2 JP3 GND SDTI (SDTI) (a) “0” data is input to SDTI3 (b) SDTO of the AK4114 (U2) is input to SDTI3 SDTI3 SDTI3 JP5 JP5 SDTI SDTIGND GND (GND) (SDTI) (1)-1-4. Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) by SW1. About setting of default, please refer to Table1. About setting except default, please refer to Table2 and Table3. (1)-1-5. Set up Output Audio Interface Format, Clock Mode and Master Clock Frequency of the AK4114 (U2) Set up Output Audio Interface Format, Clock Mode and Master Clock Frequency of theAK4114 (U2) by SW4. About setting of default, please refer to Table4. About setting except default, please refer to Table5, Table6, and Table7.

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 5 - (1)-2. External equipments are connected via 10-pin connector (PORT2). (1)-2-1. Set up RX As Optical connector: PORT1 (OPT) and BNC connector: J1 (COAX) are not used, please don’t connect anything. (1)-2-2. Set up IBICK, ILRCK and SDTI Clocks (IBICK and ILRCK) and data (SDTI) of AK4126 (U1) are supplied from external equipments via 10-pin connector: PORT2 (INPUT). JP10 IBICK1 JP12 SDTI JP11 ILRCKIMCLK JP13 IBICK2 JP14 INV THR (THR) (Open) (Open) (Open) (Open) (1)-2-3. Set up SDTI1, SDTI2 and SDTI3 Select input data to SDTI1, SDTI2 and SDTI3 of the AK4126 (U1). When these jumper pins are set to SDTI side, output data of external equipment is input to SDTI1, SDTI2 and SDTI3 via 10-pin connector: PORT2 (INPUT). When these jumper pins are set to GND side, “0” data is input to SDTI1, SDTI2 and SDTI3. (a) “0” data is input to SDTI1 (b) Output data of external equipment is input to SDTI1 SDTI1 SDTI1 JP1 JP1 GND SDTI SDTI GND (GND) (SDTI) (a) “0” data is input to SDTI2 (b) Output data of external equipment is input to SDTI2 SDTI2 JP3 SDTIGND (GND) SDTI2 JP3 GND SDTI (SDTI) (a) “0” data is input to SDTI3 (b) Output data of external equipment is input to SDTI3 SDTI3 SDTI3 JP5 JP5 SDTI SDTIGND GND (GND) (SDTI) (1)-2-4. Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) by SW1. About setting of default, please refer to Table1. About setting except default, please refer to Table2 and Table3.

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 6 - (2). Set up jumper pins and DIP-switches of output PORT (2)-1. DIT functions of AK4114 (U3) are used. (Default) (2)-1-1. Set up TX Select output connector of TX by JP15 (TX). (a) TX is output from J3 (COAX) (b) TX is output from PORT3 (OPT) TXTX JP15JP15 OPTCOAX OPT COAX (OPT)(COAX) (2)-1-2. Set up XTI Clock source of XTI of the AK4114 (U3) is selected by JP16 (XTI-TX) and JP17 (XTE-TX). When X’tal: X2 is selected, and OBICK frequency and OLRCK frequency are changed, the value of X’tal: X2 should be changed. (a) XTI is supplied from X’tal: X2 (b) XTI is supplied from J4 (XTI-TX) JP17 XTE-TX JP16 XTE-TX JP17 XTI-TXXTI-TX JP16 (Open) (Short) (Short) (Open) (2)-1-3. Set up OBICK, OLRCK and SDTO Clocks (OBICK and OLRCK) of the AK4126 (U1) are supplied from the AK4114 (U3), and data (SDTO) of the AK4126 (U1) is output to the AK4114 (U3). As 10-pin connector: PORT4 (OUTPUT) is not used, please don’t connect anything. JP19 OBI CK1 JP20 SDTO JP18 OLRCKOMCLK JP21 (Open) (Short) (Short) (Short)

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 7 - (2)-1-4. Set up SDTO1, SDTO2 and SDTO3 A data selected among SDTO1, SDTO2 and SDTO3 of the AK4126 (U1), is input to DAUX of the AK4114 (U3). SDTO1, SDTO2 and SDTO3 cannot be selected at same time. (a) SDTO1 is input to DAUX of the AK4114 (U3). SDTO1 SDTO2 JP2 JP4 SDTO1SDTO SDTO SDTO2 (Open)(SD TO ) SDTO3 JP6 SDTO SDTO3 (Open) (b) SDTO2 is input to DAUX of the AK4114 (U3). SDTO1 SDTO2 JP2 JP4 SDTO1SDTO SDTO SDTO2 (SD TO )(Open) SDTO3 JP6 SDTO SDTO3 (Open) (c) SDTO3 is input to DAUX of the AK4114 (U3). SDTO1 SDTO2 JP2 JP4 SDTO1SDTO SDTO SDTO2 (Open)(Open) SDTO3 JP6 SDTO SDTO3 (SD TO ) (2)-1-5. Set up Output Audio Interface Format 2 and Output Audio Interface Format 1 of the AK4126 (U1) Set up Output Audio Interface Format 2 and Output Audio Interface Format 1 of the AK4126 (U1) by SW2. About setting of default, please refer to Table8. About setting except default, please refer to Table9, Table11. (2)-1-6. Set up Input Audio Interface Format, Clock Mode and Master Clock Frequency of the AK4114 (U3) Set up Input Audio Interface Format, Clock Mode and Master Clock Frequency of the AK4114 (U3) by SW5. About setting of default, please refer to Table12. About setting except default, please refer to Table13, Table14, and Table15.

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 8 - (2)-2. External equipments are connected via 10-pin connector (PORT4). (2)-2-1. Set up TX As Optical connector: PORT3 (OPT) and BNC connector: J3 (COAX) are not used, please don’t connect anything. (2)-2-2. Set up OBICK, OLRCK and SDTO Clocks (OBICK and OLRCK) of the AK4126 (U1) are supplied from external equipment via 10-pin connector: PORT4 (OUTPUT), and output data (SDTO) of the AK4126 (U1) is output to external equipment via 10-pin connector: PORT4 (OUTPUT). JP19 OBI CK1 JP20 SDTO JP18 OLRCKOMCLK JP21 OBI CK2 JP22 IN V THR (THR) (Open) (Open) (Open) (Open) (2)-2-3. Set up SDTO1, SDTO2 and SDTO3 A data selected among SDTO1, SDTO2 and SDTO3 of the AK4126 (U1), is input to external equipment via 10-pin connector: PORT4 (OUTPUT). SDTO1, SDTO2 and SDTO3 cannot be selected at same time. (a) SDTO1 is input to external equipment SDTO1 SDTO2 JP2 JP4 SDTO1SDTO SDTO SDTO2 (Open)(SD TO ) SDTO3 JP6 SDTO SDTO3 (Open) (b) SDTO2 is input to external equipment SDTO1 SDTO2 JP2 JP4 SDTO1SDTO SDTO SDTO2 (SD TO )(Open) SDTO3 JP6 SDTO SDTO3 (Open) (c) SDTO3 is input to external equipment SDTO1 SDTO2 JP2 JP4 SDTO1SDTO SDTO SDTO2 (Open)(Open) SDTO3 JP6 SDTO SDTO3 (SD TO ) (2)-2-4. Set up Output Audio Interface Format 2 and Output Audio Interface Format 1 of the AK4126 (U1) Set up Output Audio Interface Format 2 and Output Audio Interface Format 1 of the AK4126 (U1) by SW2. About setting of default, please refer to Table8. About setting except default, please refer to Table9 and Table11.

• Set up SW3 ON is “H”, and OFF is “L”. Setting of default is as follows. (Please refer to Table 16.) SW3 No. Name ON (“H”) OFF (“L”) Default

1 TI2 L

2 TI1 L

3 TI0

4 SMT1 L

5 SMT0

6 DEM1 L

7 DEM0

8 PM AK4126 Channel Mode Setting

Table 16. SW3 Setting Table 17. AK4126 Soft Mute Cycle Mode Setting (On Manual Mode)

1 L H OFF (Default)

2 H L 48kHz

3 H H 32kHz

Table 18. AK4126 De-emphasis Filter Mode Setting

0 L 6-channel (Default)

1 H 4-channel

Table 19. AK4126 Channel Mode Setting

• Set up SW1 ON is “H”, and OFF is “L”. Setting of default (Slave Mode, 24bit MSB justified, IBICK lock mode (64fsi), IBICK=Input, ILRCK=Input) is as follows. (Please refer to Table 1.) SW1 No. Name ON (“H”) OFF (“L”) Default

1 PLL2 H

2 PLL1 L

3 PLL0

4 IDIF2 L

5 IDIF1 H

6 IDIF0

Table 1. SW1 Setting

0 L L L 8k ~ 96kHz

1 L L H

2 L H L

3 L H H Reserved

4 H L L 32fsi

5 H L H 64fsi (Default)

6 H H L 128fsi

7 H H H

please refer to datasheet: “PLL Loop Filter”. (Note 2) IBICK should be always and continuously supplied, except when clocks are changed. (Note 4) Please refer to datasheet: “Soft Mute Operation”: “Manual mode”. (Note 5) Please refer to datasheet: “Soft Mute Operation ”: “Semi-Auto mode”.

0 L L L 16bit, LSB justified ≥ 32fsi

1 L L H 20bit, LSB justified ≥ 40fsi

2 L H L 24/20bit, MSB justified ≥ 48fsi (Default)

3 L H H 24/16bit, I2S Compatible ≥ 48fsi or 32fsi

4 H L L 24bit, LSB justified ≥ 48fsi

5 H L H Reserved

6 H H L Reserved

7 H H H Reserved

Table 3. AK4126 Input Audio Interface Format Setting (Input PORT)

• Set up SW4 ON is “H”, and OFF is “L”. Setting of default (Master mode, 24bit Left justified) is as follows. (Please refer to Table 4.) SW4 No. Name ON (“H”) OFF (“L”) Default

1 DIF2 H

2 DIF1 L

3 DIF0

4 CM1 L

5 CM0

6 OCKS1 H

7 OCKS0

Table 4. SW4 Setting

0 L L L 16bit, Right justified H/L O 64fs O

1 L L H 18bit, Right justified H/L O 64fs O

2 L H L 20bit, Right justified H/L O 64fs O

3 L H H 24bit, Right justified H/L O 64fs O

4 H L L 24bit, Left justified H/L O 64fs O (Default)

5 H L H 24bit, I 2S Compatible L/H O 64fs O

6 H H L 24bit, Left justified H/L I 64-128fs I

7 H H H 24bit, I 2S Compatible L/H I 64-128fs I

Table 5. AK4114 Output Audio Interface Format Setting

0 L L 256fs 256fs 256fs 96 kHz

1 L H 256fs 128fs 256fs 96 kHz

2 H L 512fs 256fs 512fs 48 kHz (Default)

3 H H 128fs 64fs 128fs 192 kHz

Table 7. AK4114 Master Clock Frequency Setting

• Set up SW2 ON is “H”, and OFF is “L”. Setting of default (Slave Mode, 24bit MSB justified, OLRCK=Input, OBICK=Input, fso=8K~192KHz) is as follows. (Please refer to Table 8.) SW2 No. Name ON (“H”) OFF (“L”) Default

1 DITHER Dither ON Dither OFF L

2 OBIT1 H

3 OBIT0

5 TEST2 L

7 ODIF1 H

8 ODIF0

Table 8. SW2 Setting

0 L L 16bit ≥ 32fso

1 L H 18bit ≥ 36fso

2 H L 20bit ≥ 40fso

3 H H 24bit ≥ 48fso

Table 9. AK4126 Output Audio Interface Format 2 Setting (Output PORT)

0 L L LSB justified

1 L H (Reserved)

2 H L MSB justified (Default)

3 H H I 2S Compatible

Table 11. AK4126 Output Audio Interface Format 1 Setting (Output PORT)

• Set up SW5 ON is “H”, and OFF is “L”. Setting of default (Master mode, 24bit Left just ified) is as follows. (Please refer to Table 12.) SW5 No. Name ON (“H”) OFF (“L”) Default

6 OCKS1 L

Table 12. SW5 Setting

0 L L L 24bit, Left justified H/L O 64fs O

1 L L H 24bit, Left justified H/L O 64fs O

2 L H L 24bit, Left justified H/L O 64fs O

3 L H H 24bit, Left justified H/L O 64fs O

Table 13. AK4114 Input Audio Interface Format Setting

0 L L 256fs 256fs 256fs 96 kHz (Default)

2 H L 512fs 256fs 512fs 48 kHz

Table 15. AK4114 Master Clock Frequency Setting

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 14 - „ Toggle Switch Operation Upper side is “H” and lower side is “L”. [SW6] (PDN-AK4126): Power down switch of the AK4126 (U1). The AK4126 (U1) should be reset once by bringing to “L” upon power-up. Keep “H” during normal operation. [SW7] (SMUTE-AK4126): Soft mute switch of the AK4126 (U1). Output of the AK4126 (U1) is soft-muted by bringing to “H”. [SW8] (PDN-AK4114-RX/TX): Power down switch of the AK4114 (U2) and the AK4114 (U3). The AK4114 (U2) and the AK4114 (U3) should be reset once by bringing to “L” upon power-up. Keep “H” during normal operation. „ LED Indication [LED1] (UNLOCK): Output of UNLOCK pin of the AK4126 (U1). Turns on when PLL of the AK4126 (U1) is unlocked. [LED2] (INT0): Output of INT0 pin of the AK4114 (U2). Turns on when the AK4114 (U2) is unlocked.

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 15 - MEASUREMENT RESULTS [Measurement condition]

• Measurement unit : Audio Precision, System Two Cascade
• Power Supply : AVDD=DVDD=3.3V
• Band width : 20Hz ∼ FSO/2
• Temperature : Room [Measurement Result] SRC Characteristics SDTO1 Lch SDTO1 Rch SDTO2 Lch SDTO2 Rch SDTO3 Lch SDTO3 Rch Unit THD+N (Input = 1kHz, 0dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz Worst Case (FSO/FSI = 32kHz/176.4kHz) 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 dB dB dB dB dB Dynamic Range (Input = 1kHz, −60dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz FSO/FSI = 48kHz/32kHz Dynamic Range (Input = 1kHz, −60dBFS, A-weighted) FSO/FSI = 44.1kHz/48kHz 136.2 136.4 136.2 135.6 137.3 139.6 136.2 136.4 136.2 135.6 137.3 139.6 136.2 136.4 136.2 135.6 137.3 139.6 136.2 136.4 136.2 135.6 137.3 139.6 136.2 136.4 136.2 135.6 137.3 139.6 136.2 136.4 136.2 135.6 137.3 139.6 dB dB dB dB dB dB

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 16 - [Plot] AK4126 FFT Plot (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input=0dBFS, fin=1KHz 20 20k50 100 200 500 1k 2k 5k 10k Hz -200 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d B F S Fig 6. FFT Plot (Input = 0dBFS) AK4126 FFT Plot (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input=-60dBFS, fin=1KHz 20 20k50 100 200 500 1k 2k 5k 10k Hz -200 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d B F S Fig 7. FFT Plot (Input = -60dBFS)

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 17 - AK4126 THD+N vs Input Level (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, fin=1KHz -140 +0-130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBFS -150 -120 -148 -146 -144 -142 -140 -138 -136 -134 -132 -130 -128 -126 -124 -122 d B F S Fig 1. THD+N vs. Input Level AK4126 THD+N vs Input Frequency (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input Level=0dBFS 20 20k50 100 200 500 1k 2k 5k 10k Hz -150 -80 -145 -140 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 d B F S Fig 2. THD+N vs. Input Frequency (Input = 0dBFS)

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 18 - AK4126 THD+N vs Input Frequency (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input Level=-60dBFS 20 20k50 100 200 500 1k 2k 5k 10k Hz -180 -100 -175 -170 -165 -160 -155 -150 -145 -140 -135 -130 -125 -120 -115 -110 -105 d B F S Fig 3. THD+N vs. Input Frequency (Input = -60dBFS) AK4126 Linearity (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, fin=1KHz -150 +0-140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBFS -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d B F S Fig 4. Linearity

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 19 - AK4126 Frequency Response (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input Level=0dBFS 2k 22k4k 6k 8k 10k 12k 14k 16k 18k 20k Hz -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 +0.5 d B F S Fig 5. Frequency Response AK4126 Frequency Response (Blue: fsi=48KHz, Red: fsi=96KHz, Green: fsi=192KHz), fso=48KHz AVDD=DVDD=3.3V, Input Level=0dBFS 2k 22k4k 6k 8k 10k 12k 14k 16k 18k 20k Hz -7.5 -6.5 -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 +0.5 d B F S Fig 8. Frequency Response fsi=192kHz fsi=96kHz fsi=48kHz

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 20 - AK4126 Frequency Response (Yellow: fsi=44.1KHz, Blue: fsi=48KHz, Red: fsi=96KHz, Green: fsi=192KHz), fso=44.1KHz AVDD=DVDD=3.3V, Input Level=0dBFS 2k 22k4k 6k 8k 10k 12k 14k 16k 18k 20k Hz -7.5 -6.5 -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 +0.5 d B F S Fig 9. Frequency Response fsi=192kHz fsi=96kHz fsi=48kHz fsi=44.1kHz

ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 21 -

Revision History

• These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
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• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Date (YY/MM/DD) Manual Revision Board Revision Reason Contents 07/01/09 KM083203 2 First Edition

A A B B C C D D E E A A B B C C D D E E VDD1 VDD1 VDD1 VDD1 VDD1 ILRCK IBICK IMCLK OLRCK OBICK OMCLK SDTOSDTI AVDD1 DVDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 DVDD1 DVDD1DVDD1 DVDD1 Title Size Document Number Rev Date: Sheet of AK4126 2 AKD4126-A 14Thursday, August 03, 2006 Title Size Document Number Rev Date: Sheet of AK4126 2 AKD4126-A 14Thursday, August 03, 2006 Title Size Document Number Rev Date: Sheet of AK4126 2 AKD4126-A 14Thursday, August 03, 2006 IDIF2 PLL1 IDIF1 IDIF0 PLL0 PLL2 ODIF1 OBIT0 ODIF0 TEST1 TEST2 OBIT1 TEST3 OUTPUT-AK4126 H H PDN-AK4126 SMUTE-AK4126 L L UNLOCK DITHER INPUT-AK4126 47K SMT1 TI1 SMT0 DEM1 DEM0 TI0 PM TI2 MODE-AK4126 SDTI1 SDTI2 SDTI3 SDTO1 SDTO2 SDTO3 47K 47K SDTI SDTI SDTI GND GND GND SDTO SDTO SDTO JP2 HIF3G-50P-2.54DSA (2x1)JP2 HIF3G-50P-2.54DSA (2x1) C12 0.1u C12 0.1u CN3 64pin_1 CN3 64pin_1 SW3 DSS108 SW3 DSS108 1 2 14 7 U6A 74HC14 U6A 74HC14 10u+ 10u +C8 10u +C8 10u R16 10k R16 10k 2 1 HSU119 HSU119 R8 51R8 51 JP5HIF3G-50P-2.54DSA (3x1)JP5HIF3G-50P-2.54DSA (3x1) R6 51R6 51 SW1 DSS106 SW1 DSS106 R11 51R11 51 0.1u 0.1u R4 51R4 51 14 7 U4A 74AC14 U4A 74AC14 C10 0.1u C10 0.1u NC1 TEST02 ILRCK3 IBICK4 DVDD5 DVSS6 TST07 SDTI18 SDTI29 SDTI310 IDIF011 IDIF112 IDIF213 TST114 TST215 NC16 TST317 TST418 UNLOCK19 DVDD20 DVSS21 SMUTE22 DITHER23 PDN 24 SMT025 SMT126 DEM027 DEM128 PM 29 OBIT030 OBIT131 TST532 NC 33 TEST1 34 TEST2 35 TEST3 36 ODIF1 37 ODIF0 38 SDTO3 39 SDTO2 40 SDTO1 41 TST6 42 DVSS 43 DVDD 44 OBICK 45 OLRCK 46 TEST4 47 NC 48 NC49 TST750 TST851 DVDD52 DVSS53 PLL254 PLL155 PLL056 TST957 TST1058 NC59 AVDD60 FILT61 AVSS62 TST1163 NC64U1 AK4126 AK4126 9 8 14 7 U6D 74HC14 U6D 74HC14 +C1 10u+C1 10u R14 1kR14 1k C14 0.1u C14 0.1u RP1 M7-1-473 RP1 M7-1-473 R7 51R7 51 RP3 M9-1-473 RP3 M9-1-473 R46 100 R46 100 LED1 SML-210LT LED1 SML-210LT RP2 M9-1-473 RP2 M9-1-473 SW2 DSS108 SW2 DSS108 R13 51R13 51 R15 10k R15 10k R3 51R3 51 JP1HIF3G-50P-2.54DSA (3x1)JP1HIF3G-50P-2.54DSA (3x1) 0.22u 0.22u 470 470 R5 51R5 51 2 1 HSU119 HSU119 R2 51R2 51 3 4 14 7 U6B 74HC14 U6B 74HC14 JP3HIF3G-50P-2.54DSA (3x1)JP3HIF3G-50P-2.54DSA (3x1) 0.1u 0.1u +C7 10u +C7 10u R9 51R9 51 R12 51R12 51 CN4 64pin_2 CN4 64pin_2 SW7 ATE1D-2M3 SW7 ATE1D-2M3 C11 0.1u C11 0.1u 0.1u 0.1u JP4 HIF3G-50P-2.54DSA (2x1)JP4 HIF3G-50P-2.54DSA (2x1) SW6 ATE1D-2M3 SW6 ATE1D-2M3 R45 100 R45 100 CN1 64pin_4 CN1 64pin_4 C13 10u+ C13 10u JP6 HIF3G-50P-2.54DSA (2x1)JP6 HIF3G-50P-2.54DSA (2x1) 5 6 14 7 U6C 74HC14 U6C 74HC14 R10 51R10 51 CN2 64pin_3 CN2 64pin_3

A A B B C C D D E E A A B B C C D D E E VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 IMCLK IBICK ILRCK SDTI VDD1 VDD1 PDN-4114-TX VDD1 VDD1 VDD1 VDD1 VDD1 Title Size Document Number Rev Date: Sheet of INPUT RX AK4114 2 AKD4126-A 24Thursday, August 03, 2006 Title Size Document Number Rev Date: Sheet of INPUT RX AK4114 2 AKD4126-A 24Thursday, August 03, 2006 Title Size Document Number Rev Date: Sheet of INPUT RX AK4114 2 AKD4126-A 24Thursday, August 03, 2006 COAX OPT RX(OPT) IBICK1 SDTI ILRCK RX RX(COAX) INT0 IMCLK 24.576MHz ILRCK IMCLK IBICK SDTI XTI-RX XTI-RX H PDN-AK4114-RX/TX L DIF2 DIF1 DIF0 INPUT-AK4114 OCKS1 OCKS0 CM1 CM0 XTE-RX 47K INPUT IBICK2 THR INV R29 220k R29 220k C26 10u + C26 10u 14 7 U4C 74AC14 U4C 74AC14 RP4 M8-1-473 RP4 M8-1-473 C24 0.1u C24 0.1u BNC-R-PC BNC-R-PC 3 4 14 7 U4B 74AC14 U4B 74AC14 11 10 14 7 U6E 74HC14 U6E 74HC14 SW4 DSS107 SW4 DSS107 JP11 HIF3G-50P-2.54DSA (2x1)JP11 HIF3G-50P-2.54DSA (2x1) R21 10k R21 10k C23 0.1u C23 0.1u R18 R18 R47 R47 13 12 14 7 U6F 74HC14 U6F 74HC14 C25 10u + C25 10u 2 1 HSU119 HSU119 C16 0.1uC16 0.1u JP9 HIF3G-50P-2.54DSA (2x1) JP9 HIF3G-50P-2.54DSA (2x1) C20 10pC20 10p SW8 ATE1D-2M3 SW8 ATE1D-2M3 IPS01 NC2 DIF03 TEST24 DIF15 NC6 DIF27 IPS18 P/SN9 XTL010 XTL111 TVDD13 DVSS14 TX0 15 TX1 16 BOUT17 COUT18 UOUT19 VOUT20 DVDD21 DVSS22 MCKO123 BICK 26 MCKO2 27 DAUX 28 XTO 29 XTI 30 PDN 31 CM0 32 CM1 33 OCKS1 34 OCKS0 35 INT0 36 AVDD38 R39 VCOM40 AVSS41 RX042 NC43 RX144 TEST145 RX246 NC47 RX348 VIN12 LRCK24 SDTO 25 INT137U2 AK4114 AK4114 R26 220k R26 220k 9 10 PORT2 A1-10PA-2.54DSA PORT2 A1-10PA-2.54DSA R23 51R23 51 9 8 14 7 U4D 74AC14 U4D 74AC14 R22 51R22 51 C18 0.1uC18 0.1u R24 51R24 51 R20 1kR20 1k JP12 HIF3G-50P-2.54DSA (2x1)JP12 HIF3G-50P-2.54DSA (2x1) C15 0.1u C15 0.1u 47u 47u 2 1 LED2 SML-210LT LED2 SML-210LT R27 220k R27 220k JP7HIF3G-50P-2.54DSA (3x1)JP7HIF3G-50P-2.54DSA (3x1) OUT 1 VCC 3 GND 2 PORT1 TORX141 PORT1 TORX141 + C19 0.47u+ C19 0.47u R19 18k R19 18k JP8 HIF3G-50P-2.54DSA (2x1) JP8 HIF3G-50P-2.54DSA (2x1) R28 220k R28 220k C21 10pC21 10p C17 10u C17 10u R25 51R25 51 BNC-R-PC BNC-R-PC JP10 HIF3G-50P-2.54DSA (2x1)JP10 HIF3G-50P-2.54DSA (2x1) JP14 HIF3G-50P-2.54DSA (3x1) JP14 HIF3G-50P-2.54DSA (3x1) JP13 HIF3G-50P-2.54DSA (2x1)JP13 HIF3G-50P-2.54DSA (2x1) R17 470R17 470 1 2 X1 HC-49/UX1 HC-49/U C22 0.1u C22 0.1u

A A B B C C D D E E A A B B C C D D E E VDD2 SDTO OMCLK OBICK OLRCK VDD2 VDD2 VDD2 VDD2 VDD2 PDN-4114-TX VDD2 VDD2 Title Size Document Number Rev Date: Sheet of OUTPUT TX AK4114 2 AKD4126-A 34Thursday, August 03, 2006 Title Size Document Number Rev Date: Sheet of OUTPUT TX AK4114 2 AKD4126-A 34Thursday, August 03, 2006 Title Size Document Number Rev Date: Sheet of OUTPUT TX AK4114 2 AKD4126-A 34Thursday, August 03, 2006 OBICK1 OLRCK 11.2896MHz SDTO OLRCK OBICK OMCLK SDTO OMCLK TX(OPT) OPT COAX TX TX(COAX) 1:1 DIF2 DIF1 DIF0 OCKS1 OCKS0 CM1 CM0 OUTPUT-AK4114 XTI-TX XTE-TX XTI-TX 47K OUTPUT OBICK2 THR INV C30 0.1uC30 0.1u JP19 HIF3G-50P-2.54DSA (2x1)JP19 HIF3G-50P-2.54DSA (2x1) C37 10u + C37 10u RP5 M8-1-473 RP5 M8-1-473 R33 51R33 51 C29 10u C29 10u R32 51R32 51 R35 51R35 51 R38 220k R38 220k C27 0.1u C27 0.1u GND 1 VCC 2IN 3 PORT3 TOTX141 PORT3 TOTX141 BNC-R-PC BNC-R-PC C34 0.1u C34 0.1u + C31 0.47u+ C31 0.47u C32 10pC32 10p JP18 HIF3G-50P-2.54DSA (2x1)JP18 HIF3G-50P-2.54DSA (2x1) 9 10 PORT4 A1-10PA-2.54DSA PORT4 A1-10PA-2.54DSA R31 150 R31 150 R34 51R34 51 R37 220k R37 220k C35 0.1u C35 0.1u DA-02F DA-02F R36 220k R36 220k R30 240R30 240 SW5 DSS107 SW5 DSS107 IPS01 NC2 DIF03 TEST24 DIF15 NC6 DIF27 IPS18 P/SN9 XTL010 XTL111 TVDD13 DVSS14 TX0 15 TX1 16 BOUT17 COUT18 UOUT19 VOUT20 DVDD21 DVSS22 MCKO123 BICK 26 MCKO2 27 DAUX 28 XTO 29 XTI 30 PDN 31 CM0 32 CM1 33 OCKS1 34 OCKS0 35 INT0 36 AVDD38 R39 VCOM40 AVSS41 RX042 NC43 RX144 TEST145 RX246 NC47 RX348 VIN12 LRCK24 SDTO 25 INT137 AK4114 AK4114 JP21 HIF3G-50P-2.54DSA (2x1)JP21 HIF3G-50P-2.54DSA (2x1) 3 4 14 7 U5B 74AC14 U5B 74AC14 C33 10pC33 10p JP16 HIF3G-50P-2.54DSA (2x1) JP16 HIF3G-50P-2.54DSA (2x1) JP20 HIF3G-50P-2.54DSA (2x1)JP20 HIF3G-50P-2.54DSA (2x1) JP22 HIF3G-50P-2.54DSA (3x1) JP22 HIF3G-50P-2.54DSA (3x1) 1 2 X2 HC-49/UX2 HC-49/U R39 220k R39 220k 14 7 U5A 74AC14 U5A 74AC14 C36 10u + C36 10u JP15 HIF3G-50P-2.54DSA (3x1) JP15 HIF3G-50P-2.54DSA (3x1) C28 0.1uC28 0.1u BNC-R-PC BNC-R-PC R48 R48 51JP17 HIF3G-50P-2.54DSA (2x1) JP17 HIF3G-50P-2.54DSA (2x1)

A A B B C C D D E E A A B B C C D D E E VDD AVDD1 DVDD1 VDD2 VDD1 VDD1 VDD2 Title Size Document Number Rev Date: Sheet of POWER SUPPLY 2 AKD4126-A 44Thursday, August 03, 2006 Title Size Document Number Rev Date: Sheet of POWER SUPPLY 2 AKD4126-A 44Thursday, August 03, 2006 Title Size Document Number Rev Date: Sheet of POWER SUPPLY 2 AKD4126-A 44Thursday, August 03, 2006 74HC14 74AC14 for for (for AVDD of AK4126) (for DVDD of AK4126) (for AVDD, DVDD, TVDD of AK4114 (RX)) (for AVDD, DVDD, TVDD of AK4114 (TX)) (for VCC of TORX141 (RX Opt)) (for VCC of TOTX141 (TX Opt)) (for VDD of 74AC14(RX)) VDD-AK4126 VDD-LOGIC VDD VDD REG1 REG2 for 74AC14 RX TX (for VDD of 74AC14(TX)) (for SW1,SW2,SW3,SW4,SW6,SW7,SW8,RP1,RP2,RP3,RP4,LED1,LED2) (for SW5,RP5) (for VDD of 74HC14) C44 0.1u C44 0.1u 11 10 14 7 U4E 74AC14 U4E 74AC14 C48 0.1u C48 0.1u R43 (short)R43 (short) JP23 HIF3G-50P-2.54DSA (3x1) JP23 HIF3G-50P-2.54DSA (3x1) R42 (short)R42 (short) 13 12 14 7 U4F 74AC14 U4F 74AC14 C39 0.1u C39 0.1u C40 0.1u C40 0.1u GND1 OUT 2IN3 REG2 LT1117-3.3 REG2 LT1117-3.3 + C46 47u + C46 47u + C47 47u + C47 47u +C41 47u +C41 47u C45 0.1u C45 0.1u R40 (short)R40 (short) GND1 OUT 2IN3 REG1 LT1117-3.3 REG1 LT1117-3.3 C42 0.1u C42 0.1u C43 0.1u C43 0.1u R41 (short)R41 (short) 5 6 14 7 U5C 74AC14 U5C 74AC14 9 8 14 7 U5D 74AC14 U5D 74AC14 JP24 HIF3G-50P-2.54DSA (3x1) JP24 HIF3G-50P-2.54DSA (3x1) +C38 47u +C38 47u 11 10 14 7 U5E 74AC14 U5E 74AC14 13 12 14 7 U5F 74AC14 U5F 74AC14