AK4118A AKM | Alldatasheet
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[AK4118A] MS1130-E-02 2009/12 - 1 - GENERAL DESCRIPTION The AK4118A is a digital audio transceiver supporting 192kHz, 24bits. The channel status decoder supports both consumer and professional modes. The AK4118A can automatically detect a Non-PCM bit stream. When combined with the multi channel codec (AK4626A or AK4628A), the two chips provide a system solution for AC-3 applications. The dedicated pins or a serial µP I/F can control the mode setting. The small package, 48pin LQFP saves the system space. *AC-3 is a trademark of Dolby Laboratories.
FEATURES
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible Low jitter Analog PLL PLL Lock Range: 8kHz ∼ 192kHz Clock Source: PLL or X'tal 8-channel Receiver input 2-channel Transmission output (Through output or DIT) Auxiliary digital input De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz Detection Functions
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detection
- Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
- Unlock & Parity Error Detection
- Validity Flag Detection
- DAT Start ID Detection Up to 24bit Audio Data Format Audio I/F: Master or Slave Mode 42-bit Channel Status Buffer Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream Q-subcode Buffer for CD bit stream Serial µP I/F (I2C, SPI) Two Master Clock Outputs: 64fs/128fs/256fs/512fs Operating Voltage: 2.7 to 3.6V with 5V tolerance 8GPIO Port RX Data Input Detection Small Package: 48pin LQFP Ta: -10 to 70°C High Feature 192kHz 24bit Digital Audio I/F Transceiver AK4118A
[AK4118A] MS1130-E-02 2009/12 - 2 - ■ Block Diagram Input Selector Clock Recovery Clock Generator DAIF Decoder AC-3/MPEG Detect DEM µP I/F Audio I/F X'tal Oscillator PD N INT0 P/S=”L” LRCK BICK SDTO DAUX MCKO2 XTOXTIR AVD D AVSS CDTI CDTO CCLK CSNDVDD DVSS TVDD MCKO1 IIC RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 DIT TX0 Error & Detect STATUS INT1 Q-subcode buffer TX1 B,C,U,VOUT 8 to 3 Serial Control Mode Input Selector Clock Recovery Clock Generator DAIF Decoder AC-3/MPEG Detect DEM Audio I/F X'tal Oscillator PD N INT0 P/S=”H” LRCK BICK SDTO DAUX XTOXTIR AVD D AVSS CM1 CM0 OCKS1 OCKS0 DVDD DVSS TVDD IPS1 RX0 RX1 RX2 RX3 IPS0 DIF0 DIF1 DIF2 DIT TX0 Error & Detect STATUS INT1 TX1 B,C,U,VOUT 4 to 2 VIN MCKO2 MCKO1 Parallel Control Mode
[AK4118A] MS1130-E-02 2009/12 - 3 - ■ Ordering Guide AK4118AEQ -10 ~ +70 °C 48pin LQFP (0.5mm pitch) AKD4118A Evaluation Board for AK4118A ■ Pin Layout INT1 INT0 AVDD R 39 VCOM 40 VSS3 41 RX0 42 NC 43 RX1 44 TEST1 45 RX2 46 VSS4 OCKS0/CSN/CAD0 35 OCKS1/CCLK/SCL 34 PDN 31 XTI 30 XTO 29 DAUX 28 MCKO2 27 BICK 26 IPS0/RX4 1 NC 2 DIF0/RX5 3 TEST2 4 DIF1/RX6 5 DIF2/RX7 7 IPS1/IIC 8 PSN 9 XTL0 10 XTL1 11 LRCK MCKO1 VSS2 DVDD VOUT/GP7 UOUT/GP6 COUT/GP5 BOUT/GP4 TX1/GP3 TX0/GP2 GP1 AK4118AEQ Top View VSS1 CM1/CDTI/SD A CM0/CDTO/CAD1 SDTO 25VIN/GP0 12 RX 3 48 13 TVDD
[AK4118A] MS1130-E-02 2009/12 - 4 - ■ Compatibility with AK4118 1. Function and Characteristics Function AK4118A AK4118 Master Clock The MCKO2 pin outputs “L” when CM1-0 bit = “00”or “10” and UNLOCK bit = “0”. The MCKO1 and MCKO2 pins output “256fs, 128fs, 64fs” clock according to OCKS1-0 bits setting, regardless of the clock source. S/PDIF Receiver Time deviation Jitter typ; 100ps RMS Cycle-to-Cycle Jitter typ; 50ps RMS No descriptions about Jitter. 2. Register Addr Bit AK4118A AK4118 28H D6 1 0
[AK4118A] MS1130-E-02 2009/12 - 5 - PIN/FUNCTION No. Pin Name I/O Function IPS0 I Input Channel Select 0 Pin in Parallel Mode 1 RX4 I Receiver Channel 4 Pin in Seri al Mode (Internal biased pin)
2 NC I No Connect
No internal bonding. This pin should be connected to VSS3. DIF0 I Audio Data Interface Fo rmat 0 Pin in Parallel Mode 3 RX5 I Receiver Channel 5 Pin in Seri al Mode (Internal biased pin)
4 TEST2 I TEST 2 pin
This pin should be connect to VSS3. DIF1 I Audio Data Interface Fo rmat 1 Pin in Parallel Mode 5 RX6 I Receiver Channel 6 Pin in Seri al Mode (Internal biased pin)
6 VSS1 I Ground Pin
DIF2 I Audio Data Interface Fo rmat 2 Pin in Parallel Mode 7 RX7 I Receiver Channel 7 Pin in Seri al Mode (Internal biased pin) IPS1 I Input Channel Select 1 Pin in Parallel Mode 8 IIC I IIC Select Pin in Serial Mode. “L”: 4-wire Serial, “H”: IIC
9 PSN I Parallel/Serial Select Pin
“L”: Serial Mode, “H”: Parallel Mode
10 XTL0 I X’tal Frequency Select 0 Pin
11 XTL1 I X’tal Frequency Select 1 Pin
VIN I V-bit Input Pin for Transmitter Output 12 GP0 I/O GPIO0 pin in Serial Mode 13 TVDD I Input Buffer Power Supply Pin, DVDD ~5.5V
14 GP1 I/O GPIO1 pin1in Serial Mode
TX0 O Transmit Channel (Through Data) Output 0 Pin 15 GP2 I/O GPIO2 pin in Serial Mode TX1 O When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin. When TX bit = “1”, Transmit Channel (DAUX Data) Output Pin (Default). (TX bit= “1”: Default) 16 GP3 I/O GPIO3 pin in Serial Mode BOUT O Block-Start Output Pin for Receiver Input “H” during first 40 flames. 17 GP4 I/O GPIO4 pin in Serial Mode COUT O C-bit Output Pin for Receiver Input 18 GP5 I/O GPIO5 pin in Serial Mode UOUT O U-bit Output Pin for Receiver Input 19 GP6 I/O GPIO6 pin in Serial Mode VOUT O V-bit Output Pin for Receiver Input 20 GP7 I/O GPIO7 pin in Serial Mode 21 DVDD I Digital Power Supply Pin, 2.7V ~ 3.6V
22 VSS2 I Ground Pin
23 MCKO1 O Master Clock Output 1 Pin
24 LRCK I/O Channel Clock Pin
[AK4118A] MS1130-E-02 2009/12 - 6 - PIN/FUNCTION (Continued) No. Pin Name I/O Function
25 SDTO O Audio Serial Data Output Pin
26 BICK I/O Audio Serial Data Clock Pin
27 MCKO2 O Master Clock Output 2 Pin
28 DAUX I Auxiliary Audio Data Input Pin
29 XTO O X'tal Output Pin
30 XTI I X'tal Input Pin
31 PDN I
When “L”, the AK4118A is powered-down, and all output pins go to “L” and registers are initialized. CM0 I Master Clock Operation Mode 1 Pin in Parallel Mode CDTO O Control Data Input Pin in Serial Mode, IIC= “L”. CAD1 I Control Data Pin in Serial Mode, IIC= “H”. CM1 I Master Clock Operation Mode 1 Pin in Parallel Mode CDTI I Control Data Input Pin in Serial Mode, IIC= “L”. SDA I/O Control Data Pin in Serial Mode, IIC= “H”. OCKS1 I Output Clock Select 1 Pin in Parallel Mode CCLK I Control Data Clock Pin in Serial Mode, IIC= “L” SCL I Control Data Clock Pin in Serial Mode, IIC= “H” OCKS0 I Output Clock Select 0 Pin in Parallel Mode CSN I Chip Select Pin in Serial Mode, IIC=”L”. CAD0 I Chip Address 0 Pin in Serial Mode, IIC= “H”.
36 INT0 O Interrupt 0 Pin
37 INT1 O Interrupt 1 Pin
38 A VDD I Analog Power Supply Pin, 2.7V ~ 3.6V
39 R - External Resistor Pin
10kΩ +/-1% resistor should be connected to VSS3 externally.
40 VCOM - Common Voltage Output Pin
0.47µF capacitor should be connected to VSS3 externally.
41 VSS3 I Ground Pin
42 RX0 I Receiver Channel 0 Pin (Internal biased pin)
This channel is default in serial mode.
43 NC I No Connect
No internal bonding. This pin should be connected to VSS3.
44 RX1 I Receiver Channel 1 Pin (Internal biased pin)
45 TEST1 I TEST 1 pin. This pin should be connected to VSS3.
46 RX2 I Receiver Channel 2 Pin (Internal biased pin)
47 VSS4 I Ground Pin
48 RX3 I Receiver Channel 3 Pin (Internal biased pin)
Note 1. All input pins except internal biased pins (RX0-7 pins)should not be left floating.
[AK4118A] MS1130-E-02 2009/12 - 7 - ABSOLUTE MAXIMUM RATINGS (VSS1-4=0V; Note 2, Note 3) Parameter Symbol min max Units Power Supplies: Analog Digital Input Buffer AVDD DVDD TVDD -0.3 -0.3 -0.3 4.6 4.6 6.0 V V V Input Current (Any pins except supplies) IIN - ±10 mA Input Voltage (Except XTI pin) Input Voltage (XTI pin) VIN VINX -0.3 -0.3 TVDD+0.3 DVDD+0.3 V V Ambient Temperature (Power applied) Ta -10 70 °C Storage Temperature Tstg -65 150 °C Note 2. All voltages with respect to ground. Note 3. VSS1-4 must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1-4=0V; Note 2) Parameter Symbol min typ max Units Power Supplies: Analog Digital Input Buffer AVDD DVDD TVDD 2.7 2.7 DVDD 3.3 3.3 5.0 3.6 AVDD 5.5 V V V Note 2. All voltages with respect to ground. There is no level shifter. S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.7~3.6V; TVDD=2.7~5.5V) Parameter Symbol min typ max Units Input Resistance Zin 10 k Ω Input Voltage VTH 200 mVpp Input Hysteresis VHY - 50 mV Input Sample Frequency fs 8 - 192 kHz Time deviation Jitter (Note 4) - 100 - ps RMS Cycle - to - Cycle Jitter (Note 4) - 50 - ps RMS Note 4. A VDD=DVDD=3.3V , TVDD=5.0V , fs=48kHz
[AK4118A] MS1130-E-02 2009/12 - 8 - DC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.7~3.6V; TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation: PDN = “H” ( Note 5) P o w e r d o w n : P D N = “ L ” (Note 6) 100 mA μA High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%DVDD VSS2-0.3 TVDD 30%DVDD V V High-Level Output Voltage (Iout=-400 μA) Low-Level Output Voltage (Except SDA pin: Iout=400μA) ( SDA pin: Iout= 3mA) VOH VOL VOL DVDD-0.4 0.4 0.4 V V V Input Leakage Current Iin - - ± 10 μA Note 5. A VDD=DVDD=3.3V , TVDD=5.0V , CL=20pF, fs=192kHz, X'tal=24.576MHz, Clock Operation Mode 2, OCKS1=1, OCKS0=1. A VDD=7mA (typ), DVDD=25mA (typ), TVDD=10μA (typ). DVDD=36mA (typ) when the circuit of Figure 23 is attached to both TX0 and TX1 pins. Note 6. RX inputs are open and all digital input pins are held DVDD or VSS2.
[AK4118A] MS1130-E-02 2009/12 - 9 - SWITCHING CHARACTERISTICS (Ta=25 °C; DVDD=A VDD2.7~3.6V , TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz External Clock Frequency ( Note 7) Duty fECLK dECLK 8.192 24.576 MHz MCKO1 Output Frequency Duty fMCK1 dMCK1 4.096 24.576 MHz MCKO2 Output Frequency Duty fMCK2 dMCK2 2.048 24.576 MHz PLL Clock Recover Frequency (RX0-7) Fpll 8 - 192 kHz LRCK Frequency Duty Cycle fs dLCK 192 kHz Audio Interface Timing Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” ( Note 8) BICK “↑” t o L R C K E d g e (Note 8) LRCK to SDTO (MSB) BICK “↓” to SDTO DAUX Hold Time DAUX Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRM tBSD tDXH tDXS ns ns ns ns ns ns ns ns ns Master Mode BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO DAUX Hold Time DAUX Setup Time fBCK dBCK tMBLR tBSD tDXH tDXS -20 -15 64fs Hz ns ns ns ns Control Interface Timing (4-wire serial mode) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CDTO Delay CSN “↑” to CDTO Hi-Z tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 150 ns ns ns ns ns ns ns ns ns ns Note 7. When fECLK=8.192MHz, sampling frequency detect function (page16) is disable. Note 8. BICK rising edge must not occur at the same time as LRCK edge.
[AK4118A] MS1130-E-02 2009/12 - 10 - SWITCHING CHARACTERISTICS (Continued) (Ta=25 °C; DVDD=A VDD2.7~3.6V , TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ max Units Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling ( Note 9) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Capacitive load on bus Pulse Width of Spike Noise Suppressed by Input Filter fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Cb tSP 1.3 0.6 1.3 0.6 0.6 100 0.6 400 300 300 400 kHz μs μs μs μs μs μs ns ns ns μs pF ns Reset Timing PDN Pulse Width tPW 150 ns Note 9. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 10. I2C-bus is a trademark of NXP B.V.
AK4118A detects the stream again. The AK4118A detects 14bit Sync Word and 16bit Sync Word of DTS-CD bitstream. In Serial control mode this detect function can be ON/OFF by DTS14 bit and DTS16 bit. goes to “L”. The PLL loses lock when the received sync interval is incorrect. Table 1. PLL Lock Time (fs: Sampling Frequency) The AK4118A has two clock outputs, MCKO1 and MCKO2. The MCKO2 pin output mode is selected by XMCK bit. when 192kHz. The MCKO2 pin outputs “L” when PLL is the clock source. Table 2. Master Clock Frequency Select (Stereo mode)
Table 3. Master Clock Frequency Select (Stereo mode) frequency. The MCKO1 pin outputs the clock according to the CM1-0 and OCKS1-0 bit settings. Table 4. MCKO2 pin Output Frequency Setting frequency of X’tal is different from the recovered frequency from PLL.
0 ON ON PLL PLL “L” RX 2 1 0 1 ON ON X'tal X’tal X'tal DAUX
Note: When the X’tal is not used as clock comparison for fs detection (i.e. XTL1/0 pins= “H”), the X’tal is off. When the clock source is PLL in Mode 0 and Mode 2, the MCKO2 pin is fixed to “L”. Table 5. Clock Operation Mode select
The AK4118A has two methods for detecting the sampling frequency as follows.
- Clock comparison between recovered clock and X’tal oscillator
- Sampling frequency information on channel status
Those could be selected by XTL1/0 pins. And the detected frequency is reported on FS3-0 and PEM bits. Table 6. Reference X’tal frequency Note 12. When consumer mode, Byte3 Bit3-0 are copied to FS3-0. Note 13. In professional mode, FS3-0 bits are always “0001” except for the frequencies listed in the table. Table 7. Sampling Frequency Information default. It can be switched to channel 2 by CS12 bit in control register.
0 OFF ≠ 0X100
1 ON 0X100
Table 8. PEM in Consumer Mode
0 OFF ≠110
1 ON 110
Table 9. PEM in Professional Mode
sampling frequency and pre-emphasis information in the channel status. The AK4118A is in this mode as default. Table 10. De-emphasis Auto Control at DEAU = “1” (default) Table 11. De-emphasis Manual Control at DEAU = “0” The AK4118A has a power-down mode for all circuits by the PDN pin, and can be partially powerd-down by PWN bit. enabled. The AK4118A should be reset once by bringing the PDN pin = “L” upon power-up. the registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled. are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled.
pin. When the signal is input to the RX pin, RXDE bit = “1”. Table 12. Recovery Data Select Figure 13. B, C, U, V output timings
mode is only available when PLL is locked in the master mode. Table 13. Output Data Select for TX0 Table 14. Output Data Select for TX1 Figure 14. DAUX and VIN input timings
biphase data are used. In this case, one frame is 96kHz and LRCK frequency is 192kHz. When MONO bit = “1”, the AK4118A outputs mono data from SDTO as follows.
1 LRCK
Figure 15. MONO Mode (RX) Figure 16. MONO mode Connection Example (RX)
MONO bit = “1” and TLR bit = “1”, then Rch data is output. Figure 17. MONO Mode (TX) Figure 18. MONO Mode Connection Example (TX)
(1) Reset all the AK4118A’s by the PDN pin = “L” → “H” or RSTN bit = “0” → “1”. (2) Set all the AK4118A’s to MONO mode while they are still in slave mode. LRCK externally to all the AK4118A’s at the same time. Figure 19. MONO Mode Setup Sequence (TX)
[AK4118A] MS1130-E-02 2009/12 - 27 - ■ Error Handling The following nine events cause the INT0 and INT1 pins to show the status of the interrupt condition. When the PLL is OFF (Clock Operation Mode 1), INT0 and INT1 pins go to “L”. 1. UNLCK : PLL unlock state detect “1” when the PLL loses lock. The AK4118A loses lock when the distance between two preamble is not correct or when those preambles are not correct. 2. PAR : Parity error or bi-phase coding error detection “1” when parity error or bi-phase coding error is detected, updated every sub-frame cycle. 3. AUTO : Non-Linear PCM or DTS-CD Bit Stream detection The OR function of NPCM and DTSCD bits is available at the AUTO bit. 4. V : Validity flag detection “1” when validity flag is detected. Updated every sub-frame cycle. 5. AUDION : Non-audio detection “1” when the “AUDION” bit in recovered channel status indicates “1”. Updated every block cycle. 6. STC : Sampling frequency or pre-emphasis information change detection When either FS3-0 bit or PEM bit is changed, it maintains “1” during 1 sub-frame. 7. QINT : U-bit Sync flag “1” when the Q-subcode differs from the old one. Updated every sync code cycle for Q-subcode. 8. CINT : Channel status sync flag “1” when received C bit differs from the old one. Updated every block cycle. 9. DAT : DAT Start ID detect “1” when the category code indicates “DAT” and “DAT Start ID” is detected. When DCNT bit is “1”, it does not indicate “1” even if “DAT Start ID” is detected again within “3841 x LRCK”. When “DAT Start ID” is detected again after “3840 x LRCK” passed, it indicates “1”. When DCNT bit is “0”, it indicates “1” every “DAT Start ID” detection.
all error events are removed. Table 15 shows the state of each output pins when the INT0/1 pin is “H”. Note 14. The INT1 pin outputs “L” or “H” in accordance with the ORed signal between AUTO and AUDION. Note 15. The INT0 pin outputs “L” or “H” in accordance with the ORed signal between UNLCK and PAR. Table 15. Error Handling in parallel control mode (x: Don’t care) QINT, CINT and DAT bits goes to “1”, it stays “1” until the register is read. Table 16. Error Handling in serial control mode (x: Don’t care)
Figure 26. INT0/1 pin Timing
Figure 27. Error Handling Sequence Example 1
Figure 28. Error Handling Sequence Example (for Q/CINT)
last 4LSBs are auxiliary data (Figure 29). Clock Operation Mode 1/3 and unlock state of Mode 2. Figure 29. Bit Configuration Table 17. Audio Data Format
state of GPIO registers, BCU bit, TX1E/TX0E bit and VIN E bit. Table 18. VINGP0 pin and Internal Statement (x: Don’t care) Table 19. GP1 pin and Internal Statement (x: Don’t care) Table 20. TX0/1 GP2/3 pin and Internal Statement (x: Don’t care) Table 21. B/C/U/VOUT GP4/5/6/7 pin and Internal Statement (x: Don’t care)
pin is changed, the AK4118A should be reset by the PDN pin= “L”. Figure 34. 4-wire Serial Control I/F Timing
[AK4118A] MS1130-E-02 2009/12 - 40 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H CLK & Power Down Control CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN 01H Format & De-em Control MONO DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS 02H Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 03H Input/ Output Control 1 EFH1 EFH0 UDIT TLR DIT IPS2 IPS1 IPS0 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MDTS0 MPE0 MAUD0 MPAR0 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MDTS1 MPE1 MAUD1 MPAR1 06H Receiver status 0 QINT AUTO CINT UNLCK DTSCD PEM AUDION PAR 07H Receiver stat us 1 FS3 FS2 FS1 FS0 0 V QCRC CCRC 08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 0DH TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 0EH TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10 CT9 CT8 0FH TX Channel Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17 CT16 10H TX Channel Status Byte 3 CT31 CT30 CT29 CT28 CT27 CT26 CT25 CT24 11H TX Channel Status Byte 4 CT39 CT38 CT37 CT36 CT35 CT34 CT33 CT32 12H Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 13H Burst Preamble Pc Byte 1 PC15 PC 14 PC13 PC12 PC11 PC10 PC9 PC8 14H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 15H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 16H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 17H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 18H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 19H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 1AH Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 1BH Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 1CH Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1DH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1EH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1FH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74
[AK4118A] MS1130-E-02 2009/12 - 41 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 20H GPE GPE RXDETE VINE FAST EXCKMD DCNT DTS16 DTS14 21H GPDR IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 22H GPSCR CS7 SC6 CS5 SC4 SC3 SC2 SC1 CS0 23H GPLR GPL7 GPL 6 GPL 5 GPL 4 GPL 3 GPL 2 GPL 1 GPL 0 24H DAT Mask & DTS Detect XMCK DIV MED1 MDR0 MSTC1 MSTC0 MDAT1 MDAT0 25H RX Detect RXDE7 RXDE6 R XDE5 RXDE4 RXDE3 RXDE2 RXDE1 RXDE0 26H STC & DAT Detect 0 0 0 0 0 0 STC DAT 27H RX Channel Status Byte 5 0 0 0 0 0 0 CR41 CR40 28H TX Channel Status Byte 5 0 1 0 0 0 0 CT41 CT40 Note: When the PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values. All data can be written to the register even if PWN bit is “0”.
[AK4118A] MS1130-E-02 2009/12 - 42 - ■ Register Definitions Reset & Initialize Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H CLK & Power Down Control CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 0 0 0 0 1 1 RSTN: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation PWN: Power Down 0: Power Down 1: Normal Operation OCKS1-0: Master Clock Frequency Select CM1-0: Master Clock Operation Mode Select BCU: Block start & C/U Output Mode When BCU=1, the three Output Pins(BOUT, COUT, UOUT) become to be enabled. The block signal goes high at the start of frame 0 and remains high until the end of frame 31. CS12: Channel Status Select 0: Channel 1 1: Channel 2 Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0, Pc and Pd. The de-emphasis filter is controlled by channel 1 in the Parallel Mode. Format & De-emphasis Control Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Format & De-em Control MONO DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 0 1 0 1 0 DFS: 96kHz De-emphasis Control DEM1-0: 32, 44.1, 48kHz De-emphasis Control (Table 11) DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable DIF2-0: Audio Data Format Control (Table 17) MONO: Double sampling frequency mode enable 0: Stereo mode 1: Mono mode
[AK4118A] MS1130-E-02 2009/12 - 43 - Input/Output Control Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 0 1 0 0 0 OPS02-00: Output Through Data Select for TX0 pin OPS12-10: Output Through Data Select for TX1 pin TX0E: TX0 Output Enable 0: Disable. TX0 outputs “L”. 1: Enable TX1E: TX1 Output Enable 0: Disable. TX1 outputs “L”. 1: Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Input/ Output Control 1 EFH1 EFH0 UDIT TLR DIT IPS2 IPS1 IPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 0 0 1 0 0 0 IPS2-0: Input Recovery Data Select DIT: Through data/Transmit data select for TX1 pin 0: Through data (RX data). 1: Transmit data (DAUX data). TLR: Double sampling frequency mode channel select for DIT(stereo) 0: L channel 1: R channel UDIT: U bit control for DIT 0: U bit is fixed to “0” 1: Recovered U bit is used for DIT (loop mode for U bit) EFH1-0: Interrupt 0 Pin Hold Count Select 00: 512 LRCK 01: 1024 LRCK 10: 2048 LRCK 11: 4096 LRCK
[AK4118A] MS1130-E-02 2009/12 - 44 - Mask Control for INT0 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H INT0 MASK MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 0 1 1 1 0 MPR0: Mask Enable for PAR bit MAN0: Mask Enable for AUDN bit MPE0: Mask Enable for PEM bit MDTS0: Mask Enable for DTSCD bit MUL0: Mask Enable for UNLOCK bit MCI0: Mask Enable for CINT bit MAT0: Mask Enable for AUTO bit MQI0: Mask Enable for QINT bit 0: Mask disable 1: Mask enable Mask Control for INT1 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H INT1 MASK MQI1 MAT1 MCI1 MUL1 MDTS1 MPE1 MAN1 MPR1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 1 1 0 1 0 1 MPR1: Mask Enable for PAR bit MAN1: Mask Enable for AUDN bit MPE1: Mask Enable for PEM bit MDTS1: Mask Enable for DTSCD bit MUL1: Mask Enable for UNLOCK0 bit MCI1: Mask Enable for CINT bit MAT1: Mask Enable for AUTO bit MQI1: Mask Enable for QINT bit 0: Mask disable 1: Mask enable
[AK4118A] MS1130-E-02 2009/12 - 45 - Receiver Status 0 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Receiver status 0 QINT AUTO CINT UNLCK DTSCD PEM AUDION PAR R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 PAR: Parity Error or Biphase Error Status 0:No Error 1:Error It is “1” if Parity Error or Biphase Error is detected in the sub-frame. AUDION: Audio Bit Output 0: Audio 1: Non Audio This bit is made by encoding channel status bits. PEM: Pre-emphasis Detect. 0: OFF 1: ON This bit is made by encoding channel status bits. DTSCD: DTS-CD Auto Detect 0: No detect 1: Detect UNLCK: PLL Lock Status 0: Locked 1: Unlocked CINT: Channel Status Buffer Interrupt 0: No change 1: Changed AUTO: Non-PCM Auto Detect 0: No detect 1: Detect QINT: Q-subcode Buffer Interrupt 0: No change 1: Changed QINT, CINT and PAR bits are initialized when 06H is read. Receiver Status 1 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Receiver stat us 1 FS3 FS2 FS1 FS0 0 V QCRC CCRC R/W RD RD RD RD RD RD RD RD Default 0 0 0 1 0 0 0 0 CCRC: Cyclic Redundancy Check for Channel Status 0:No Error 1:Error QCRC: Cyclic Redundancy Check for Q-subcode 0:No Error 1:Error V: Validity of channel status 0:Valid 1:Invalid FS3-0: Sampling Frequency detection (Table 7)
[AK4118A] MS1130-E-02 2009/12 - 46 - Receiver Channel Status Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 27H RX Channel Status Byte 5 0 0 0 0 0 0 CR41 CR40 R/W RD Default Not initialized CR41-0: Receiver Channel Status Byte 5-0 Transmitter Channel Status Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 0EH TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10 CT9 CT8 0FH TX Channel Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17 CT16 10H TX Channel Status Byte 3 CT31 CT30 CT29 CT28 CT27 CT26 CT25 CT24 11H TX Channel Status Byte 4 CT39 CT38 CT37 CT36 CT35 CT34 CT33 CT32 28H TX Channel Status Byte 5 0 1 0 0 0 0 CT41 CT40 R/W R/W Default 0 CT41-0: Transmitter Channel Status Byte 5-0 Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 12H Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 13H Burst Preamble Pc Byte 1 PC 15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 14H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 15H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 R/W RD Default Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1
[AK4118A] MS1130-E-02 2009/12 - 47 - Q-subcode Buffer Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 16H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 17H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 18H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 19H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 1AH Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 1BH Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 1CH Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1DH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1EH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1FH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 R/W RD Default Not initialized GPIO Control Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 20H GPE GPE RXDETE VINE FAST EXCKMD DCNT DTS16 DTS14 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 1 0 1 1 1 DTS14: DTS-CD 14bit Sync Word Detect 0: Disable 1: Enable (default) DTS16: DTS-CD 16bit Sync Word Detect 0: Disable 1: Enable (default) DCNT: Start ID Counter 0: Disable 1: Enable (default) EXCKMD: X’tal Oscillator Setting 0: Power Up (default) 1: Power Down FAST: PLL Lock Time Select ( Table 1) 0: ≤ (15ms + 384/fs) (default) 1: ≤ (15ms + 1/fs) VINE: VIN Input Enable 0: Disable 1: Enable (default) RXDETE: RX Input Detect Enable 0: Disable 1: Enable (default) GPE: GPIO mode Enable 0: GPIO mode Disable (default) 1: GPIO mode Enable GPIO mode for GP2-7 pins is enabled when GPE bit= “1” and BCU bit= TX1E bit= TX0E bit= “0”. The GP0 pin is in GPIO mode regardless of the state of GPE bit when VINE bit= “0”. The GP1 pin is always in GPIO mode.
[AK4118A] MS1130-E-02 2009/12 - 48 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 21H GPDR IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 IO7-0: GPIO pin Input/Output Setting 0: Input (default) 1: Output Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 22H GPSCR SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SC7-0: GPIO pin Output Level Setting 0: “L” (default) 1: “H” This is effective only when the pin setting is in output mode (21H: GPDR= “1”). Actual pin level can be read by GPLR register. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 23H GPLR GPL7 GPL6 GPL5 GPL4 GPL3 GPL2 GPL1 GPL0 R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 GPD7-0: GPIO pin Input Level Read GLP7-0 bits are read only regist er that can read the input signal level of corresponding GPIO pins (GP7-0 pins). GPIO mode is enabled GP2-7 pins can read the input signal level when GPE bit = “1” and BCU bit = TX1E bit = TX0E bit = “0”. When VINE bit = “0”, GPIO mode of the GP1 pin is enabled and GPLO bit can read the input signal leve l. GPL1 bit can always read the input signal level of the GP1 pin. GPL2-7 bits and GPL0 bit are always “0” when GPIO mode is disable.
[AK4118A] MS1130-E-02 2009/12 - 49 - DAT Mask & DTS Detect Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 24H DAT Mask & DTS Detect XMCK DIV MRDT1 MRDT0 MSTC1 MSTC0 MDAT1 MDAT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 1 1 1 1 1 MDAT0: Mask enable for DAT bit 0: Mask disable 1: Mask enable (default) When the Mask is enabled “1”, DAT state is not reflected on to the INT0 pin. MDAT1: Mask enable for DAT bit 0: Mask disable 1: Mask enable (default) When the Mask is enabled “1”, DAT state is not reflected on to the INT1 pin. MSTC0: Mask enable for STC bit 0: Disable 1: Enable (default) When the Mask is enabled “1”, STC stat e is not reflected on to the INT0 pin. MSTC1: Mask enable for STC bit 0: Disable 1: Enable (default) When the Mask is enabled “1”, STC stat e is not reflected on to the INT1 pin. MRDT0: Mask enable for RX Detect 0: Disable 1: Enable (default) When the Mask is enabled “1”, RX input detection resault is not reflected on to the INT0 pin. MRDT1: Mask enable for RX Detect 0: Disable 1: Enable (default) When the Mask is enabled “1”, RX input detection resault is not reflected on to the INT1 pin. DIV: MCKO2 Frequency Dividing Ratio in X’tal mode ( Table 4) 0: x1 (default) 1: x 1/2 XMCK: MCKO2 Output Setting (Table 4) 0: Setting by CM1-0 bits and OCKS1-0 bits (default) 1: Fixed in X’tal mode RX Detect Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 25H RX Detect RXDE7 RXDE6 R XDE5 RXDE4 RXDE3 RXDE2 RXDE1 RXDE0 R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 RXDE7-0: The RX pin Input Detect 0: No Detect 1: Detect When the RXDETE bit is set to “0”, the input detection function is disabled and the register is fixed to “0”. When the unused RX pin is open, the AK4118A may not be able to detect the input signal correctly. The unused RX pin should be connected to the GND.
DAT bit is initialized when Addr= 26H is READ. Figure 44. Data structure in IEC60958 Table 22. Burst preamble words
Table 23. Fields of burst info Pc
Figure 47 shows the example of system connection diagram for Serial Mode.
12 VIN
24 LRCK
Figure 47. Typical Connection Diagram (Serial Mode)
- For XTL0 and XTL1settings, refer to the Table 5.
- “C” value is dependent on the crystal.
- VSS1-4 must be connected the same ground plane.
[AK4118A] MS1130-E-02 2009/12 - 54 - PACKAGE 1 12 48 13 7.0 9.0 ± 0.2 7.0 9.0 ± 0.2 0.22 ± 0.08 48pin LQFP(Unit:mm) 0.10 37 24 25 36 1.40 ± 0.05 0.13 ± 0.13 1.70Max 0° ∼ 10° 0.10 M0.5 0.09~0.20 0.3~0.75 ■ Material & Lead finish Package molding compound: Epoxy, Halogen (bromine and chlorine) free Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
[AK4118A] MS1130-E-02 2009/12 - 55 - MARKING AK4118AEQ XXXXXXX XXXXXXXX: Date code identifier Date (YY/MM/DD) Revision Reason Page Contents 09/10/06 00 First Edition 09/10/21 01 Error Correction 39 ■ Register Map Addr 11H, D6~D1: CT39 → CT38 ~ 33
45 Transmitter Channel Status
Addr 28H, D0: CT42 → CT40 09/12/24 02 Description 4 “ ■ Compatibility with AK4118” was added. Addition 16 A description about Table 3 was added.
REVISION HISTORY
[AK4118A] MS1130-E-02 2009/12 - 56 - IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these produc ts, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor auth orized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.