AK8180A AKM | Alldatasheet

Document overview

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Technical content

Features

Configurable 3-bank 10 LVCMOS outputs Selectable two LVCMOS inputs Single, dual and mixed voltage supply available on 2.5V and 3.3V Clock output frequency up to 250MHz Output-to-output skew : 200ps max Tri-state outputs Enable to drive up to 20 series terminated clock lines Operating Temperature Range: -40 to +85℃ Package: 32-pin LQFP (Pb free) Pin compatible with MPC9446

Description

The AK8180A is a member of AKM’ｓ LVCMOS clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew. The AK8180A distributes 10 buffered clocks configured by pin-setting per bank. Each bank has the selected output divided by one or two through DSELx pin. Each of 3-bank outputs operate at 2.5V or 3.3V respectively. The 10 outputs can drive terminated 50 W transmission lines. The AK8180A is available in a 7mm x 7mm 32-pin LQFP package. Block Diagram 2.5V, 3.3V LVCMOS 1:10 Clock Fanout Buffer AK8180A

  • 2 - Pin Descriptions 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 V D D B G N D Q B 0 V D D B Q B 1 G N D Q B 2 V D D C QC0 QC3 GND QC2 VDDC QC1 GND VDDC GND VDDA QA2 GND QA1 VDDA QA0 AK8180A D S E L C C C L K _ S E L V D D C C L K 0 C C L K 1 D S E L A D S E L B G N D MR/OE Package: 32-Pin LQFP(Top View) Pin No. Pin Name Pin Type Pullup /down Description 1 CCLK_SEL IN PD CCLK Select Input.

2 VDD -- -- Power Supply for Core

3 CCLK0 IN PU Clock Inputs

4 CCLK1 IN PU Clock Inputs

5 DSELA IN PD Divide Select Input for Output Bank A

6 DSELB IN PD Divide Select Input for Output Bank B

7 DSELC IN PD Divide Select Input for Output Bank C

8, GND -- -- Ground

9 VDDC -- -- Power Supply for Output bank C

10 QC0 OUT --- Clock output Bank C

11 GND -- -- Ground

12 QC1 OUT --- Clock output Bank C

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  • 3 - Pin No. Pin Name Pin Type Pullup /down Description

13 VDDC -- -- Power Supply for Output bank C

14 QC2 OUT --- Clock output Bank C

15 GND -- -- Ground

16 QC3 OUT --- Clock output Bank C

17 VDDC -- -- Power Supply for Output bank C

18 VDDB -- -- Power Supply for Output bank B

19 QB2 OUT --- Clock output Bank B

20 GND -- -- Ground

21 QB1 OUT --- Clock output Bank B

22 VDDB -- -- Power Supply for Output bank B

23 QB0 OUT --- Clock output Bank B

24 GND -- -- Ground

25 VDDA -- -- Power Supply for Output bank A

26 QA2 OUT --- Clock output Bank A

27 GND -- -- Ground

28 QA1 OUT --- Clock output Bank A

29 VDDA -- -- Power Supply for Output bank A

30 QA0 OUT --- Clock output Bank A

31 GND -- -- Ground

32 OE MR/ IN PD Master Reset and Output Enable

(Output disable = High impedance) PU: Pull up PD: Pull down

Ordering Information

Part Number Marking Shipping Packaging Package Temperature Range AK8180A AK8180A Tape and Reel 32-pin LQFP -40 to 85 ℃

  • 4 - Absolute Maximum Rating Over operating free-air temperature range unless otherwise noted (1) Items Symbol Ratings Unit Supply voltage VDD -0.3 to 4.6 V Input voltage Vin GND-0.3 to VDD+0.3 V Input current (any pins except supplies) I IN ±10 mA Storage temperature Tstg -55 to 130 °C (1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. This device is manufactured on a CMOS process, therefore, generically susceptible to damage by excessive static voltage. Failure to observe proper handling and installation procedures can cause damage. AKM recommends that this device is handled with appropriate precautions. Recommended Operation Conditions Parameter Symbol Conditions Min Typ Max Unit Operating temperature Ta -40 85 °C 2.375 2.5 2.625 Supply voltage (1) VDD, VDDA VDDB, VDDC ±5% 3.135 3.3 3.465 V (1) Supply voltages require to be supplied from each single source of 2.5V or 3.3V. A decoupling capacitor of 0.1 mF for power supply line should be located close to each VDD pin. Supported VDD Supply Voltage Configurations Supply Voltage Configuration VDD VDDA VDDB VDDC GND General Specification Parameter Symbol Conditions Min Typ Max Unit Output Termination Voltage VTT VDD/2 V ESD Protection 1 MM Machine model 200 V ESD Protection 2 HBM Human Body Model 2000 V Latch-Up Immunity LU 200 mA Input Capacitance C IN 4.0 pF ESD Sensitive Device
  • 5 - Power Supply Current <3.3V> VDD=VDDA=VDDB=VDDC= 3.3V±5%, Ta: -40 to +85 ℃ Parameter Symbol Conditions Min Typ Max Unit Full operation (1) IDD1 CCLK0=250MHz CCLK1=H 84 105 mA Quiescent state (1) IDD2 CCLK0=H CCLK1=H 0.8 1.7 mA (1) The outputs have no loads. CCLK_SEL=L, DSELA=DSELB=DSELC=L, OE MR/=L DC Characteristics <3.3V> All specifications at VDD=VDDA=VDDB=VDDC= 3.3V±5%, Ta: -40 to +85 ℃, unless otherwise noted Parameter Symbol Conditions MIN TYP MAX Unit High Level Input Voltage V IH LVCMOS 2.0 VDD+0.3 V Low Level Input Voltage V IL LVCMOS -0.3 0.8 V Input Current (1) IL1 Vin=GND or VDD -200 +200 μA High Level Output Voltage V OH IOH= -24mA (2) 2.4 V Low level Output Voltage V OL IOL= +24mA (2) IOL= +12mA 0.55 0.30 V Output Impedance Z OUT 14-17 W (1) Input pull-up / pull down resistors influence input current. (2) The AK8180A is capable of driving 50 W transmission lines of the incident edge. Each output drives one 50 W parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 W series terminated transmission lines. AC Characteristics <3.3V> (1) All specifications at VDD=VDDA=VDDB=VDDC= 3.3V±5%, Ta: -40 to +85 ℃, unless otherwise noted (1) AC characteristics apply for parallel output termination of 50 W to VTT. (2) The AK8180A is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz. (3) Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, input pulse width, output duty cycle and maximum frequency specifications. (4) Output pulse skew t skO is the absolute difference of the propagation delay times:| t PLH - tPHL |. (5) Output duty cycle is frequency dependent (= 0.5 ± tskO x fout). For example at fout = 125 MHz the output duty cycle limit is 50% ± 2.5%. Parameter Symbol Conditions MIN TYP MAX Unit Input Frequency (2) f IN CCLK0,1 250 MHz Input Pulse Width t pwIN CCLK0,1 1.4 ns Input Rise/Fall time (3) t rIN,tfOUT CCLK0,1 0.8 to 2.0V 1.0 ns Output Frequency (2) f OUT DSELA,B,C= 0 x1 output DSELA,B,C= 1 x1/2 output 250

125 MHz

CCLK0,1 to any Q CCLK0,1 to any Q 1.15 1.15 2.0 2.0 3.4 3.4 ns Output Disable Time t PLZ,tPHZ 10 ns Output Enable Time t PZL,tPZH 10 ns Output-to-Output Skew t sk(O) Within one bank Any output, same output divider Any output, Any output divider 150 200 350 ps Device-to-Device Skew t skPP 2.25 ns Output Pulse Skew (4) t sk(P) 200 ps Output Duty Cycle (5) DC OUT DCREF= 50% x1 output DCREF= 25-75% x1/2 output 53 % Output Rise/Fall Time t r, tf 0.55 to 2.4V 0.1 1.0 ns

  • 6 - Power Supply Current <2.5V> VDD=VDDA=VDDB=VDDC= 2.5V±5%, Ta: -40 to +85 ℃ Parameter Symbol Conditions Min Typ Max Unit Full operation (1) IDD1 CCLK0=250MHz CCLK1=H 62 75 mA Quiescent state (1) IDD2 CCLK0=H CCLK1=H 0.5 1.0 mA (1) The outputs have no loads. CCLK_SEL=L, DSELA=DSELB=DSELC=L, OE MR/=L DC Characteristics <2.5V> All specifications at VDD=VDDA=VDDB=VDDC= 2.5V±5%, Ta: -40 to +85 ℃, unless otherwise noted Parameter Symbol Conditions MIN TYP MAX Unit High Level Input Voltage V IH LVCMOS 1.7 VDD+0.3 V Low Level Input Voltage V IL LVCMOS -0.3 0.7 V Input Current (1) IL1 Vin=GND or VDD -200 +200 μA High Level Output Voltage V OH IOH= -15mA (2) 1.8 V Low level Output Voltage V OL IOL= +15mA (2) 0.6 V Output Impedance Z OUT 17-20 W (1) Input pull-up / pull down resistors influence input current. (2) The AK8180A is capable of driving 50 W transmission lines of the incident edge. Each output drives one 50 W parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 W series terminated transmission lines. AC Characteristics <2.5V> (1) All specifications at VDD=VDDA=VDDB=VDDC= 2.5V±5%, Ta: -40 to +85 ℃, unless otherwise noted (1) AC characteristics apply for parallel output termination of 50 W to VTT. (2) The AK8180A is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz. (3) Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, input pulse width, output duty cycle and maximum frequency specifications. (4) Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |. Parameter Symbol Conditions MIN TYP MAX Unit Input Frequency (2) f IN CCLK0,1 250 MHz Input Pulse Width t pwIN CCLK0,1 1.4 ns Input Rise/Fall time (3) t rIN,tfOUT CCLK0,1 0.7 to 1.7V 1.0 ns Output Frequency (2) f OUT DSELA,B,C= 0 x1 output DSELA,B,C= 1 x1/2 output 250 125 MHz Propagation Delay tPLH tPHL CCLK0,1 to any Q CCLK0,1 to any Q 1.3 1.3 2.4 2.4 4.3 4.3 ns Output Disable Time t PLZ,tPHZ 10 ns Output Enable Time t PZL,tPZH 10 ns Output-to-Output Skew t sk(O) Within one bank Any output, same output divider Any output, Any output divider 150 200 350 ps Device-to-Device Skew t skPP 3.0 ns Output Pulse Skew (4) t sk(P) 200 ps Output Duty Cycle DC OUT DC REF= 50% x1 or 1/2 output 45 50 55 % Output Rise/Fall Time t r, tf 0.6 to 1.8V 0.1 1.0 ns
  • 9 - Function Table The following table shows the inputs/outputs clock state configured through the control pins. Table 1: Control-Pin-Setting Function Table Control Pin Default 0 1 CCLK_SEL 0 CCLK0 CCLK1 DSELA 0 QA0-2 = REFCLK x 1 QA0-2 = REFCLK x 1/2 DSELB 0 QB0-2 = REFCLK x 1 QB0-2 = REFCLK x 1/2 DSELC 0 QC0-3 = REFCLK x 1 QC0-3 = REFCLK x 1/2 OE MR/ 0 Output enabled Internal reset. Outputs disabled. (High impedance) REFCLK is the selected input clock through the CCLK_SEL pin.
  • 10 -

Package Information

  • Mechanical data : 32-lead LQFP 0゜～7゜ 0 . 0 5 ～ 0 . 1 5 0 . 0 9 ～ 0 . 2 0 0.20 M 0.37±0.05 1 8 1724 7.00 9.00±0.20 9 . 0 0 ± 0 . 2 0 7 . 0 0 0.80 0.60±0.10 1 . 6 0 M A X 1 . 3 5 ～ 1 . 4 5 S S0.10
  • 11 -
  • Marking a: #1 Pin Index b: Part number c: Date code (7 digits) AKM and the logo - - are the brand of AKM’ ｓ IC’s and identify that AKM continues to offer the best choice for high performance mixed-signal solution under this brand.
  • RoHS Compliance All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in “lead-free” packages* are fully compliant with RoHS. (*) RoHS compliant products from AKM are identified with “Pb free” letter indication on product label posted on the anti-shield bag and boxes. a b c
  • 12 - IMPORTANT NOTICE  These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products.  Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein.  Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.  AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.  It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.