AK7736BVQ AKM | Alldatasheet
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[AK7736B] MS1562-E-00-PB 2013/10 - 1 - 1. General Description The AK 7736B is a highly integrated audio digital signal processor with integrated 2ch SRC. It includes internal memories for digital audio processing, that allows surround effect process, time alignment and parametric equalizing. Moreover, the AK7736B can process both data and filter coefficients as floating point data so that high accuracy IIR/FIR filter performance can be achieved easily. The AK 7736B can operate a hands-free software by AKM as well as sound processing, by programs downloaded via the microprocessor interface. 2. Features □ DSP Block - Word length: 24-bit - Machine Cycle: 8.1 ns (2560step/fs; fs = 48kHz) - Step fs=48kHz: Maximum 2560 step fs=8kHz: Maximum 15360step fs=16kHz: Maximum 7680step - Multiplication: 20 x 24 → 44-bit (Double precision arithmetic available) - Divider 20 / 20 → 20-bit (floating point normalization function) - ALU: 48-bit arithmetic and logic operation (overflow margin 4-bit) - Shift: Multiple DBUS ±15bit Shift with indirect shifting function - Program RAM (PRAM): 6144word x 36-bit - Coefficient RAM (CRAM): 4096word x 24-bit - Data RAM (DRAM): 4096 x 24-bit (Variable Bank Size) - Offset Register (OFREG): 32word x 15-bit - Delay RAM (DLRAM): 16384word x 24-bit (Variable Bank Size) - Register: 48-bit × 4 (ACC) [ALU] 24-bit × 12 (TMP) [DBUS connection] 24-bit × 6 level stack (PTMP) [DBUS connection] □ Stereo 24-bit SRC -SRC: FSI=8kHz to 96kHz / FSO=8kHz to 96kHz (FSO/FSI = 0.167 to 6.0) □ Mono 24-bit Simple SRC -FSCONV: FSI=44.1kHz to 48kHz / FSO=8kHz to 16kHz □ Digital Interface Input/Output - 8ch Serial Data Inputs - 8ch Serial Data Outputs - Sampling Frequency: 8kHz to 96kHZ □ Microcontroller Interface: SPI, I2CBUS (400kHz Fast-Mode) □ PLL □ Power Supply -VDD: 3.0 to 3.6V typ 3.3V (Internal Regulator) -TVDD: 1.7 to 3.6V (1~8pin) □ Operating Temperature Range: -40°C to 85°C □ Package: 48-pin LQFP Audio/HF DSP with 2Ch SRC AK7736B
[AK7736B] MS1562-E-00-PB 2013/10 - 2 - 3. Table of Contents
- Block Diagram and Functions
Figure 1. Block Diagram
Figure 2. AK7736B Main DSP Block Diagram
[AK7736B] MS1562-E-00-PB 2013/10 - 5 - 5. Pin Configurations and Functions ■ Ordering Guide AK7736BVQ -40 to +85C 48-pin LQFP (0.5mm pitch) AKD7736B Evaluation Board for AK7736B ■ Pin Layout AK7736BLQFP Note) ** is an Internal pull-down pin. *: Pin Name Input Output I/O Power PIN TESTI1 SDOUT2B SDOUT1 SDIN1 SDIN2B TESTI3 BITCLK1 LRCLK1 TVDD VSS XTI XTO SDOUT4 SDOUT3 SDOUT2A RDY VSS VDD I2CSEL PDN SDIN2A LRCLKO BITCLKO CLKO STO SO LRCLKI2/JX2 BITCLKI2/JX1 SDIN4 CSN/CAD1 SI/CAD0 SDA SCLK/SCL VDD VSS AVDRV SDIN3 VSS VDD BITCLKI3 LRCLKI3 SDIN2C JX0 EXPDN VDD VSS LFLT 48pin LQFP (TOP VIEW) TESTI2
[AK7736B] MS1562-E-00-PB 2013/10 - 6 - ■ Pin Functions No Name I/O Function Classification
1 TESTI1 I Test Pin (Internal pull-down)
This pin must be connected to VSS. Test
2 SDOUT2B O Serial Data2 B Output Pin Serial Data
3 SDOUT1 O Serial Data1 Output Pin
4 SDIN1 I Serial Data1 Input Pin Serial Data
5 SDIN2B I Serial Data2 B Input Pin
6 TESTI3 I Test Pin (Internal pull-down)
This pin must be connected to VSS Test
7 BITCLK1 I/O Serial Bit Clock Pin 1 (Internal pull-down) System Clock
8 LRCLK1 I/O LR Channel Select Clock Pin 1 (Internal pull-down)
9 TVDD - Power Supply Pin for 1pin-8pin I/O 1.7 to 3.6V Power Supply
10 VSS - Ground Pin 0V
11 XTI I Crystal Oscillator Input Pin
Connect a crystal oscillator between this pin and the XTO pin, or input an external clock to the XTI pin. System Clock
12 XTO O Crystal Oscillator Output Pin
When a crystal oscillator is used, connect it between XTI and XTO. When an external clock is used, leave this pin open.
13 SDOUT4 O Serial Data4 Output Pin Serial Data
14 SDOUT3 O Serial Data3 Output Pin
15 SDOUT2A O Serial Data2 A Output Pin
16 RDY O RDY Pin Status
17 VSS - Ground Pin 0V Power Supply
18 VDD - Power Supply Pin 3.0 to 3.6V (typ. 3.3V)
19 I2CSEL I I2C BUS Select Pin
I2CSEL= “L”: SPI Interface I2CSEL= “H”: I2CBUS Interface I2CSEL should be connected to “L” (VSS) or “H” (VDD). I2C
20 PDN I Power Down N Pin
The AK7736B is powered-down by this pin. This pin must be set to “L” when power-up the AK7736B Power Down
21 SDIN2A I Serial Data2 A Input Pin Serial Data
22 LRCLKO O LR Channel Select Clock Pin System Clock
23 BITCLKO O Serial Bit Clock Output Pin
24 CLKO O Clock Output Pin Clock Output
25 STO O Status Output Pin Status
26 SO O Control Data Output Pin for Microprocessor Interface
Hi-Z output when the CSN pin = “H” Microprocessor Interface
27 LRCLKI2 I LR Channel Select Clock Pin 2 (for FSCONV) System Clock
JX2 I External Conditional Jump Pin 2 Conditional Input
28 BITCLKI2 I Serial Bit Clock Input Pin 2 (for FSCONV) System Clock
JX1 External Conditional Jump Pin 1 Conditional Input
29 SDIN4 I Serial Data4 Input Pin Serial Data
[AK7736B] MS1562-E-00-PB 2013/10 - 7 -
30 CSN I Microprocessor Interface Request N Pin (I2CSEL pin= “L”)
Set this pin to “H” when not interfacing to a microprocessor or during power-down. Microprocessor Interface CAD1 I I2CBUS Address Pin 1 (I2CSEL pin= “H”) I2C
31 SI I Serial Data Input Pin for Microprocessor Interface
Set this pin to “L” when not using. Microprocessor Interface CAD0 I I2C BUS Address Pin 0 (I2CSEL pin= “H”) I2C
32 SDA O Control Data Input /Output Pin (I2CSEL pin= “L”)
“Hi-Z” Output. This pin must be open when the I2CSEL pin = “L”. Open I/O Control Data Input /Output Pin (I2CSEL pin= “H”) SDA: I2C BUS Interface I2C
33 SCLK I Control Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”)
Set this pin to “H” when no clock is input. Microprocessor Interface SCL I Control Data Clock Pin (I2CSEL pin= “H”) SCL: I2C BUS Interface I2C 34 VDD - Power Supply Pin 3.0 to 3.6V (typ. 3.3V) Power Supply
35 VSS - Ground Pin 0V
36 AVDRV AVDRV pin
Connect a 1F capacitor between this pin and the VSS pin (No. 35). No external circuits should be connected to this pin. Analog Output
37 SDIN3 I Serial Data3 Input Pin Serial Data
38 VSS - Ground Pin 0V Power Supply
39 VDD - Power Supply Pin 3.0 to 3.6V (typ. 3.3V)
40 BITCLKI
I Serial Bit Clock Input Pin 3 (for SRC) System Clock
41 LRCLKI3 I LR Channel Select Clock Pin 3 (for SRC)
42 SDIN2C I Serial Data2 C Input Pin Serial Data
43 JX0 I External Conditional Jump Pin 0 Conditional
44 EXPDN O Power Down Signal Output Pin Power Down
45 VDD - Power Supply Pin 3.0 to 3.6V (typ. 3.3V) Power Supply
46 TESTI2 I Test Pin (internal pull-down)
This pin must be connected to VSS. Test
47 VSS - Ground Pin 0V Power Supply
48 LFLT O PLL RC Component Connect Pin
Connect C=12nF between this pin and No.47 (VSS) pin. Analog Output Note 1. All digital input pins must not be allowed to float Note 2. The I2CSEL pin must be fixed to “L” (VSS) or “H” (TVDD). ■ Handling of Unused Pin Unused I/O pins must be connected appropriately: Pin Name Setting Output Pins Leave Open Input/Output Pins SDA LRCLK1 BITCLK1 Leave Open Connect to VSS Connect to VSS Input Pins Connect to VSS
[AK7736B] MS1562-E-00-PB 2013/10 - 8 - ■ Output pin Status in Power-down Mode (PDN pin = “L”) No Pin Name I/O Power-down Status No Pin Name I/O Power-down Status
2 SDOUT2B O “L” Output 22 LRCLKO O “L” Output
3 SDOUT1 O “L” Output 23 BITCLKO O “L” Output
7 BITCLK1 I/O Input 24 CLKO O “L” Output
8 LRCLK1 I/O Input 25 STO O “L” Output
12 XTO O “H” Output 26 SO O “Hi-Z” Output
13 SDOUT4 O “L” Output 32 SDA I/O “Hi-Z” Output
14 SDOUT3 O “L” Output 44 EXPDN O “L” Output
15 SDOUT2A O “L” Output 48 LFLT O “L” Output
16 RDY O “L” Output
■ Relationship between the I2CSEL Pin and the SDA Pin I2CSEL PDN SDA SPI L L Hi-Z Interface L H Hi-Z I2C BUS support H L “Hi-Z” → pull-up H H function 6. Absolute Maximum Ratings (VSS=0V: All voltages are with respect to ground) Parameter Symbol min max Unit Power Supply TVDD VDD TVDD VDD -0.3 -0.3 4.3 4.3 V V Input Current (except for power supply pin) IIN – ±10 mA Digital Input Voltage (1pin-8pin) VINDT -0.3 (TVDD+0.3) V Digital Input Voltage (except 1pin-8pin) VIND -0.3 (VDD+0.3) Operating Ambient Temperature Ta -40 85 °C Storage Temperature Tstg -65 150 °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (VSS=0V: All voltages are with respect to ground.) Parameter Symbol min typ max Unit Power Supply TVDD VDD TVDD VDD 1.7 3.0 1.8 3.3 3.6 3.6 V V Note 3. The TVDD pin is the power supply pin for pin number 1 ~ 8 pins. Note 4. The power-up sequence with VDD and TVDD is not critical. The PDN pin should be held “L” when power is supplied. The PDN pin is allowed to be “H” after all power supplies are applied and settled. Note 5. Do not turn off the power supply of the AK7736B with the power supply of the surrounding device turned on. VDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for VDD in the SDA and SCL pins.)
[AK7736B] MS1562-E-00-PB 2013/10 - 9 - 8. Electrical Characteristics ■ SRC Characteristics 1) SRC (Ta= -40°C to 85°C; TVDD=1.8V, VDD=3.3V; VSS=0V; data = 24bit; measurement bandwidth = 20Hz~FSO/2; unless otherwise specified.) Parameter Symbol min typ max Unit Resolution 24 Bits Input Sample Rate FSI 8 96 kHz Output Sample Rate FSO 8 96 kHz THD+N (Input= 1kHz, 0dBFS) FSO/FSI=44.1kHz/48kHz FSO/FSI=44.1kHz/96kHz FSO/FSI=48kHz/44.1kHz FSO/FSI=48kHz/96kHz FSO/FSI=48kHz/8kHz FSO/FSI=16kHz/48kHz FSO/FSI=16kHz/44.1kHz FSO/FSI=8kHz/48kHz FSO/FSI=8kHz/44.1kHz -112 -111 -112 -113 -111 -113 -100 -113 -95 -103 dB dB dB dB dB dB dB dB dB Dynamic Range (Input= 1kHz, -60dBFS) FSO/FSI=44.1kHz/48kHz FSO/FSI=44.1kHz/96kHz FSO/FSI=48kHz/44.1kHz FSO/FSI=48kHz/96kHz FSO/FSI=48kHz/8kHz FSO/FSI=16kHz/48kHz FSO/FSI=16kHz/44.1kHz FSO/FSI=8kHz/48kHz FSO/FSI=8kHz/44.1kHz Dynamic Range (Input= 1kHz, -60dBFS, A-weighted) FSO/FSI=44.1kHz/48kHz 108 113 113 113 113 113 113 113 111 114 115 dB dB dB dB dB dB dB dB dB dB Ratio between Input and Output Sample Rate FSO/FSI 0.167 6 - 2) FSCONV (Ta= -40°C to 85°C; TVDD=1.8V, VDD=3.3V; VSS=0V; data = 24bit; measurement bandwidth = 20Hz~FSO/2; unless otherwise specified.) Parameter Symbol min typ max Unit Resolution 24 Bits Input Sample Rate FSI 44.1 48 kHz Output Sample Rate FSO 8 16 kHz THD+N (Input= 1kHz, 0dBFS) FSO/FSI=16kHz/48kHz FSO/FSI=16kHz/44.1kHz FSO/FSI=8kHz/48kHz FSO/FSI=8kHz/44.1kHz -114 -95 -115 -97 dB dB dB dB Dynamic Range (Input= 1kHz, -60dBFS) FSO/FSI=16kHz/48kHz FSO/FSI=16kHz/44.1kHz FSO/FSI=8kHz/48kHz FSO/FSI=8kHz/44.1kHz Dynamic Range (Input= 1kHz, -60dBFS, A-weighted) FSO/FSI=8kHz/48kHz 114 114 114 114 117 dB dB dB dB dB Ratio between Input and Output Sample Rate FSO/FSI 0.167 0.363 - Note 6. Input signal frequency bandwidth of FSCONV must be attenuated more than 4kHz when the output sampling rate is 8kHz, or must be attenuated more than 8kHz when the output sampling rate is 16kHz.
[AK7736B] MS1562-E-00-PB 2013/10 - 10 - ■ DC Characteristics (Ta= -40°C to 85°C, VSS=0V, VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V) Parameter Symbol min typ max Unit High Level Input Voltage 1 (56H Note 7) VIH1 80%TVDD V Low Level Input Voltage 1 (57H Note 7) VIL1 20%TVDD V High Level Input Voltage 2 (58H Note 8) VIH2 80%VDD V Low Level Input Voltage 2 (59H Note 8) VIL2 20%VDD V SCL, SDA High Level Input Voltage VIH3 70%VDD V SCL, SDA Low Level Input Voltage VIL3 30%VDD V High Level Output Voltage1 Iout= -100A (60H Note 7) 1.7 ≤ TVDD < 3.0 VOH1 TVDD-0.3 V 3.0 ≤ TVDD ≤ 3.6 VOH1 TVDD-0.5 Low Level Output Voltage1 Iout=100A (61H Note 7) 1.7 ≤ TVDD < 3.0 VOL1 0.3 V 3.0 ≤ TVDD ≤ 3.6 VOL1 0.5 High Level Output Voltage2 Iout= -100A (62H Note 8) VOH2 VDD-0.5 V Low Level Output Voltage2 Iout=100A (63H Note 8) VOL2 0.5 V SDA Low Level Output Voltage Iout=3mA VOL3 0.4 V Input Leak Current (64H Note 9) Input Leak Current with pulled-down (65H Note 10) Iin Iid ±10 Note 7. TESTI1, SDOUT2B, SDOUT1, SDIN1, SDIN2B, TESTI3, BITCLK1 and LRCLK1 pins. Pin no. 1 to 8. Note 8. Except 1pin-8pin, SDA and SCL pins Note 9. Pull-down pins, and the XTI pin is not included. Note 10. LRCLK1, BITCLK1, TESTI1, TESTI2 and TESTI3 pins are internal pulled-down pin. (typ. 40.7kΩ) ■ Current Consumption Parameter min typ max Unit Normal Operation Mode (66H Note 11) TVDD 0.3 0.5 mA VDD 31 50 mA Power-down Mode TVDD 0.01 A (PDN = L) VDD 1 A Note 11. The current consumption changes depending on the system frequency and contents of the DSP program.
[AK7736B] MS1562-E-00-PB 2013/10 - 11 - 9. Digital Filter Characteristics ■ SRC Block (Ta= -40°C to 85°C, VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V) Parameter Symbol min typ max Unit Passband -0.01dB 0.980≤FSO/FSI≤6.000 PB 0 0.4583FSI kHz 0.900≤FSO/FSI<0.990 PB 0 0.4167FSI kHz 0.533≤FSO/FSI<0.909 PB 0 0.2182FSI kHz 0.490≤FSO/FSI<0.539 PB 0 0.2177FSI kHz 0.450≤FSO/FSI<0.495 PB 0 0.1948FSI kHz 0.225≤FSO/FSI<0.455 PB 0 0.1312FSI kHz Passband -0.50dB 0.167≤FSO/FSI<0.227 PB 0 0.0658FSI kHz Stopband 0.980≤FSO/FSI≤6.000 SB 0.5417FSI kHz 0.900≤FSO/FSI<0.990 SB 0.5021FSI kHz 0.533≤FSO/FSI<0.909 SB 0.2974FSI kHz 0.490≤FSO/FSI<0.539 SB 0.2812FSI kHz 0.450≤FSO/FSI<0.495 SB 0.2604FSI kHz 0.225≤FSO/FSI<0.455 SB 0.1802FSI kHz 0.167≤FSO/FSI<0.227 SB 0.0970FSI kHz Passband Ripple 0.225≤FSO/FSI≤6.000 PR ±0.01 dB 0.167≤FSO/FSI<0.227 PR ±0.50 dB Stopband Attenuation 0.450≤FSO/FSI≤6.000 SA 95.2 dB 0.167≤FSO/FSI<0.455 SA 90.0 dB Group Delay (Tsi=1/fsi,Tso=1/fso) (67H Note 12) GD 54Tsi + 9Tso Tsi,Tso Note 12. This delay is the a period from the rising edge of LRCLKI3, just after the data is input, to the rising edge of LRCLKO, just before the data is output, when there is no phase difference between Input and Output signals. ■ FSCONV Block (Ta= -40°C to 85°C, VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V) Parameter Symbol min typ max Unit Passband -0.01dB 0.167≤FSO/FSI≤0.363 PB 0 0.1814FSI kHz Stopband 0.167≤FSO/FSI≤0.363 SB 0.8185FSI kHz Passband Ripple 0.167≤FSO/FSI≤0.363 PR ±0.005 dB Stopband Attenuation 0.167≤FSO/FSI≤0.363 SA 94.0 dB Group Delay (Tsi=1/fsi,Tso=1/fso) (68H Note 13) GD 8Tsi + 1Tso Tsi,Tso 69H Note 6. Input signal frequency bandwidth of FSCONV must be attenuated more than 4kHz when the output sampling rate is 8kHz, or must be attenuated more than 8kHz when the output sampling rate is 16kHz. Note 13. This delay is the a period from the rising edge of LRCLKI2, just after the data is input, to the rising edge of LRCLKO, just before the data is output, when there is no phase difference between Input and Output signals.
[AK7736B] MS1562-E-00-PB 2013/10 - 12 - 10. Switching Characteristics ■ System Clock (Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V; CL=20pF) Parameter Symbol min typ max a) with a Crystal Oscillator CKM[2:0]bits=0h fXTI 11.2896 12.288 MHz CKM[2:0]bits=1h fXTI 16.9344 18.432 MHz b) with an External Clock Duty Cycle 40 50 60 % CKM[2:0]bits=0h,2h fXTI 11.0 11.2896 12.288
12.4 MHz
CKM[2:0]bits=1h fXTI 16.5 16.9344 18.432
18.6 MHz
LRCLK1 Frequency (70H Note 14) fs 8 96 kHz BITCLK1 Frequency (71H Note 15) 32,48,64 fs High Level Width Low Level Width tBCLKH tBCLKL ns ns Frequency fBCLK 0.23 3.072 6.2 MHz LRCLKI2 Frequency (FSCONV) (72H Note 16) fs 44.1 48 kHz BITCLKI2 Frequency (FSCONV) (73H Note 17) 32,48,64,12 fs High Level Width Low Level Width tBCLKH tBCLKL ns ns Frequency fBCLK 1.25 3.072 6.2 MHz LRCLKI3 Frequency (SRC) fs 8 96 kHz BITCLKI3 Frequency (SRC) 32,48,64,12 fs High Level Width Low Level Width tBCLKH tBCLKL ns ns Frequency fBCLK 0.23 3.072 12.4 MHz Note 14. LRCLK1 frequency and sampling rate (fs) should be the same. Note 15. When BITCLK1 is used as a master clock reference clock, it should be synchronized with LRCLK1, and its frequency should be fixed. Note 16. fs=8~48kHz in CKM mode 4. Note 17. 128fs is inhibited in CKM mode 4. ■ Power Down (Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V) Parameter Symbol min typ max Unit PDN (74H Note 18) tRST 600 ns Note 18. The PDN pin must be “L” when power up the AK7736B.
[AK7736B] MS1562-E-00-PB 2013/10 - 13 - ■ Serial Data Interface (Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V; CL=20pF) Parameter Symbol min typ max Unit DSP Section Input SDIN1, 2A, 2B, 2C, 3, 4 (75H Note 19) Delay Time from BITCLK1 “↑” to LRCLK1 (76H Note 20) tBLRD 20 ns Delay Time from LRCLK1 to BITCLK1 “↑” (77H Note 20) tLRBD 20 ns Serial Data Input Latch Setup Time tBSIDS 80 ns Serial Data Input Latch Hold Time tBSIDH 80 ns SRC Section Input SDIN3 Delay Time from BITCLKI3 “↑” to LRCLKI3 (78H Note 21) tBLRD 20 ns Delay Time from LRCLKI3 to BITCLKI3 “↑” (79H Note 21) tLRBD 20 ns Serial Data Input Latch Setup Time tBSIDS 40 ns Serial Data Input Latch Hold Time tBSIDH 40 ns FSCONV Section Input SDIN4 (80 H Note 22) Delay Time from BITCLKI2 “↑” to LRCLKI2 (81H Note 23) tBLRD 20 ns Delay Time from LRCLKI2 to BITCLKI2 “↑” (82H Note 23) tLRBD 20 ns Serial Data Input Latch Setup Time tBSIDS 40 ns Serial Data Input Latch Hold Time tBSIDH 40 ns Output SDOUT1, SDOUT2, SDOUT3, SDOUT4 BITCLKO Frequency (83H Note 24) fBCLK 64 fs BITCLKO Duty Factor (84H Note 24) 50 % Delay Time from BITCLKO “↓” to LRCLKO (85H Note 25) tMBL -20 40 ns Delay Time from LRCLK1 to Serial Data Output (86H Note 26) tLRD 80 ns Delay Time from BITCLK1“↓” to Serial Data Output (87H Note 27) tBSOD 80 ns Delay Time from LRCLKO to Serial Data Output (88H Note 26) tLRD 80 Delay Time from BITCLKO “↓” to Serial Data Output (89H Note 28) tBSOD 80 SDINn → SDOUTn (n=1, 2A, 2B, 2C, 3, 4) Delay Time from SDINn to SDOUTn Output tIOD 60 ns Note 19. In CKM mode 4, these are the time from LRCKLI2 or BITCLKI2. Note 20. When BITCLK1 polarity is inverted, delay time is from BITCLK1 “↓”. Note 21. When BITCLKI3 polarity is inverted, delay time is from BITCLKI3 “↓”. Note 22. Except CKM mode 4. Note 23. When BITCLKI2 polarity is inverted, delay time is from BITCLKI2 “↓”. Note 24. Except slave mode. Note 25. When BCKOP bit = “1”, delay time is from BITCLKO “↑”. Note 26. Except I2S compatible mode. Note 27. When BITCLK1 polarity is inverted, delay time is from BITCLK1 “↑”. Note 28. When BITCLKO polarity is inverted, delay time is from BITCLKO “↑”.
[AK7736B] MS1562-E-00-PB 2013/10 - 14 - ■ Microprocessor Interface (Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS=0V; CL=20pF) Parameter Symbol min typ max Unit Microprocessor Interface Signal SCLK Frequency fSCLK 2.1 MHz SCLK Low Level Width tSCLKL 200 ns SCLK High Level Width tSCLKH 200 ns Microprocessor → AK7736B CSN High Level Width tWRQH 500 ns From CSN “↑” to PDN “↑” tRST 600 ns From PDN “↑” to CSN “↓” tIRRQ 1 ms From CSN “↓” to SCLK “↓” tWSC 500 ns From SCLK “↑” to CSN “↑” tSCW 800 ns SI Latch Setup Time tSIS 200 ns SI Latch Hold Time tSIH 200 ns AK7736B → Microprocessor Delay Time from SCLK “↓” to SO Output tSOS 200 ns Hold Time from SCLK “↑” to SO Output (90H Note 29) tSOH 200 ns Note 29. Except when input the eighth bit of the command code. ■ I2C-BUS Interface (Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS=0V; CL=20pF) Parameter Symbol min typ max Unit I2C Timing SCL clock frequency fSCL 400 kHz Bus Free Time Between Transmissions tBUF 1.3 s Start Condition Hold Time (prior to first Clock pulse) tHD:STA 0.6 s Clock Low Time tLOW 1.3 s Clock High Time tHIGH 0.6 s Setup Time for Repeated Start Condition tSU:STA 0.6 s SDA Hold Time from SCL Falling tHD:DAT 0 0.9 s SDA Setup Time from SCL Rising tSU:DAT 0.1 s Rise Time of Both SDA and SCL Lines tR 0.3 s Fall Time of Both SDA and SCL Lines tF 0.3 s Setup Time for Stop Condition tSU:STO 0.6 s Pulse Width of Spike Noise Suppressed By Input Filter tSP 0 50 ns Capacitive load on bus Cb 400 pF
[AK7736B] MS1562-E-00-PB 2013/10 - 20 - 11. Package ■ Outline Dimensions 48pin LQFP (Unit mm) (ASECL: LQFP48-7x7-0.50 PP-C-06-B268) ■ Materials and Lead Specification Package: Epoxy Lead frame: Copper Lead-finish: Soldering (Pb free) plate
[AK7736B] MS1562-E-00-PB 2013/10 - 21 - ■ Marking AK7736BVQ ￥0VT XXXXXXX AKM 1) pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK7736BVQ 4) Asahi Kasei Logo
Revision History
Date (Y/M/D) Revision Reason Page Contents 13/10/03 00 First Edition
[AK7736B] MS1562-E-00-PB 2013/10 - 22 - IMPORTANT NOTICE 0. Asahi Kas ei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ( “Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products . AKM neither makes warranties or repres entations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, tr affic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance -related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or rel ated technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The P roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. Thank you for your access to AKM product information. More detail product information is available, please contact our sales office or authorized distributors.