AK7600

AK7600 AKM | Alldatasheet

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[AK7600] MS0999-E-00 2008/09 - 1 - GENERAL DESCRIPTION AK7600 is a CODEC (2ch ADC, 6ch DAC) with a delay line memory and digital filters such as EQ. This device operates in master mode and the internal sampling rate is 44.1kHz. It supports 5.0V single input and the integrated regulator generates the internal voltage. The 2-channeled ADC achieves dynamic rage of 97dB single end inputs, and 6-channeled DAC achieves 102dB single end outputs. The delay line memory covers 36ms in total. Time alignment of 6m or less is possible since the delay line memory can store for 18ms data for both left and right channels. A car audio system can be built easily 5-bands EQ and time alignment functions.

FEATURES

1. 2ch 24bit ADC - 64times Over Sampling - Linear Phase Digital Anti-Alias Filter - Single-ended input - S/(N+D): 90dB - DR, S/N: 97dB - Digital HPF for AC coupling 2. 6ch 24bit DAC - 128times Over Sampling - 8times 24bit Digital filter - Single-ended output - S/(N+D): 90dB - DR, S/N: 102dB 3. Digital Processing - 5Band EQ×2ch (Second-order IIR-filter setting is also available) - Delay line memory control Maximum delay time: Max 36ms / Lch 18ms, Rch 18ms (1input and 3outputs for each channel) Adjustable output time (1/fs step) - X’Over filter: 2step 2nd-order IIR Filter for Each channel of Delay line memory Spectrum analyzer: 7Band 68Hz, 160Hz, 400Hz, 1kHz, 2.5kHz, 6.3kHz,16kHz - Soft Mute - Zero Detect Function 4. Master Clock - Master Mode: 256fs 5. μP Interface: I 2C Bus (Ver 1.0, 400kHz mode) 6. Power Supply - Analog: AVDD = 4.5 ∼ 5.5V - Digital: DVDD = 4.5 ∼ 5.5V 7. Power Consumption: 52mA (fs=44.1kHz) 9. Package: 30VSOP(0.65mm pitch) 2/6-Channel Audio CODEC with Digital EQ AK7600

Figure 1. Block Diagram

Figure 2. Pin Layout

1 TSTI

9 VREFH

[AK7600] MS0999-E-00 2008/09 - 4 - PIN FUNCTION No. Pin Name I/O Function

1 TSTI I Test Pin

This pin should be connected to VSS1. 2 REF18 O Internal regulator 1.8V Output pin

3 VSS4 - Ground Pin, 0V

4 VCOM O VCOM pin

5 AINL I ADC Input pin Lch.

6 AINR I ADC Input pin Rch

7 AVDD - Analog Power Supply Pin 4.5~5.5V

8 VSS1 - Ground Pin, 0V

9 VREFH - Positive Voltage Reference Input Pin, AVDD

10 AOUT1L O DAC1 Lch Output pin.

11 AOUT1R O DAC1 Rch Output pin

12 AOUT2L O DAC2 Lch Output pin

13 AOUT2R O DAC2 Rch Output pin

14 AOUT3L O DAC3 Lch Output pin

15 AOUT3R O DAC3 Rch Output pin

16 DZF O Zero detect pin

17 PDN I

Power-Down & Reset Pin When “L”, the AK7600 is powered-down and the control registers are reset to default state.

18 VSS3 - Ground Pin 0V

19 SDA I/O Control Data Input Pin : SDA (I 2C Bus) (Note 2)

20 SCL I Control Data Clock Pin : SCL (I 2C Bus)

21 CLKO O Master Clock Output Pin

22 DVDD - Digital Power Supply 1 Pin, 4.5~5.5V

23 BICK O Output Audio Serial Data Clock Pin

24 LRCK O Output Channel Clock Pin

25 SDTO1 O Audio Serial Data Output 1 Pin

26 SDTO2 O Audio Serial Data Output 2 Pin

27 SDTO3 O Audio Serial Data Output 3 Pin

28 XTI I X’tal Input Pin

29 XTO O X’tal Output Pin

30 VSS2 - Ground Pin, 0V

Note 1. All digital input pins are never to be left float. Note 2. Input mode when powered-down. ■Handling of Unused Pin The unused I/O pins should be processed appropriately as below Classification Pin Name Setting Analog AOUT1L, AOUT1R, AOUT2L, AOUT2R, AOUT3L, AOUT3R, XTO These pins should be open. TSTI This pin should be connected to VSS1. Digital BICK, LRCK, CLKO, SDTO1, SDTO2, SDTO3 These pins should be open.

[AK7600] MS0999-E-00 2008/09 - 5 - ABSOLUTE MAXMUM RATING (VSS1=VSS2=VSS3=VSS4=0V; Note 3) Parameter Symbol min max Units Power Supplies Analog Digital AVDD DVDD -0.3 -0.3 6.0 6.0 V V Input Current (any pins except for supplies) IIN - ±10 mA Analog Input Voltage VINA -0.3 AVDD+0.3 V Digital Input Voltage VIND -0.3 DVDD+0.3 V Ambient Temperature (power applied) Ta -40 85 °C Storage Temperature Tstg -65 150 °C Note 3. All indicated voltages are with respect to ground VSS1, VSS2, VSS3 and VSS4 must be connected to the analog ground plane. Note 4. Analog input pins are AINL and AINR. Note 5. Digital input pins are TSTI, SDA, SCL and XTI. WARNING: Operating at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these critical conditions. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4 =0V; Note 3) Parameter Symbol min typ max Units Power Supplies (Note 6) Analog Digital AVDD DVDD 4.5 4.5 5.0 5.0 5.5 5.5 V V Note 6. AVDD and DVDD must be the same voltage. The power up sequence between AVDD and DVDD is not critical but the PDN pin must be “L” until all power supplies are ON, then put the PDN pin to “H”. All power supplies of the AK7600 are must be ON. Do not turn any power supply off (means the same voltage as ground or floating) independently. When using the AK7600 with I²C bus, the power supply of the AK7600 must not be turned off unless the power supplies of the surrounding device are turned off. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK7600] MS0999-E-00 2008/09 - 6 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD=5.0V, DVDD =5.0V; VSS1=VSS2=VSS3=VSS4=0V; VREFH=AVDD, fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 44.1kHz, ; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics (single inputs) Resolution 24 Bits -1dBFS 83 90 dB S/(N+D) fs=44.1kHz BW=20kHz -60dBFS 35 DR (-60dBFS with A-weighted) 90 97 dB S/N (A-weighted) 90 97 dB Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0 0.5 dB Gain Drift 20 - ppm/°C Input Voltage AIN=0.65xVREFH 3.09 3.25 3.41 Vpp Input Resistance 22 45 kΩ Power Supply Rejection (Note 7) 50 dB DAC Analog Output Characteristics (single outputs) Resolution 24 Bits -1dBFS 90 dB S/(N+D) fs=44.1kHz BW=20kHz -60dBFS 39 DR (-60dBFS with A-weighted) 102 dB S/N (A-weighted) 102 dB Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0 0.5 dB Gain Drift 20 - ppm/°C Output Voltage AOUT=0.65xVREFH 3.09 3.25 3.41 Vpp Load Resistance (AC load) 5 kΩ Load Capacitance 30 pF Power Supply Rejection (Note 7) 50 dB ADC to DAC Characteristics (single outputs) Resolution 24 Bits -1dBFS 80 87 dB S/(N+D) fs=44.1kHz BW=20kHz -60dBFS 34 DR (-60dBFS with A-weighted) 87 96 dB S/N (A-weighted) 87 96 dB Note 7. PSR is applied to AVDD and DVDD with 1kHz, 50mVpp. This is the value of convoluted sinusoidal voltage of 1kHz and 50mVpp when the VREFH pin is held +5V. Parameter min typ max Units Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) AVDD fs=44.1kHz DVDD fs=44.1kHz Power-down mode (PDN pin = “L”) AVDD+DVDD (Note 8) 300 450 mA mA µA Note 8. The AK7600 is not operating. This value is when all the digital input pins including clocks are held to VSS2.

[AK7600] MS0999-E-00 2008/09 - 7 - FILTER CHARACTERISTICS (Ta= -40 ∼ +85°C; AVDD=4.5∼ 5.5V, DVDD=4.5∼ 5.5V) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 9) ±0.1dB −0.2dB −3.0dB PB 18.3 21.1 17.3 kHz kHz kHz Stopband (Note 9) SB 25.7 - - kHz Passband Ripple PR - - ±0.04 dB Stopband Attenuation SA 68 - - dB Group Delay Distortion ΔGD - 0 - μs Group Delay (Note 10) GD - 16 - 1/fs ADC Digital Filter (HPF): Frequency Response (Note 9) −3dB −0.1dB FR 0.86 5.9 Hz Hz DAC Digital Filter (LPF): Passband (Note 9) ±0.06dB −6.0dB PB 22.05 20.0 kHz kHz Stopband (Note 9) SB 24.1 - - kHz Passband Ripple PR - - ±0.02 dB Stopband Attenuation SA 54 - - dB Group Delay Distortion ΔGD - 0 - μs Group Delay (Note 10) GD - 20 - 1/fs DAC Digital Filter + Analog Filter: Frequency Response (Note 11) 20~20kHz FR - ±0.1 - dB Note 9. The passband and stopband frequencies scale with fs (system sampling rate). For example, when fs= 44.1kHz, DAC is PB=0.45412*fs (@±0.06dB). Note 10. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC. This time is from the set of 24bit data to the input registers to the output of analog signal for DAC. Note 11. The reference frequency of these responses is 1kHz.

[AK7600] MS0999-E-00 2008/09 - 8 - DC CHARACTERISTICS (Ta=-40°C∼+85°C; AVDD= DVDD=4.5∼5.5V) Parameter Symbol Min typ max Units High-Level Input Voltage ( XTI, TSTI pins) Low-Level Input Voltage (XTI, TSTI pins) VIH VIL 70%DVDD 30%DVDD V V High-Level Input Voltage (PDN, SDA, SCL pins) Low-Level Input Voltage (PDN, SDA, SCL, pins) VIH VIL 2.0 0.8 V V High-Level Output Voltage (SDTO1, SDTO2 ,SDTO3, LRCK, BICK, SDA CLKO, DZF pins: Iout=-100µA) Low-Level Output Voltage (SDTO1, SDTO2, SDTO3, LRCK, BICK, CLKO, DZF pins: Iout= 100µA) (SDA pins: Iout= 3mA) VOH VOL VOL DVDD-0.5 0.5 0.4 V V V Input Leakage Current Iin - - ±10 µA

[AK7600] MS0999-E-00 2008/09 - 9 - SWITCHING CHARACTERISTICS (Ta=-40∼+85°C; AVDD=4.5~5.5V; DVDD=4.5∼5.5V; CL=20pF; unless otherwise specified) Parameter Symbol Min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL MHz MCKO Output Frequency Duty cycle fMCK dMCK MHz External Clock 256fsn: Pulse Width Low Pulse Width High fCLK tCLKL tCLKH MHz ns ns MCKO Output Frequency Duty cycle fMCK dMCK MHz Audio Interface Timing (Master mode) BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO fBCK dBCK tMBLR tBSD −20 −20 64fs Hz ns ns Note 12. “L” when using I2C format. Note 13. BICK rising edge must not occur at the same time as LRCK edge. Parameter Symbol min typ max Units Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling ( Note 14) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb 1.3 0.6 1.3 0.6 0.6 0.1 0.6 400 0.3 0.3 400 kHz μs μs μs μs μs μs μs μs μs μs ns pF Power-down & Reset Timing PDN Pulse Width (Note 15) tPD 150 ns Note 14. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 15. The AK7600 can be reset by bringing the PDN pin = “L”. Note 16. I2C is a registered trademark of Philips Semiconductors.

Figure 3. Clock Timing

[AK7600] MS0999-E-00 2008/09 - 14 - ■ Zero Detect Function The AK7600 has independent zeros detect function for each DAC, which is always enabled. DZDD1-3 bits of CONT1 can select detection channel group and this function covers 6-channel outputs. Counting on “AND” for zero detected flags of selected channels, when the input data is continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H” at DZLH bit (CONT1) is “0”, the DZF pin goes to “L” at DZLH bit (CONT1) is “1”. The DZF pin immediately returns to “L” (DZLH bit “0”) or “H” (DZLH bit “1”) if the input data is not zero after the zero detection. ■ Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit is set “1”, the output signal is attenuated to -∞ in 1024 LRCK cycles. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting this operation, the attenuation is discontinued and it is return ed to 0dB by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit Attenuation DZF DAC Full Level AOUT 8192/fs GD GD (1) (3) (4) (5) (2) Note: (1) The transition time to attenuate input data to -∞ is 1024 LRCK cycles (1024/fs). (2) The transition time to return to the full scale of the DAC input is 1024 LRCK cycles (1024/fs). (3) Analog output corresponding to digital input has group delay (GD). (4) If the soft mute is cancelled before attenuating - ∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (5) When the input data for both channels are continuously zero for 8192 LRCK cycles, the DZF pin goes to “H”. if the DZLH bit is “0” (the DZF pin goes to “L” if the DZLH bit is “1”). The DZF pin immediately returns to “L” if the input data are not zero after going to DZF “H” (DZLH bit =“0”). Figure 11 Soft Mute and Zero Detect Function

bit to “1” after an interval of 10ms. = “0”. Figure 12 shows the power on/off sequence example. (3) Regulator will be powered-up after the PDN pin goes to “H”. (4) The DAC and SDTO1-3 outputs corresponding to the ADC input has group delay (GD). (5) The SDTP1-3 outputs are “0” when the AK7600 is powered-down. (6) The DAC output is VSS voltage when the AK7600 is powered-down. (7) Click noise occurs at the falling edge of PDN. (9) In power down mode(PDN pin = “L”), the DZF pin = “L”. (10) The DZF pin output will reflects the DZLH bit setting when internal PDN is “H”. Figure 12. Power Up/Down Sequence Example

(1) Internal RSTN will be “L”, 4~5/fs after RSTN bit went to “0”. (2) ADC internal RSTN will be “H”, within 1/fs after RSTN bit = “1”. (3) The reset cycle is 8/fs after ADC internal RSTN goes to “H”. (4) Internal RSTN for IIR will be “H” after 7~8/fs from RSTN bit =“1”. (5) Internal RSTN for DAC will be “H” after 1.5~2.5/fs from RSTN bit = “1”. (6) The DAC and SDTO1-3 outputs corresponding to the ADC input has group delay (GD). (7) SDTO1-3 output is “0” data when the AK7600 is in powered down mode. (9) Click noise occurs at the edge of internal RSTN. (10) Analog output is VCOM voltage(AVDD/2) when RSTN bit = “0”. (12) The DZF pin reflects the setting of DZLH bit. This pin changes to “L” or “H” 9/fs after the RSTN bit is set to “0”. Figure 13. Reset Sequence Example

[AK7600] MS0999-E-00 2008/09 - 20 - ■ Command Code BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 8/16/32 flag Area to be accessed (1) 8/16/32 flag When BIT[7:6] bits are “00”, the following data will be 8bit. The data will be 16bit 10byte of 1word x 5 transfer when “01”, and 32bit 20byte of 1word x 5 transfer when “10”. (2) Accompanying data to the access area BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Command and Content 0 0 0 0 0 1 01H Control Register Cont0 Setting 0 0 0 0 1 0 02H Control Register Cont1 Setting 0 0 0 0 1 1 03H Control Register Cont2 Setting 0 0 0 0 0 0 40H Function2, Lch Coefficient Setting Preparation 0 0 0 0 0 1 41H Function2, Rch Coefficient Setting Preparation 0 0 0 0 1 0 42H Function2 Filter1 Coefficient Setting Preparation 0 0 0 0 1 1 43H Function2 Filter2 Coefficient Setting Preparation 0 0 0 1 0 0 44H Pre EQ ATT Coefficient Setting Preparation 0 0 0 1 0 1 45H EQ3 Filter Coefficient Setting Preparation 0 0 0 1 1 0 46H EQ4 Filter Coefficient Setting Preparation 0 0 0 1 1 1 47H X’Over ATT Coefficient Setting Preparation 0 0 1 0 0 0 48H X’Over Gain Coefficient Setting Preparation 0 0 1 0 0 1 49H Delay data Lch Setting Preparation 0 0 1 0 1 0 4AH Delay data Rch Setting Preparation 0 0 0 0 0 1 81H EQ0 Filter Coefficient Setting Preparation 0 0 0 0 1 0 82H EQ1 Filter Coefficient Setting Preparation 0 0 0 0 1 1 83H EQ2 Filter Coefficient Setting Preparation 0 0 0 1 0 0 84H X’Over HPF1-1 Coefficient Setting Preparation 0 0 0 1 0 1 85H X’Over HPF1-2 Coefficient Setting Preparation 0 0 0 1 1 0 86H X’Over HPF2-1 Coefficient Setting Preparation 0 0 0 1 1 1 87H X’Over HPF2-2 Coefficient Setting Preparation 0 0 1 0 0 0 88H X’Over LPF-1 Coefficient Setting Preparation 0 0 1 0 0 1 89H X’Over LPF-2 Coefficient Setting Preparation 0 0 0 0 0 1 C1H Read SpeAna 1Band (60Hz) 0 0 0 0 1 0 C2H Read SpeAna 2Band (160Hz) 0 0 0 0 1 1 C3H Read SpeAna 3Band (400Hz) 0 0 0 1 0 0 C4H Read SpeAna 3Band (1kHz) 0 0 0 1 0 1 C5H Read SpeAna 3Band (2.5kHz) 0 0 0 1 1 0 C6H Read SpeAna 3Band (6.3kHz) 0 0 0 1 1 1 C7H Read SpeAna 3Band (16kHz)

Figure 20. Write Sequence Table 3. List of Usable Command Codes in Write Sequence

[AK7600] MS0999-E-00 2008/09 - 22 - ■ Data Format Data Write (1)Control Register Write SDA (1) COMMAND 01H, 02H, 03H (2) DATA D7~D0 Relationship between COMMAND and control register data. 1) Command 01H is write command for CONT0. 2) Command 02H is write command for CONT1. 3) Command 03H is write command for CONT2. (2)16bit Coefficient or Delay Data Write SDA (1) COMMAND 40H,41H,42H,43H,44H,45H,46H,47H,48H,49H,4AH (2) DATA1-1 D15~D8 (3) DATA1-2 D7~D0 (4) DATA2-1 D15~D8 (5) DATA2-2 D7~D0 (6)~(11) (Continues in 2byte unit to DATA5. In total 10byte DATA) (3)28bit Coefficient Data Write SDA (1) COMMAND 80H,81H,82H,83H,84H,85H,86H,87H,88H,89H (2) DATA1-1 0 0 0 0 D27~D24 (3) DATA1-2 D23~D16 (4) DATA1-3 D15~D8 (5) DATA1-4 D7~D0 (6)~(21) (Continues in 4byte unit to DATA5. In total 20byte DATA)

data regarding to command code. and since it did not release the BUS, the stop condition cannot be properly received. Figure 21. Read Sequence Table 4. List of Usable Read Command Codes in Read Sequence

[AK7600] MS0999-E-00 2008/09 - 24 - Data Read (1)Control Register Read SDA (1) COMMAND 01H,02H,03H (2) DATA D7~D0 Relationship between COMMAND and control register data. 4) Command 01H is read command for CONT0. 5) Command 02H is read command for CONT1. 6) Command 03H is read command for CONT2. (2)16bit Coefficient or Delay Time Read SDA (1) COMMAND 40H,41H,42H,43H,44H,45H,46H,47H,48H,49H,4AH(Input) (2) DATA1-1 D15~D8 (Output) (3) DATA1-2 D7~D0 (4) DATA2-1 D15~D8 (5) DATA2-2 D7~D0 (6)~(11) (Continues in 2byte unit to DATA5. In total 10byte DATA) (3)28bit Coefficient Data Read SDA (1) COMMAND 80H,81H,82H,83H,84H,85H,86H,87H,88H,89H (Input ) (2) DATA1-1 0 0 0 0 D27~D24 ( Output ) (3) DATA1-2 D23~D16 (4) DATA1-3 D15~D8 (5) DATA1-4 D7~D0 (6)~(21) (Continues in 4byte unit to DATA5. In total 20byte DATA) (4) Spectrum Analyzer Data Read SDA (1) COMMAND C1H, C2H, C3H, C4H, C5H, C6H, C7H (Input) (2) DATA2 D15 D14 D13 D12 D11 D10 D9 D8 (Output) (3) DATA1 D7 D6 D5 D4 D3 D2 D1 D0

[AK7600] MS0999-E-00 2008/09 - 25 - ■ Register Definitions Register Name: CONT0 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND (01H) 0 0 0 0 0 0 0 1 Setting bit (1byte) 0 0 0 0 0 PMADC PMDAC RSTN R/W RD RD RD RD RD R/W R/W R/W Default 0 0 0 0 0 1 1 0 RSTN: Internal timing reset 0: Reset (The DZF pin goes to “H” but Register values are not initialized.) 1 : N o r m a l O p e r a t i o n PMDAC: DAC1-3 power management 0: Power Down (All DAC’s) 1 : N o r m a l O p e r a t i o n PMADC: ADC power management 0 : P o w e r D o w n 1 : N o r m a l O p e r a t i o n

[AK7600] MS0999-E-00 2008/09 - 26 - Register Name: CONT1 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND (02H) 0 0 0 0 0 0 1 0 Setting bit (1byte) DZD3 DZD2 DZD1 DZLH DIF 0 0 SMUTE R/W R/W R/W R/W R/W R/W RD RD R/W Default 0 0 0 0 1 0 0 0 Note) Writing to RD bits is ignored. DZD3: DZF setting 0: Indicate Zero detect of DAC3 at DZF 1: Ignore Zero detect DZD2: DZF setting 0: Indicate Zero detect of DAC2 at DZF 1: Ignore Zero detect DZD1: DZF setting 0: Indicate Zero detect of DAC1 at DZF 1: Ignore Zero detect DZLH: DZF setting 0: Output “H” as a result of DZF zero detection 1: Output “L” as a result of DZF zero detection D7 D6 D5 D4 DAC3 DAC2 DAC1 DZF pin output Level 0 0 0 0 Zero Zero Zero H 0 0 1 0 Zero Zero - H 0 1 0 0 Zero - Zero H 0 1 1 0 Zero - - H 1 0 0 0 - Zero Zero H 1 0 1 0 - Zero - H 1 1 0 0 - - Zero H 1 1 1 0 - - - H 0 0 0 1 Zero Zero Zero L 0 0 1 1 Zero Zero - L 0 1 0 1 Zero - Zero L 0 1 1 1 Zero - - L 1 0 0 1 - Zero Zero L 1 0 1 1 - Zero - L 1 1 0 1 - - Zero L 1 1 1 1 - - - L SMUTE: Soft Mute enable 0 : N o r m a l O p e r a t i o n 1: Soft Mute execute for all DAC’s DIF: Digital output format (DIF mode setting) 0: Left justified mode 1 : I 2 S m o d e ( d e f a u l t )

[AK7600] MS0999-E-00 2008/09 - 27 - Register Name: CONT2 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND (03H) 0 0 0 0 0 0 1 1 Setting bit (1byte) LRCK BICK MCKO Reserved DO3 DO2 DO1 0 R/W R/W R/W R/W R/W R/W R/W R/W RD Default 0 0 0 0 0 0 0 0 LRCK: LRCK output enable 0: LRCK pin outputs “L” 1: Output LRCK(1fs) to the LRCK pin BICK: BIT clock output enable 0: BICK pin outputs “L” 1: Output BIT clock (64fs) to the BICK pin MCKO: Master clock output enable 0: CLKO pin outputs “L” 1: Output master clock (256fs) to the CLKO pin Reserved: Write “0” into this bit. DO3: SDTO3 output enable 0: SDTO3 pin outputs “L” 1: Output audio data to the SDTO3 pin DO2: SDTO2 output enable 0: SDTO2 pin outputs “L” 1: Output audio data to the SDTO2 pin DO1: SDTO1 output enable 0: SDTO1 pin outputs “L” 1: Output audio data to the SDTO1 pin

[AK7600] MS0999-E-00 2008/09 - 28 - ■ Blocks and Circuits Construction of Command Setting ADC Function SpeAna ATT EQ0 EQ1 EQ2 EQ3 EQ4 Delay Control F-ATT R-ATT N-ATT HPF1-1 HPF2-1 LPF1 HPF1-2 HPF2-2 LPF2 F-Gain R-Gain N-Gain Mute Mute Mute DAC1 DAC2 DAC3

[AK7600] MS0999-E-00 2008/09 - 29 - Command 40H Shift Setting R/W Default Value Data 1 (2byte) LI1 Coefficient 1bit left x2 R/W 0x2000 Data 2 (2byte) RI1 Coefficient 1bit left x2 R/W 0x2000 Data 3 (2byte) LT Coefficient 1bit left x2 R/W 0x4000 Data 4 (2byte) LO1 Coefficient 1bit left x2 R/W 0x0000 Data 5 (2byte) LO2 Coefficient 1bit left x2 R/W 0x0000 Command 41H Shift Setting R/W Default Value Data 1 (2byte) LI2 Coefficient 1bit left x2 R/W 0x2000 Data 2 (2byte) RI2 Coefficient 1bit left x2 R/W 0x2000 Data 3 (2byte) RT Coefficient 1bit left x2 R/W 0x4000 Data 4 (2byte) RO1 Coefficient 1bit left x2 R/W 0x0000 Data 5 (2byte) RO2 Coefficient 1bit left x2 R/W 0x0000 Command 42H Shift Setting R/W Default Value Data 1 (2byte) A12 Coefficient 1bit left x2 R/W 0x0000 Data 2 (2byte) A11 Coefficient 1bit left x2 R/W 0x0000 Data 3 (2byte) A10 Coefficient 1bit left x2 R/W 0x4000 Data 4 (2byte) B12 Coefficient 1bit left x2 R/W 0x0000 Data 5 (2byte) B11 Coefficient 1bit left x2 R/W 0x0000 Command 43H Shift Setting R/W Default Value Data 1 (2byte) A22 Coefficient 1bit left x2 R/W 0x0000 Data 2 (2byte) A21 Coefficient 1bit left x2 R/W 0x0000 Data 3 (2byte) A20 Coefficient 1bit left x2 R/W 0x4000 Data 4 (2byte) B22 Coefficient 1bit left x2 R/W 0x0000 Data 5 (2byte) B21 Coefficient 1bit left x2 R/W 0x0000 Note: All data are R/W. Z-n Z-1 Z-1 Z-1Z-1 Z-1 Z-1 Z-1Z-1 Z-n LT a10 LI1 RI1 LI2 RI2 a11 a12 a20 a21 a22 b11 b12 b21 b22 RT LO1 RO1 LO2 RO2 Function All 16bit 1bit Left

[AK7600] MS0999-E-00 2008/09 - 30 - ATT Attenuate input data for both Left and Right channels. Command 44H Shift Setting R/W Default Value Data 1 (2byte) Pre EQ ATT setting coefficient 1bit left x2 R/W 0x4000 Data 2 (2byte) Dummy 1bit left x2 R/W 0x0000 Data 3 (2byte) Dummy 1bit left x2 R/W 0x0000 Data 4 (2byte) Dummy 1bit left x2 R/W 0x0000 Data 5 (2byte) Dummy 1bit left x2 R/W 0x0000 Note: All data are R/W. EQ Setting Command 81H Shift Setting R/W Default Value Data 1 (4byte) EQ0 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) EQ0 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) EQ0 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) EQ0 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) EQ0 B1 Coefficient 1bit left x 2 R/W 0x00000000 Command 82H Shift Setting R/W Default Value Data 1 (4byte) EQ1 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) EQ1 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) EQ1 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) EQ1 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) EQ1 B1 Coefficient 1bit left x 2 R/W 0x00000000 Command 83H Shift Setting R/W Default Value Data 1 (4byte) EQ2 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) EQ2 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) EQ2 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) EQ2 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) EQ2 B1 Coefficient 1bit left x 2 R/W 0x00000000 Note: All data are R/W. << 1 << 1 EQ1 EQ2 EQ3 EQ4 Z EQ0 Lch Rch Z Z Z Z Z Z Z Z Z Z Z

[AK7600] MS0999-E-00 2008/09 - 31 - Command 45H Shift Setting R/W Default Value Data 1 (2byte) EQ3 A2 Coefficient 1bit left x2 R/W 0x0000 Data 2 (2byte) EQ3 A1 Coefficient 1bit left x2 R/W 0x0000 Data 3 (2byte) EQ3 A0 Coefficient 1bit left x2 R/W 0x4000 Data 4 (2byte) EQ3 B2 Coefficient 1bit left x2 R/W 0x0000 Data 5 (2byte) EQ3 B1 Coefficient 1bit left x2 R/W 0x0000 Command 46H Shift Setting R/W Default Value Data 1 (2byte) EQ4 A2 Coefficient 1bit left x2 R/W 0x0000 Data 2 (2byte) EQ4 A1 Coefficient 1bit left x2 R/W 0x0000 Data 3 (2byte) EQ4 A0 Coefficient 2bit left x4 R/W 0x2000 Data 4 (2byte) EQ4 B2 Coefficient 1bit left x2 R/W 0x0000 Data 5 (2byte) EQ4 B1 Coefficient 1bit left x2 R/W 0x0000 Note: All data are R/W. F-ATT, R-ATT, N-ATT Amplify or regulate each Front (L1, R1), Rear (L2, R2) and SW (L3, R3) X’Over filter input data. Command 47H Shift Setting R/W Default Value Data 1 (2byte) Front ATT setting coefficient 1bit left x2 R/W 0x4000 Data 2 (2byte) Rear ATT setting coefficient 1bit left x2 R/W 0x4000 Data 3 (2byte) SW(NF) ATT setting coefficient 1bit left x2 R/W 0x4000 Data 4 (2byte) Dummy 1bit left x2 R/W 0x0000 Data 5 (2byte) Dummy 1bit left x2 R/W 0x0000 Note: All data are R/W. X’Over filter (HPF & LPF) Command 84H Shift Setting R/W Default Value Data 1 (4byte) HPF1-1 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) HPF1-1 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) HPF1-1 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) HPF1-1 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) HPF1-1 B1 Coefficient 1bit left x 2 R/W 0x00000000 Note: All data are R/W. << 1 << 1 Z First step Second step Z Z Z Z Z HPF1-1 HPF2-1 LPF-1 HPF1-2 HPF2-2 LPF-2

[AK7600] MS0999-E-00 2008/09 - 32 - Command 85H Shift Setting R/W Default Value Data 1 (4byte) HPF1-2 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) HPF1-2 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) HPF1-2 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) HPF1-2 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) HPF1-2 B1 Coefficient 1bit left x 2 R/W 0x00000000 Command 86H Shift Setting R/W Default Value Data 1 (4byte) HPF2-1 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) HPF2-1 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) HPF2-1 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) HPF2-1 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) HPF2-1 B1 Coefficient 1bit left x 2 R/W 0x00000000 Command 87H Shift Setting R/W Default Value Data 1 (4byte) HPF2-2 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) HPF2-2 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) HPF2-2 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) HPF2-2 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) HPF2-2 B1 Coefficient 1bit left x 2 R/W 0x00000000 Command 88H Shift Setting R/W Default Value Data 1 (4byte) LPF-1 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) LPF-1 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) LPF-1 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) LPF-1 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) LPF-1 B1 Coefficient 1bit left x 2 R/W 0x00000000 Command 89H Shift Setting R/W Default Value Data 1 (4byte) LPF-2 A2 Coefficient 1bit left x 2 R/W 0x00000000 Data 2 (4byte) LPF-2 A1 Coefficient 1bit left x 2 R/W 0x00000000 Data 3 (4byte) LPF-2 A0 Coefficient 1bit left x 2 R/W 0x04000000 Data 4 (4byte) LPF-2 B2 Coefficient 1bit left x 2 R/W 0x00000000 Data 5 (4byte) LPF-2 B1 Coefficient 1bit left x 2 R/W 0x00000000 Note: All data are R/W. F-Gain, R-Gain, N-Gain Amplify or regulate each Front (L1, R1), Rear (L2, R2) and SW (L3, R3) X’Over filter output data. Command 48H Shift Setting R/W Default Value Data 1 (2byte) Front Gain setting coefficient 1bit left x 2 R/W 0x4000 Data 2 (2byte) Rear Gain setting coefficient 1bit left x 2 R/W 0x4000 Data 3 (2byte) SW(NF) Gain setting coefficient 1bit left x 2 R/W 0x4000 Data 4 (2byte) Dummy 1bit left x 2 R/W 0x0000 Data 5 (2byte) Dummy 1bit left x 2 R/W 0x0000 << 1 << 1

[AK7600] MS0999-E-00 2008/09 - 33 - ■ Delay Time Setting (fs step) 1. D1 or D2 delay time setting of Function2 2. Delay time setting of each FL, FR, RR, RL, NL and NR channel (1/fs = 1/44100 = approximately 0.0226ms)= one unit. Command 49H Setting Unit R/W Default Value Data 1 (2byte) Function2 D1 delay time Set range (0x0000~0x002D) Delay time: 1/fs unit R/W 0x0000 Data 2 (2byte) Front L1 out delay time Set range (0x0000~0x031A) Delay time: 1/fs unit R/W 0x0000 Data 3 (2byte) Rear L2 out delay time Set range (0x0000~0x031A) Delay time: 1/fs unit R/W 0x0000 Data 4 (2byte) SW L3 out delay time Set range (0x0000~0x031A) Delay time: 1/fs unit R/W 0x0000 Data 5 (2byte) Dummy - R/W 0x0000 Command 4AH Setting Unit R/W Default Value Data 1 (2byte) Function2 D2 delay time Set range (0x0000~0x002D) Delay time: 1/fs unit R/W 0x0000 Data 2 (2byte) Front R1 out delay time Set range (0x0000~0x031A) Delay time: 1/fs unit R/W 0x0000 Data 3 (2byte) Rear R2 out delay time Set range (0x0000~0x031A) Delay time: 1/fs unit R/W 0x0000 Data 4 (2byte) SW R3 out delay time Set range (0x0000~0x031A) Delay time: 1/fs unit R/W 0x0000 Data 5 (2byte) Dummy - R/W 0x0000 Note: All data are R/W. When the delay time is set over its limit, it will be set to the maximum value. Delay Memory 1word=24bit 18ms Delay = 794word (44.1kHz x 0.018) Lch input FL RL NL L1 out (Front) L2 out (Rear) L3 out (SW) Delay Memory 1word=24bit 18ms Delay = 794word (44.1kHz x 0.018) Rch input FR RR NL R1 out (Front) R2 out (Rear) R3 out (SW)

[AK7600] MS0999-E-00 2008/09 - 34 - Spectrum Analyzer Each data level read of Spectrum Analyzer Command C1H R/W Data1 (2byte) 68Hz Level RD Command C1H R/W Data1 (2byte) 160Hz Level RD Command C1H R/W Data1 (2byte) 400Hz Level RD Command C1H R/W Data1 (2byte) 1kHz Level RD Command C1H R/W Data1 (2byte) 2.5kHz Level RD Command C1H R/W Data1 (2byte) 6.3kHz Level RD Command C1H R/W Data1 (2byte) 16kHz Level RD Measuring Frequency of Spectrum Analyzer There are 7 bands of the detection frequency of spectrum analyzer level at Fs=44.1kHz. Band 1 2 3 4 5 6 7 f0[Hz] 68 160 400 1000 2500 6300 16000

as suggestions for peripheral circuitry. Figure 22. Typical Connection Diagram Note: Do not take load current from the REF18 pin.

7 AVDD

[AK7600] MS0999-E-00 2008/09 - 36 - 1. Grounding and Power Supply Decoupling The AK7600 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, the power-up sequence is not critical. VSS1, VSS2, VSS3 and VSS4 of the AK7600 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK7600 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The input voltage to the VREFH pin sets the analog output range. Usually the VREFH pin is connected to AVDD and a 0.1μF ceramic capacitor is connected between AVDD and VSS1. VCOM is a signal ground of this chip (AVDD/2). The electrolytic capacitor around 2.2µF attached between VCOM anVSS1 eliminates the effects of high frequency noise. The ceramic capacitor in particular should be connected as close as possible to the pin. No load current may be taken from the VCOM pin. All signals, especially clock, should be kept away from VREFH and VCOM in order to avoid unwanted coupling into the AK7600. 3. Analog Inputs The ADC inputs is single-ended and biased to VCOM voltage (AVDD/2) internally by 45kΩ(typ). The inputs signal range scales with nominally at 0.65 x VREFH Vpp (typ)@fs=44.1kHz. The AK7600 can accept input voltage from VSS1 to AVDD. The output code format is 2's complement. Input DC offset is canceled by an integrated high-pass filter. The AK7600 samples the analog input at 64fs(@fs=44.1kHz). A digital filter removes the noise over the stopband attenuation level, except for a band of integral multiplication of 64fs. AK7600 has an integrated anti-alias RC filter in order to reduce the noise at 64fs. 4. Analog output The DAC output is single-ended and output range is 0.65xVREFH Vpp (typ) centered on VCOM. The bias voltage of the external summing circuit is supplied externally. The input data format is two’s compliment. Positive full-scale output corresponds to 7FFFFFH (@24bit) input code, Negative full scale is 800000H (@24bit) and VCOM voltage ideally is 000000H (@24bit). The Out-of-Band noise (shaping noise) generated by the internal delta-sigma modulator is attenuated by an integrated switched capacitor filter (SCF) and a continuous time filter (CTF). DC offsets on analog outputs are eliminated by AC coupling since analog outputs has DC offset of VCOM.

[AK7600] MS0999-E-00 2008/09 - 37 - PACKAGE Detail A NOTE: Dimension "*" does not include mold flash. 0.22 ±0.1 0.65 *9.7 ±0.1 1.5MAX A 1 15 1630 30pin VSOP (Unit: mm) 5.6±0.1 7.6±0.2 0.45±0.2 -0.05 +0.10 0.3 0.150.12 M 0.08 1.2±0.10 0.10 +0.10 -0.05 ■ Materials and Lead Specification Package: Epoxy Lead frame: Copper Lead-finish: Soldering plate (Pb free)

[AK7600] MS0999-E-00 2008/09 - 38 - MARKING AKM AK7600VF XXXBYYYYC XXXBYYYYC Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character)

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents 08/09/03 00 First Edition IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these product s, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AK EMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.