AK4950

AK4950 AKM | Alldatasheet

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Technical content

[AK4950] MS1320-E-00 2011/10 - 1 - GENERAL DESCRIPTION The AK4950 is a 24bit stereo CODEC with a microphone, speaker and headphone amplifiers. The input circuits include a microphone amplifier and the output circuits include a speaker amplifier. It is suitable for portable application with recording/playback function. The integrated charge pump generates an internal negative power supply rail and removes the output c oupling capacitor. A one c hannel composite In/Out video amplifier is also integrated. Digital sound processing is provided by the internal DSP. The AK4950 is available in a small 32pin QFN (4mm x 4mm, 0.4mm pitch), saving more board space.

FEATURES

1. Recording Functions

• Stereo Single-ended input with two Selectors
• MIC Amplifier (+24dB/+21dB/+18dB/+16dB/+14dB/+11dB/+8dB/+5dB/0dB)
• Digital ALC (Automatic Level Control) (Setting Range: +35.625dB ∼ −54dB, 0.375dB Step)
• ADC Performance: S/(N+D): 83dB, DR, S/N: 88dB (MIC-Amp=+18dB) S/(N+D): 85dB, DR, S/N: 96dB (MIC-Amp=0dB)
• MIC Sensitivity Compensation
• Wind-noise Reduction Filter
• 4 Band Notch Filter
• Stereo Separation Emphasis Circuit
• Digital MIC Interface 2. Playback Functions
• Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
• Digital ALC (Automatic Level Control) (Setting Range: +35.625dB ~ −54dB, 0.375dB Step)
• Digital Volume Control (+12dB ~ −78dB, 0.375dB Step)
• Stereo Separation Emphasis Circuit
• Stereo Line Output - S/(N+D): 83dB, S/N: 92dB
• Mono Mixing Output
• Mono Speaker-Amplifier - SPK-Amp Performance: S/(N+D): 75dB@150mW, 70dB@250mW, S/N: 95dB - Thermal Shut-down - BTL Output - Output Power: 400mW@8Ω (SVDD=3.3V)
• Analog Mixing: Mono Input 3. Power Management 4. Master Clock: (1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 13.5MHz, 24MHz, 25MHz, 27MHz (MCKI pin) 32fs or 64fs (BICK pin) (2) External Clock Mode
• Frequencies: 512fs or 1024fs (MCKI pin) AK4950 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950] MS1320-E-00 2011/10 - 2 - 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs

• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode: 7.35kHz ∼ 48kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 6. μP I/F: 3-wire Mode, I2C Bus (Ver 1.0, 400kHz Fast-Mode) 7. Master/Slave mode 8. Audio Interface Format: MSB First, 2’s complement
• ADC: 24bit MSB justified, 16/24bit I2S
• DAC: 24bit MSB justified, 16bit LSB justified, 24bit LSB justified, 16/24bit I2S 9. Video Functions
• One Composite Signal Input
• Capacitor-less Video Amplifier for Composite Signal Output
• LPF
• Charge Pump Circuit for Negative Power Supply 11. Power Supply:
• Analog Power Supply (AVDD): 2.7 ~ 3.6V
• Digital I/O Power Supply (TVDD): 1.6 ~ 3.6V 12. Package: 32pin QFN (4 x 4mm, 0.4mm pitch)

3 Band EQ

1 Band EQ

Figure 1. Block Diagram

[AK4950] MS1320-E-00 2011/10 - 4 - ■ Ordering Guide AK4950EN −30 ∼ +85°C 32pin QFN (0.4mm pitch) AKD4950 Evaluation board for AK4950 ■ Pin Layout VSS3 AVDD VCOM VSS1 VOUT VSS4 PVEE VIN SPN SPP I2C REGFILA REGFILB MCKO MCKI VSS2 ROUT/MIN LOUT LIN1 RIN1 MPWR LIN2 RIN2 PDN TVDD BICK LRCK SDTO SDTI CDTIO/CAD0 CCLK/SCL CSN/SDA AK4950EN Top View

[AK4950] MS1320-E-00 2011/10 - 5 - PIN/FUNCTION No Pin Name I/O Function ROUT O Rch Analog Output Pin (PMBP bit = “0”) 1 MIN I Mono Analog Signal Input Pin (PMBP bit = “1”)

2 LOUT O Lch Analog Output Pin

LIN1 I Lch Analog Input Line Input 1Pin (DMIC bit = “0”) 3 DMDAT I Digital Microphone Data Input Pin (DMIC bit = “1”) RIN1 I Rch Analog Input 1 Pin (DMIC bit = “0”) 4 DMCLK O Digital Microphone Clock pin (DMIC bit = “1”)

5 MPWR O MIC Power Supply Pin for Microphone

6 LIN2 I Lch Analog Input 2 pin

7 RIN2 I Rch Analog Input 2 Pin

8 PDN I

Power-down & Reset When “L”, the AK4950 is in power-down mode and is held in reset. The AK4950 must be always reset upon power-up. CSN I Chip Select Pin (I2C pin = “L”) 9 SDA I/O Control Data Input/Output Pin (I2C pin = “H”) CCLK I Control Data Clock Pin (I2C pin = “L”) 10 SCL I Control Data Clock Pin (I2C pin = “H”) CDTIO I/O Control Data Input/Output Pin (I2C pin = “L”) 11 CAD0 I Chip Address Select Pin (I2C pin = “H”)

12 SDTI I Audio Serial Data Input Pin

13 SDTO O Audio Serial Data Output Pin

14 LRCK I/O Input/Output Channel Clock Pin

15 BICK I/O Audio Serial Data Clock Pin

16 TVDD - Digital I/F Power Supply Pin

17 VSS2 - Ground 2 Pin

18 MCKI I External Master Clock Input Pin

19 MCKO O Master Clock Output Pin

20 REGFILB O

LDO Voltage Output pin for Digital Logic (typ 1.8V) This pin must be connected to the VSS1 pin with a 1.0μF capacitor (±50% including tolerance and temperature allowance) in series.

21 REGFILA O

LDO Voltage Output pin for Analog Logic (typ 2.3V) This pin must be connected to the VSS1 pin with a 2.2μF capacitor (±50% including tolerance and temperature allowance) in series.

22 I2C I Control Mode Select Pin “H”: I 2C Bus, “L”: 3-wire mode

The input circuit of the I2C pin is operated by AVDD.

23 SPP O Speaker Amp Positive Output Pin

24 SPN O Speaker Amp Negative Output Pin

25 VSS3 - Ground 3 Pin

26 AVDD - Analog Power Supply Pin

This pin must be connected to VSS4 with a 0.1μF ceramic capacitor in series.

27 VCOM O Common Voltage Output Pin

Bias voltage of ADC inputs and DAC outputs.

28 VSS1 - Ground 1 Pin

29 VOUT O Composite Video Output Pin

30 VSS4 - Ground 4 Pin

31 PVEE O Negative Voltage Output Pin for Video Output

This pin must be connected to VSS4 with a 2.2μF ceramic capacitor in series.

32 VIN I Composite Video Input Pin

Note 1. All input pins except analog input pins (MIN, LIN1, RIN1, LIN2, RIN2, VIN) must not be allowed to float.

[AK4950] MS1320-E-00 2011/10 - 6 - ■ Handling of Unused Pin Unused I/O pins must be processed appropriately as below. Classification Pin Name Setting Analog MPWR, SPN, SPP, ROUT/MIN, LOUT, RIN2, LIN2, LIN1/DMDAT, RIN1/DMCLK, VIN, VOUT These pins must be open. MCKO This pin must be open. Digital MCKI This pin must be connected to VSS2. ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4=0V; Note 2) Parameter Symbol min max Unit Power Supplies: Analog AVDD −0.3 6.0 V Digital I/O TVDD −0.3 6.0 V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 4) VINA −0.3 AVDD+0.3 V Digital Input Voltage (Note 5) VIND −0.3 TVDD+0.3 V Ambient Temperature (powered applied) Ta −30 85 °C Storage Temperature Tstg −65 150 °C Maximum Power Dissipation (Note 6) Pd1 - 450 mW Note 2. All voltages are with respect to ground. Note 3. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog ground plane. Note 4. MIN, LIN1, RIN1, LIN2, RIN2, VIN, I2C pins Note 5. PDN, CSN, CCLK, CDTIO, SDTI, LRCK, BICK, MCKI pins Note 6. In case that PCB wiring density is over 200% and its surface wiring density is over 50%. This power is the AK4950 internal dissipation that does not include power dissipation of externally connected speakers. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4=0V; Note 2) Parameter Symbol min typ max Unit Power Supplies Analog AVDD 2.7 3.3 3.6 V (Note 7) Digital I/O TVDD 1.6 1.8 3.6 V Note 2. All voltages are with respect to ground. Note 7. The power-up sequence between AVDD and TVDD is not critical. The PDN pin must be “L” upon power up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error. * When TVDD is powered ON and the PDN pin is “L”, AVDD can be powered ON/OFF. When the AK4950 is powered ON from power-down state, the PDN pin must be “H” after all power supplies are ON. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4950] MS1320-E-00 2011/10 - 7 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD=3.3V, TVDD= 1.8V; VSS1=VSS2=VSS3=VSS4=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max Unit MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins Input Resistance 23 33 43 kΩ MGAIN3-0 bits = “0000” -1 0 +1 dB MGAIN3-0 bits = “0001” +4 +5 +6 dB MGAIN3-0 bits = “0010” +7 +8 +9 dB Gain MGAIN3-0 bits = “0011” +10 +11 +12 dB MGAIN3-0 bits = “0100” +13 +14 +15 dB MGAIN3-0 bits = “0101” +15 +16 +17 dB MGAIN3-0 bits = “0110” +17 +18 +19 dB MGAIN3-0 bits = “0111” +20 +21 +22 dB MGAIN3-0 bits = “1000” +23 +24 +25 dB MIC Power Supply: MPWR pin Output Noise Level (A-weighted) - −108 - dBV Load Resistance 0.5 - - kΩ Load Capacitance - - 30 pF PSRR (fin =1kHz) - 100 - dB ADC Analog Input Characteristics : LIN1/RIN1/LIN2/RIN2 pins → ADC → IVOL, IVOL=0dB, ALC=OFF Resolution/ - - 24 Bits (Note 10) - 0.261 - Vpp Input Voltage (Note 9) (Note 11) 1.86 2.07 2.28 Vpp (Note 10) 73 83 - dBFSS/(N+D) (−1dBFS) (Note 11) - 85 - dBFS (Note 10) 78 88 - dB D-Range (−60dBFS, A-weighted) (Note 11) - 96 - dB (Note 10) 78 88 - dB S/N (A-weighted) (Note 11) - 96 - dB (Note 10) 75 90 - dB Interchannel Isolation (Note 11) - 100 - dB (Note 10) - 0 0.5 dB Interchannel Gain Mismatch (Note 11) - 0 0.5 dB MICL bit is “0”. Note 9. Vin = 0.9 x 2.3Vpp (typ) @MGAIN3-0 bits = “0000” (0dB) Note 10. MGAIN3-0 bits = “0110” (+18dB) Note 11. MGAIN3-0 bits = “0000” (0dB)

[AK4950] MS1320-E-00 2011/10 - 8 - Parameter min typ max Unit DAC Characteristics: Resolution - - 24 Bits Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, DVOL=OVOL =0dB, LOVL1-0 bit = “01”, RL=10kΩ, PMBP bit= “0” S/(N+D) (−3dBFS) 73 83 - dBFS S/N (A-weighted) 82 92 - dB Interchannel Isolation 85 100 - dB Interchannel Gain Mismatch - - 0.8 dB Load Resistance 10 - - kΩ Load Capacitance - - 30 pF PSRR (fin =1kHz) - 80 - dB Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, DVOL=OVOL =0dB, RL=8Ω, BTL Output Voltage SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW) - 3.18 - Vpp SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW) 3.20 4.00 4.80 Vpp SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW) - 1.79 - Vrms S/(N+D) SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW) - 75 - dB SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW) 20 70 - dB SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW) - 65 - dB S/N SPKG1-0 bits = “01”, −0.5dBFS(Po=250mW) (A-weighted) 85 95 - dB Load Resistance 6.8 - - Ω Load Capacitance - - 30 pF PSRR (fin =1kHz) - 60 - dB LOVL0 bit is “0”.

[AK4950] MS1320-E-00 2011/10 - 9 - Parameter min typ max Unit Mono Input: MIN pin, External Resistance mode (PMBP bit =“1”, BPM bit = “1”, BPVCM bit = “0”, BPLVL2-0 bits = “000”), External Input Resistance= 66kΩ Maximum Input Voltage (Note 13) - 1.54 - Vpp Gain (Note 14) MIN Æ LOUT LOVL1-0 bit = “00” −4.5 0 +4.5 dB LOVL1-0 bit = “01” - +1.34 - dB LOVL1-0 bit = “10” - +2 - dB LOVL1-0 bit = “11” - +3.34 - dB MIN Æ SPP/SPN ALC bit = “0”, SPKG1-0 bits = “00” +1.6 +6.1 +10.6 dB ALC bit = “0”, SPKG1-0 bits = “01” - +8.1 - dB ALC bit = “0”, SPKG1-0 bits = “10” - +10.1 - dB ALC bit = “0”, SPKG1-0 bits = “11” - +12.1 - dB ALC bit = “1”, SPKG1-0 bits = “00” - +8.1 - dB ALC bit = “1”, SPKG1-0 bits = “01” - +10.1 - dB ALC bit = “1”, SPKG1-0 bits = “10” - +12.1 - dB ALC bit = “1”, SPKG1-0 bits = “11” - +14.1 - dB Mono Input: MIN pin, Internal Resistance Mode (PMBP bit =“1”, BPM bit = “0” , BPVCM bit = “0”, BPLVL2-0 bits = “000”) Input Resistance 56 66 76 kΩ Maximum Input Voltage (Note 13) - 1.54 - Vpp Gain MIN Æ LOUT LOVL1-0 bit = “00” -1 0 +1 dB LOVL1-0 bit = “01” - +1.34 - dB LOVL1-0 bit = “10” - +2 - dB LOVL1-0 bit = “11” - +3.34 - dB MIN Æ SPP/SPN ALC bit = “0”, SPKG1-0 bits = “00” +4.1 +6.1 +8.1 dB ALC bit = “0”, SPKG1-0 bits = “01” - +8.1 - dB ALC bit = “0”, SPKG1-0 bits = “10” - +10.1 - dB ALC bit = “0”, SPKG1-0 bits = “11” - +12.1 - dB ALC bit = “1”, SPKG1-0 bits = “00” - +8.1 - dB ALC bit = “1”, SPKG1-0 bits = “01” - +10.1 - dB ALC bit = “1”, SPKG1-0 bits = “10” - +12.1 - dB ALC bit = “1”, SPKG1-0 bits = “11” - +14.1 - dB Note 13. The maximum value is AVDD Vpp when BPVCM bit = “1”. However, it must be set that the output level of MIN-Amp is less than 0.1Vpp by setting BPLVL2-0 bits. Note 14. The gain is in inverse proportion to external input resistance.

[AK4950] MS1320-E-00 2011/10 - 11 - Parameter min typ max Unit Power Supplies: Power Up (PDN pin = “H”) All Circuit Power-up (Note 18) AVDD+TVDD - 22.2 33 mA MIC + ADC (Note 15) AVDD+TVDD - 5.5 - mA DAC + Lineout (Note 16) AVDD+TVDD - 5.2 - mA DAC + SPK-Amp AVDD+TVDD - 6 - mA Video Block (Note 22) AVDD - 12.7 19 mA Power Down (PDN pin = “L”) (Note 17) AVDD+TVDD - 1 5 μA Note 18. When PMADL=PMADR=PMDAC=PMPFIL =PMLO=PMSPK=PMPLL=MCKO=PMBP=PMMP=M/S= PMV bits = “1”, SPK-amp No load, and black signal is only input to the VIN pin in PLL Master Mode (MCKI=12MHz). In this case, the output current of the MPWR pin is 0mA. AVDD=20.7mA (typ), TVDD=1.5mA (typ). Note 19. When PMADL = PMADR bits= “1” and PMPFIL bit = “1” in EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”). Note 20. When PMDAC = PMLO bits= “1” and PMPFIL bit = “1” in EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”). Note 21. When PMDAC = PMSPK =SPPSN bits = “1”, PMPFIL bit = “1”, and No load at SPK-amp in EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”). Note 22. When PMV=PMCP bits = “1”, No-load, and the black signal is only input to the VIN pin. Note 23. All digital input pins are fixed to TVDD or VSS2.

[AK4950] MS1320-E-00 2011/10 - 12 - FILTER CHARACTERISTICS Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): Passband (Note 24) ±0.16dB PB 0 - 17.3 kHz −0.66dB - 19.4 - kHz −1.1dB - 19.9 - kHz −6.9dB - 22.1 - kHz Stopband (Note 24) SB 26.1 - - kHz Passband Ripple PR - - ±0.1 dB Stopband Attenuation SA 73 - - dB Group Delay (Note 25) GD - 19 - 1/fs Group Delay Distortion ΔGD - 0 - μs ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response −3.0dB FR - 3.4 - Hz −0.5dB - 10 - Hz −0.1dB - 22 - Hz DAC Digital Filter (LPF): Passband (Note 24) ±0.05dB PB 0 - 20.0 kHz −6.0dB - 22.05 - kHz Stopband (Note 24) SB 24.1 - - kHz Passband Ripple PR - - ±0.02 dB Stopband Attenuation SA 54 - - dB Group Delay (Note 25) GD - 20 - 1/fs DAC Digital Filter (LPF) + SCF: Frequency Response: 0 ∼ 20.0kHz FR - ±1.0 - dB Note 24. The passband and stopband frequencies scale with fs (system sampling rate). Each response refers to that of Note 25. A calculating delay time which induced by digital filtering. This time is from the input of an analog signal to the setting of 24-bit data of both channels to the ADC output register. For the DAC, this time is from setting the 24-bit data of a channel from the input register to the output of analog signal. Group delay time is the same as the value shown above even when a signal path that includes the programmable filters (1st order HPF + 1st order LPF + 3-band Equalizer + ALC + Equalizer) is selected.

[AK4950] MS1320-E-00 2011/10 - 13 - DC CHARACTERISTICS Parameter Symbol min typ max Unit Audio Interface & Serial µP Interface (CDTIO/CAD0, CSN/SDA, CCLK/SCL, I2C, PDN, BICK, LRCK, SDTI, MCKI pins ) High-Level Input Voltage (Except I2C pin, TVDD ≥ 2.2V) (Except I2C pin, TVDD < 2.2V) (I2C pin) Low-Level Input Voltage (Except I2C pin, TVDD ≥ 2.2V) (Except I2C pin, TVDD < 2.2V) (I2C pin) VIH VIH1 VIL VIL1 70%TVDD 80%TVDD 70%AVDD 30%TVDD 20%TVDD 30%AVDD V V V V V V Audio Interface & Serial µP Interface (CDTIO, SDA MCKO, BICK, LRCK, SDTO pins Output) High-Level Output Voltage (Iout = −80μA) Low-Level Output Voltage (Except SDA pin : Iout = 80μA) (SDA pin, 2.0V ≤ TVDD ≤ 3.6V: Iout = 3mA) (SDA pin, 1.6V ≤ TVDD < 2.0V: Iout = 3mA) VOH VOL1 VOL2 VOL2 TVDD−0.2 0.2 0.4 20%TVDD V V V V Input Leakage Current Iin - - ±10 μA Digital MIC Interface (DMDAT pin Input ; DMIC bit = “1”) High-Level Input Voltage Low-Level Input Voltage VIH2 VIL2 65%AVDD 35%AVDD V V Digital MIC Interface (DMCLK pin Output ; DMIC bit = “1”) High-Level Output Voltage (Iout=−80μA) Low-Level Output Voltage (Iout= 80μA) VOH3 VOL3 AVDD-0.4 0.4 V V Input Leakage Current Iin2 - - ±20 μA

[AK4950] MS1320-E-00 2011/10 - 14 - SWITCHING CHARACTERISTICS (Ta =25°C; AVDD=2.7 ∼ 3.6V, TVDD =1.6 ∼ 3.6V; CL=20pF) Parameter Symbol min typ max Unit PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.256 - 12.288 MHz Duty Cycle dMCK 40 50 60 % LRCK Output Timing Frequency fs 8 - 48 kHz Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - % PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.256 - 12.288 MHz Duty Cycle dMCK 40 50 60 % LRCK Input Timing Frequency fs 8 - 48 kHz Duty Duty 45 - 55 % BICK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns

[AK4950] MS1320-E-00 2011/10 - 15 - Parameter Symbol min typ max Unit PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs 7.35 - 48 kHz Duty Duty 45 - 55 % BICK Input Timing Period PLL3-0 bits = “0010” tBCK - 1/(32fs) - ns PLL3-0 bits = “0011” tBCK - 1/(64fs) - ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns External Slave Mode MCKI Input Timing Frequency 512fs fCLK 3.7632 - 24.576 MHz 1024fs fCLK 7.5264 - 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Input Timing Frequency 512fs fs 7.35 - 48 kHz 1024fs fs 7.35 - 13 kHz Duty Duty 45 - 55 % BICK Input Timing Period tBCK 312.5 - - ns Pulse Width Low tBCKL 130 - - ns Pulse Width High tBCKH 130 - - ns External Master Mode MCKI Input Timing Frequency 512fs fCLK 3.7632 - 24.576 MHz 1024fs fCLK 7.5264 - 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Output Timing Frequency fs 7.35 - 48 kHz Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - %

[AK4950] MS1320-E-00 2011/10 - 16 - Parameter Symbol min typ max Unit Audio Interface Timing Master Mode BICK “↓” to LRCK Edge (Note 26) tMBLR −40 - 40 ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD −70 ns BICK “↓” to SDTO tBSD −70 - 70 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Slave Mode LRCK Edge to BICK “↑” (Note 26) tLRB 50 - - ns BICK “↑” to LRCK Edge (Note 26) tBLR 50 - - ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD ns BICK “↓” to SDTO tBSD - - 80 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Control Interface Timing (3-wire Mode): CCLK Period tCCK 200 - - ns CCLK Pulse Width Low tCCKL 80 - - ns Pulse Width High tCCKH 80 - - ns CDTIO Setup Time tCDS 40 - - ns CDTIO Hold Time tCDH 40 - - ns CSN “H” Time tCSW 150 - - ns CSN Edge to CCLK “↑” (Note 27) tCSS 50 - - ns CCLK “↑” to CSN Edge (Note 27) tCSH 50 - - ns CCLK “↓” to CDTIO (at Read Command) tDCD - - 70 ns CSN “↑” to CDTIO (Hi-Z) (at Read Command)(Note 29) tCCZ - - 70 ns Control Interface Timing (I2C Bus Mode): SCL Clock Frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - μs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - μs Clock Low Time tLOW 1.3 - - μs Clock High Time tHIGH 0.6 - - μs Setup Time for Repeated Start Condition tSU:STA 0.6 - - μs SDA Hold Time from SCL Falling ( Note 30) tHD:DAT 0 - - μs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - μs Rise Time of Both SDA and SCL Lines tR - - 0.3 μs Fall Time of Both SDA and SCL Lines tF - - 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 - - μs Capacitive Load on Bus Cb - - 400 pF Pulse Width of Spike Noise Suppre ssed by Input Filter tSP 0 - 50 ns Note 26. BICK rising edge must not occur at the same time as LRCK edge. Note 27. CCLK rising edge must not occur at the same time as CSN edge. Note 28. I 2C-bus is a trademark of NXP B.V. Note 29. It is the time of 10% potential change of the CDTIO pin when RL=1kΩ (pull-up or TVDD). Note 30. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

[AK4950] MS1320-E-00 2011/10 - 17 - Parameter Symbol min typ max Unit Digital Audio Interface Timing; CL=100pF DMCLK Output Timing Period tSCK - 1/(64fs) - ns Rising Time tSRise - - 10 ns Falling Time tSFall - - 10 ns Duty Cycle dSCK 40 50 60 % Audio Interface Timing DMDAT Setup Time tSDS 50 - - ns DMDAT Hold Time tSDH 0 - - ns Power-down & Reset Timing PDN Pulse Width (Note 31) tPD 150 - - ns PMADL or PMADR “↑” to SDTO valid (Note 32) ADRST bit = “0” tPDV - 1059 - 1/fs ADRST bit = “1” tPDV - 267 - 1/fs Note 31. The AK4950 can be reset by the PDN pin = “L”. When restart the AK4950 after powered-down, set the PDN pin to “L” and change to “H” after a 10ms interval. Note 32. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.

There are the following five clock modes to interface with external devices (Table 1, Table 2). clocks are output from the MCKO pin. Table 1. Clock Mode Setting (x: Don’t care)

0 L PLL Slave Mode

Table 2. Clock pins state in Clock Mode reset state, the AK4950 goes to master mode by changing M/S bit to “1”.

0 Slave Mode (default)

1 Master Mode

Table 3. Select Master/Slave Mode

(PMPLL bit = “0” → “1”) or the sampling frequency is changed, are shown in Table 4. Note 36. The resistor tolerance is ±5% and the capacitor tolerance is ±30%. **Table 4. PLL Mode Setting (*fs: Sampling Frequency, N/A: Not Available)** Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” When PLL2 bit is “0” (PLL reference clock input pin is the BICK pin), the sampling frequency is selected by FS1-0 bits. Table 6). * Since the default setting of FS3-0 bits is “1111” (Not Available), FS3-0 bits must be set when PLL2 bit = “0”. Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2

“0”. During PMPLL bit = “0”, these pins output the same clocks as EXT Master Mode. Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) data when the PLL is unlocked. The DAC outputs can be muted by setting DACL and DACS bits to “0”. Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

Figure 18. PLL Master Mode Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”) Table 10. BICK Output Frequency at Master Mode

CODEC. The external clocks required to operate this mode are MCKI (512fs or 1024fs), LRCK (fs) and BICK (≥32fs). Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins Figure 21. EXT Slave Mode

Table 13. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. Table 14. Relationship between MCKI and S/N of LOUT/ROUT pins Figure 22. EXT Master Mode Table 15. BICK Output Frequency at Master Mode

after the initialization cycle is finished. When using a digital microphone, the initialization cycle is the same as ADC’s. Table 16. ADC Initialization Cycle out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”) of BICK. Table 17. Audio Interface Format

Figure 26. Mode 3 Timing PMDMR bit = “1”, the setting of PMADL and PMADR bits is ignored. Table 18. Mono/Stereo ADC operation (Analog MIC) Table 19. Mono/Stereo ADC operation (Digital MIC)

“1”, digital microphone input is selected regardless of INL and INR bits. Table 20. MIC/Line In Path Select (x: Don’t care, N/A: Not available) 21). The typical input impedance is 30kΩ. Table 21. Input Gain

Table 22. MIC Sensitivity Compensation 2C mode) without setting MAGAINL/R3-0 bits. In this case, the gain can be set in a step less than 0.1dB. Round X off to the closest whole number and convert it to two’s complement. MSB of the MIC sensitivity compensation register is a sign bit. The following is an access sequence to Register Map 2.

1. Addr=01H, Data=xxxxxxH(24bit Data); Lch MIC Sensitivity Compensation Value
2. Addr=02H, Data=xxxxxxH(24bit Data); Rch MIC Sensitivity Compensation Value
3. PMPFIL bit = “1”; Programmable Block Power Up

access to MSGAINL/R3-0 bits of the address 2BH.

minimum 0.5kΩ. In case of using two sets of stereo microphones, the load resistance is minimum 2kΩ for each channel.

0 Hi-Z (default)

1 Output

Table 23. MIC Power Figure 27. MIC Block Circuit

is 24bit full scale when the 1bit data density is 0%~100%.

0 Rch Lch (default)

1 Lch Rch

Table 24. Data In/Output Timing with Digital MIC (DCLKP bit = “0”) Figure 30. Data In/Output Timing with Digital MIC (DCLKP bit = “1”) Figure 31. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)

3 Band

1 Band

(1) ADC: Includes the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”. (2) HPF1: High Pass Filter (HPF) for ADC as shown in “FILTER CHRACTERISTICS”. (4) DAC: Includes the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”. Figure 32. Digital Block Path Select

Table 25. Recording Playback Mode (x: Don’t care) When changing those modes, PMPFIL bit must be “0”. Figure 33. The Path in Recording Mode 1 (default) Figure 34. The Path in Playback Mode 1 Figure 35. The Path in Recording Mode 2 & Playback Mode 2 Figure 36. The Path in Loopback Mode

[AK4950] MS1320-E-00 2011/10 - 41 - ■ Digital Programmable Filter Circuit (1) High Pass Filter (HPF2) Normally, this HPF is used for Wind-Noise Reduction. This is composed 1st order HPF. The coefficient of HPF is set by 03H, 04H, 06H (3-wire mode, COEW bit = “1”) and 83H, 84H and 86H (I2C mode). HPF bit controls ON/OFF of the HPF2. When the HPF2 is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when PMPFIL bit = “0”. The HPF2 starts operation 2/fs (max) after when HPF bit=PMPFIL bit= “1” is set. fs: Sampling Frequency fc: Cutoff Frequency Register Setting (Register Map 2) (

1 Note 37)

A0: Register Addr = 03H(3-wire mode), 83H(I2C mode) A1: Register Addr = 04H(3-wire mode), 84H(I2C mode) B1: Register Addr = 06H(3-wire mode), 86H(I2C mode) A0 = 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) B1 = 1 / tan (πfc/fs) − 1 1 / tan (πfc/fs) + 1 , A1 = − A0, Transfer Function H(z) = A0 1 − z −1 1 − B1 z −1 The cut-off frequency must be set as below. fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz) Setting Example) When fc=150Hz @ fs=44.1kHz (I 2C mode) A0 = 0FD4B1 (hex): Addr. 83H A1 = F02B4F (hex): Addr. 84H B1 = 0FA963 (hex): Addr. 86H

[AK4950] MS1320-E-00 2011/10 - 42 - (2) Low Pass Filter (LPF) This is composed with 1st order LPF. 09H, 0AH, 0CH (3-wire mode, COEW bit = “1”) and 89H~8AH and 8CH (I2C mode) set the coefficient of LPF. LPF bit controls ON/OFF of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when PMPFIL bit = “0”. The LPF starts operation 2/fs (max) after when LPF bit =PMPFIL bit= “1” is set. fs: Sampling Frequency fc: Cutoff Frequency Register Setting (Register Map 2) ( A0: Register Addr = 09H(3-wire mode), 89H(I2C mode) A1: Register Addr = 0AH(3-wire mode), 8AH(I2C mode) B1: Register Addr = 0CH(3-wire mode), 8CH(I2C mode) A0 = A1 = B1 = 1 / tan (πfc/fs) − 1 1 / tan (πfc/fs) + 1 1 + 1 / tan (πfc/fs) Transfer Function H(z) = A0 1 + z −1 1 − B1 z −1 The cut-off frequency must be set as below. fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz) Setting Example) When fc=15kHz @ fs=44.1kHz (I2C mode) A0 = 0A53F3 (hex): Addr. 89H A1 = 0A53F3 (hex): Addr. 8AH B1 = FB581A (hex): Addr. 8CH

[AK4950] MS1320-E-00 2011/10 - 43 - (3) Stereo Separation Emphasis Filter (FIL3) FIL3 is used to emphasize the stereo separation of stereo microphone recording data and playback data. Address 0FH, 10H, 11H, 12H and 13H (3-wire mode, COEW bit = “1”), and address 8FH, 90H, 91H, 92H and 93H (I2C mode) set the filter coefficients of FIL3. FIL3 bit controls ON/OFF of the FIL3. When the stereo separation emphasis filter is OFF, the audio data passes this block by 0dB gain. The coefficient should be set when PMPFIL bit = “0”. The FIL3 starts operation 2/fs(max) after when FIL3 bit =PMPFIL bit= “1” is set. 1) In case of setting FIL3 as LPF fs: Sampling Frequency fc: Cutoff Frequency κ: Gain (0.25 ≤ κ ≤ 1) * κ dB [dB], κ = 10κdB/20 α = sin (2π fc / fs) / 2Q Gain =20 log (Q)[dB] for fs. Normally Q should be set to 0.7071. Register Setting (Register Map2) (1 Note 37) A0: Register Addr = 0FH(3-wire mode), 8FH(I2C mode) A1: Register Addr = 10H(3-wire mode), 90H(I2C mode) A2: Register Addr = 11H(3-wire mode), 91H(I2C mode) B1: Register Addr = 12H(3-wire mode), 92H(I2C mode) B2: Register Addr = 13H(3-wire mode), 93H(I2C mode) A0 = A2 = 1– cos (2πfc/fs) × 1 1+ α × κ A1 = 1– cos (2πfc/fs) 1+ α × κ B1 = 2 cos (2πfc/fs) 1+ α B2 = α +1 α –1 Transfer Function Hx (z) = A0 + A1 z −1 + A2z −2 1 − B1z −1− B2z −2 The cut-off frequency must be set as below. fc / fs < 0.497 Setting Example) When fc=15kHz @ fs=44.1kHz. (I 2C mode) A0 = 03D96B (hex): Addr. 8FH A1 = 07B2D5 (hex): Addr. 90H A2 = 03D96B (hex): Addr. 91H B1 = F53F37 (hex): Addr. 92H B2 = FBF575 (hex): Addr. 93H

emphasis filter. Gain compensation is composed of the Equalizer (EQ0) and the Gain (0dB/+6dB/+12dB/+24dB). Address 19H ~ 1DH(3-wire mode, COEW bit = “1”) and address 99H~9DH (I2C mode) set the coefficient of EQ0. operation 2/fs(max) after when EQ0 bit =PMPFIL bit= “1” is set. A = boost gain. Example) Boost gain = +12dB (A = 10 Gain [dB] / 40 ) when A=2. Gain =20 log (Q)[dB] for fs. Normally Q should be set to 0.7071. The cut-off frequency must be set as below. Figure 37. EQ0 Frequency Response (High –boost)

A = boost gain. Example) Boost gain = +12dB (A = 10 Gain [dB] / 40 ) when A=2. Gain =20 log (Q)[dB] for fs. Normally Q should be set to 0.7071. The cut-off frequency must be set as below. Figure 38. EQ0 Frequency Response (Low –boost)

Table 26. Gain Select of the Gain Block be set when PMPFIL bit = “0”. EQ1-4 start operation 2/fs(max) after when EQx (x=1, 2, 3 or 4) = PMPFIL bit = “1” is set. The cut-off frequency must be set as below.

[AK4950] MS1320-E-00 2011/10 - 47 - 2) When EQ1 ~ EQ4 = Dip boost Filter fs: Sampling Frequency fo: Center Furequency α = sin (2πfc/fs) / 2Q A = Boost gain Example) Boost gain = +12dB (A = 10 Gain [dB] / 40) when A=2. Q = fo/BW (BW: Band Width) A0 = A + α A (1+ αA) A1 = A + α –2Acos (2πfc/fs) A2 = A + α A (1– αA) B1 = A + α 2Acos (2πfc/fs) B2 = A + α A – α The cut-off frequency must be set as below. EQ1, EQ4: 0.0625 < fon / fs < 0.497 EQ2, EQ3: fon / fs < 0.497 Setting Example) EQ2 (Notch Filter ) fs = 44.1kHz, fo = 8kHz, BW =200Hz (I 2C mode) A0 = 0FD201 (hex): Addr. A0H A1 = F2C80F (hex): Addr. A1H A2 = 0FD201 (hex): Addr. A2H B1 = 0D37F1 (hex): Addr. A3H, A5H B2 = F05BFE (hex): Addr. A4H, A6H Note 37. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 2 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit.

Note 38. In this section, VOL means IVL and IVR for recording path, OVL and OVR for playback path. Note 39. In this section, REF means IREF for recording path, OREF for playback path. level exceeds ALC limiter detection level. Table 27. ALC Limiter Detection Level / Recovery Counter Reset Level Table 28. ALC Limiter ATT Amount

VOL values are not increased. the waiting timer of ALC recovery operation starts. Table 29. ALC Recovery Operation Waiting Period Table 30. ALC Recovery GAIN Amount

Table 31. Reference Level of ALC Recovery Operation for Recoding Table 32. Reference Level of ALC Recovery Operation for Playback Table 33. Fast Recovery Gain Setting

1. The Volume at ALC Operation

the register value of VOL7-0 bits. Table 34. Value of VOL7-0 bits

Table 35 and Table 36 show the examples of the ALC setting for recording and playback path. Table 35. Example of the ALC Setting (Recording) Table 36. Example of the ALC Setting (Playback)

1. Example of registers set-up sequence of ALC Operation

Figure 39. Registers Set-up Sequence at ALC1 Operation (recording path)

1. After exiting reset state, when setting up the registers for ALC operation (LMTH and etc.)
2. When the registers for ALC operation (Limiter period, Recovery period and etc.) are changed.

For example; when the sampling frequency is changed.

1. When IVOL is used as a manual volume control.

together when IVOLC bit = “1”. Table 37. Input Digital Volume Setting PMPFIL bit is changed to “1”. can be reduced by setting into soft mute sate (SMUTE bit = “1”) before changing ADCPF bit.

soft mute sate (SMUTE bit = “1”) before changing ADCPF bit. Table 38. Output Digital Volume Setting Table 39. The Table 39. Output Digital Volume2 Setting

44.1kHz). HPFAD bit controls the ON/OFF of the HPF1 (HPF ON is recommended). Table 40. HPF1 Cut-off Frequency 44kHz, 48kHz) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 41). Table 41. De-emphasis Control

path. SMUTE bit is invalid during an ALC operation. Figure 40. Soft Mute Function (1) The input signal is attenuated to −∞ (“0”) during 10ms@fs =44.1kHz. (2) Analog output corresponding to digital input has group delay (GD). DVOL7-0 bits within the same cycle.

LOVL1-0 bits set the gain of stereo line output. Figure 41. Stereo Line Output

0 Power Down Pull-down to VSS1 (default) 0 1 Normal Operation Normal Operation

0 Power Save Fall down to VSS1

Table 42. Stereo Line Output Mode Select Table 43. Stereo Lineout Volume Setting Figure 42. External Circuit for Stereo Line Output (in case of using a Pop Noise Reduction Circuit)

Figure 43. Stereo Line Output Control Sequence (in case of using a Pop Noise Reduction Circuit) (1) Set LOPS bit = “1”. Stereo line output enters the power-save mode. (2) Set PMLO bit = “1”. Stereo line output exits the power-down mode. LOUT and ROUT pins rise up to common voltage. Rise time is 200ms (max 300ms) when C=1μF. (3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode. Stereo line output is enabled. (4) Set LOPS bit = “1”. Stereo line output enters power-save mode. (5) Set PMLO bit = “0”. Stereo line output enters power-down mode. LOUT and ROUT pins fall down to 1% of the common voltage. Fall time is 200ms (max 300ms) at C=1μF. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. Table 44. LOUT/ROUT pin Output Data Switch

LOPS= EXTC bits= “1”. When using the LOUT (or ROUT) pin as DAC output, the LIN1 (or RIN1) pin is pulled up (typ. 100kΩ) to typ. 1.35V* by setting PMADC=LOPS bits = “0” and EXTC bit = “1”. Table 45. LIN1/RIN1 and LOUT/ROUT Mode Setting (x: Don’t care) Figure 44. LIN1/RIN1→ADC path: External Line Share

Figure 45. DAC→ LOUT/ROUT path: External Line Share “1”, the ROUT/MIN pin becomes mono input pin (MIN pin mode). Table 46. ROUT/MIN pin Mode Select (x: Don’t care) signal gain which is in inverse proportion to Ri resister value. set by BPLVL2-0 bits, speaker amplifier gain (SPKG1-0 bits) and stereo lineout amplifier gain (LOVL1-0 bits).

1 External Resistance Mode

0 Internal Resistance Mode (default)

Table 47. BEEP Mode Setting

1. External Resistance Mode (BPM bit = “1”)

Figure 46. Block Diagram of MIN pin (PMBP bit = “1”, BPM bit =“1”) Table 48. MIN Æ LOUT Output Gain Table 49. MIN Æ SPK Output Gain

1. Internal Resistance Mode (BPM bit = “0”)

Table 50. BEEP Output Gain Setting when BPM bit = “0” Figure 47. Block Diagram of MIN pin (PMBP bit = “1”, BPM bit =“0”)

on AVDD and SPKG1-0 bits setting. Table 51. SPK-Amp Gain under 4.0Vpp (AVDD=3.3V) by adjusting digital volume to prevent clipped noise. Table 52. SPK-Amp Output Level

pin is placed in Hi-Z state and the SPN pin outputs AVDD/2 voltage. “0”), pop noise can also be reduced by first entering power-save-mode.

0 Power-save Hi-Z AVDD/2 1 1 Normal Operation Normal Operation Normal Operation

Figure 48. Power-up/Power-down Timing for Speaker-Amp

power management is controlled by PMV bit. The charge pum p circuit power management is controlled by PMCP bit. signal source impedance at transmitting side must not over 600Ω. Figure 49. Video Block Diagram Table 54. Video Signal Gain Setting

Figure 53. 3-wire Mode Control Interface Timing (COEW bit = “1”)

[AK4950] MS1320-E-00 2011/10 - 74 - ■ Register Map 1 Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 00H Power Management 1 PMPFIL 0 PMBP PMSPK PMLO PMDAC PMADR PMADL 01H Power Management 2 ADRST 0 0 0 M/S PMMP MCKO PMPLL 02H MIC gain Control 1 0 0 0 0 MGAIN3 M GAIN2 MGAIN1 MGAIN0 03H Gain Control MICL 0 SPPKG1 SPKG0 0 0 LOVL1 LOVL0 04H Mode Control 1 SPPSN LOPS 0 0 BEEPS BEEPL DACS DACL 05H Mode Control 2 READ MLOUT 0 0 0 0 INR INL 06H Mode Control 3 0 0 EXTC 0 MONO1 MONO0 DEM1 DEM0 07H PLL Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0 08H PLL Control 2 PS1 PS0 0 0 FS3 FS2 FS1 FS0 09H Digital MIC 0 0 PMDMR PMDML 0 DCLKE DCLKP DMIC 0AH BEEP Control BPM 0 0 BPVCM 0 BPLVL2 BPLVL1 BPLVL0 0BH HPF Control 0 0 0 0 0 HPFC1 HPFC0 HPFAD 0CH Video Control 0 0 0 0 VG1 VG0 PMCP PMV 0DH Mode Control 4 THDET 0 0 0 0 0 0 COEW 0EH Mode Control 5 0 0 0 0 0 0 0 INIT 0FH ALC Level VOL7 VOL6 VOL 5 VOL4 VOL3 VOL2 VOL1 VOL0 10H Reserved 0 0 0 0 0 0 0 0 11H Reserved 0 0 0 0 0 0 0 0 12H Reserved 0 0 0 0 0 0 0 0 13H Reserved 0 0 0 0 0 0 0 0 14H Reserved 0 0 0 0 0 0 0 0 15H Reserved 0 0 0 0 0 0 0 0 16H Reserved 0 0 0 0 0 0 0 0 17H Reserved 0 0 0 0 0 0 0 0 18H Reserved 0 0 0 0 0 0 0 0 19H Reserved 0 0 0 0 0 0 0 0 1AH Reserved 0 0 0 0 0 0 0 0 1BH Reserved 0 0 0 0 0 0 0 0 1CH Reserved 0 0 0 0 0 0 0 0 1DH Reserved 0 0 0 0 0 0 0 0 1EH Reserved 0 0 0 0 0 0 0 0 1FH Reserved 0 0 0 0 0 0 0 0 20H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 21H Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 22H Lch Output Volume Control OVL7 OVL6 OVL5 OVL4 OVL3 OVL2 OVL1 OVL0 23H Rch Output Volume Control OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 24H ALC Mode Contorl 1 IREF7 IREF6 IREF5 IREF4 IREF3 IREF2 IREF1 IREF0 25H ALC Mode Contorl 2 OREF7 OREF6 OREF5 OREF4 OREF3 OREF2 OREF1 OREF0 26H ALC Mode Contorl 3 0 0 WTM1 WTM0 0 0 RFST1 RFST0 27H ALC Mode Contorl 4 SMUTE ALC RGAIN2 RGAIN1 RGAIN0 0 LMTH1 LMTH0 28H Reserved 0 0 0 0 0 0 0 0 29H Reserved 0 0 0 0 0 0 0 0 2AH Digital Volume Control DVOL 7 DVOL6 DVOL5 DVOL4 DVOL 3 DVOL2 DVOL1 DVOL0 2BH MIC Gain Control 2 MSGAINR3 MSGAINR2 MSGAINR 1 MSGAINR0 MSGAINL3 MSGAI NL2 MSGAINL1 MSGAINL0 2CH Digital Filter Contorl 1 0 0 0 PFSDO PFDAC ADCPF OVOLC IVOLC 2DH Digital Filter Contorl 2 0 0 LPF HPF EQ0 GN1 GN0 FIL3 2EH Digital Filter Contorl 3 0 0 0 0 EQ4 EQ3 EQ2 0 2FH Reserved 0 0 0 0 0 0 0 0 Note 42. PDN pin = “L” resets the registers to their default values. Note 43. The bits defined as 0 must contain a “0” value. Note 44. Address 0FH is a read only register. Writing access to 0FH is ignored and does not effect the operation. Note 45. D15~D0 registers must contain “0” value.

[AK4950] MS1320-E-00 2011/10 - 75 - ■ Register Map 2: Filter Coefficient (COEW bit = “1”) Control Register Addr I2C pin =“L” (3-wire mode) I2C pin =“H” (I2C mode) Register Name Initial 01H 81H Lch input volume 100000H 02H 82H Rch input volume 100000H 03H 83H HPF A0 100000H 04H 84H HPF A1 000000H 06H 86H HPF B1 000000H 09H 89H LPF A0 100000H 0AH 8AH LPF A1 000000H 0CH 8CH LPF B1 000000H 0FH 8FH Stereo Filter A0 100000H 10H 90H Stereo Filter A1 000000H 11H 91H Stereo Filter A2 000000H 12H 92H Stereo Filter B1 000000H 13H 93H Stereo Filter B2 000000H 19H 99H EQ0 A0 100000H 1AH 9AH EQ0 A1 000000H 1BH 9BH EQ0 A2 000000H 1CH 9CH EQ0 B1 000000H 1DH 9DH EQ0 B2 000000H 20H A0H EQ2 A0 100000H 21H A1H EQ2 A1 000000H 22H A2H EQ2 A2 000000H 23H A3H EQ2 B1 000000H 24H A4H EQ2 B2 000000H 25H A5H EQ2 B1 000000H 26H A6H EQ2 B2 000000H 29H A9H EQ3 A0 100000H 2AH AAH EQ3 A1 000000H 2BH ABH EQ3 A2 000000H 2CH ACH EQ3 B1 000000H 2DH ADH EQ3 B2 000000H 2EH AEH EQ3 B1 000000H 2FH AFH EQ3 B2 000000H 32H B2H EQ4 A0 100000H 33H B3H EQ4 A1 000000H 34H B4H EQ4 A2 000000H 35H B5H EQ4 B1 000000H 36H B6H EQ4 B2 000000H 6BH EBH EQ1 A0 100000H 6CH ECH EQ1 A1 000000H 6DH EDH EQ1 A2 000000H 6EH EEH EQ1 B1 000000H 6FH EFH EQ1 B2 000000H

[AK4950] MS1320-E-00 2011/10 - 76 - ■ Register Definitions Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 00H Power Management 1 PMPFIL 0 PMBP PMSPK PMLO PMDAC PMADR PMADL R/W R/W R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMADL: MIC-Amp Lch and ADC Lch Power Management 0: Power-down (default) 1: Power-up PMADR: MIC-Amp Rch, ADC Rch Power Management 0: Power down (default) 1: Power up When the PMADL or PMADR bit is changed from “0 ” to “1”, the initialization cycle (1059/fs=24ms @44.1kHz, ADRST bit = “0”) starts. After initializing, digital data of the ADC is output. PMDAC: DAC Power Management 0: Power-down (default) 1: Power-up PMLO: Stereo Line Output Power Management 0: Power-down (default) 1: Power-up PMSPK: Speaker-Amp Power Management 0: Power-down (default) 1: Power-up PMBP: Mono Input Power Management 0: Power-down (default) 1: Power-up The ROUT/MIN pin performs as MIN pin. BEEPL and BEEPS bits control the path settings of Rch lineout and speaker from the MIN pin respectively. PMPFIL: Programmable Filter Block (HPF2/LPF/FIL3/EQ/5 Band EQ/ALC) Power Management (DSP system reset) 0: Power down (default) 1: Power up All blocks except regulators can be powered-down by writing “0” to the address “00H”, PMPLL, PMMP, PMDML, PMDMR, DMPE, PMADR, PMV, PMCP and MCKO bits. In this case, register values are maintained.

[AK4950] MS1320-E-00 2011/10 - 77 - Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 01H Power Management 2 ADRST 0 0 0 M/S PMMP MCKO PMPLL R/W R/W R R R R/ W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMPLL: PLL Power Management 0: EXT Mode and Power down (default) 1: PLL Mode and Power up MCKO: Master Clock Output Enable 0: Disable: MCKO pin = “L” (default) 1: Enable: Output frequency is selected by PS1-0 bits. PMMP: MIC Power Management 0: Power down (default) 1: Power up M/S: Master / Slave Mode Select 0: Slave Mode (default) 1: Master Mode ADRST: ADC Initializing Cycle Select 0: 1059/fs (default) 1: 267/fs Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 02H MIC gain Control 1 0 0 0 0 MGAIN3 MGAIN2 MGAIN1 MGAIN0 R/W R R R R R/W R/W R/W R/W Default 0 0 0 0 0 1 1 0 MGAIN3-0: MIC-Amp Gain Control ( Table 21) Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 03H Gain Control MICL 0 SPKG1 SPKG0 0 0 LOVL1 LOVL0 R/W R/W R R/W R/ W R R R/W R/W Default 0 0 0 0 0 0 0 1 LOVL1-0: Stereo Line Output Gain and Signal Ground Setting ( Table 43) SPKG1-0: Speaker-Amp Output Gain Select ( Table 51) MICL: MIC Power Output Voltage Select 0: typ 2.5V (AVDD=3.0 ~ 3.6V) (default) 1: typ 2.2V (AVDD = 2.7 ~ 3.6V)

[AK4950] MS1320-E-00 2011/10 - 78 - Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 04H Mode Control 1 SPPSN LOPS 0 0 BEEPS BEEPL DACS DACL R/W R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DACL: DAC Output Signal to Stereo Line Amp Control 0: OFF (default) 1: ON When PMLO bit = “1”, this bit setting is enabled. LOUT and ROUT pins output VSS1 when PMLO bit = “0”. DACS: Signal Switch Control from DAC to Speaker-Amp 0: OFF (default) 1: ON When DACS bit is “1”, DAC output signal is input to Speaker-Amp. BEEPL: Signal Switch Control from the MIN pin to Lineout 0: OFF (default) 1: ON This setting is valid when PMBP bit = “1”. Set BEEP signal input mode by BPM bit. The signal from the MIN pin is input to lineout by BEEPL bit = “1”. BEEPS: Signal Switch Control from the MIN pin to Speaker-Amp 0: OFF (default) 1: ON This setting is valid when PMBP bit = “1”. Set BEEP signal input mode by BPM bit. The signal from the MIN pin is input to lineout by BEEPS bit = “1”. LOPS: Stereo Line Output Power Save 0: Normal Operation (default) 1: Power Save Mode SPPSN: Speaker-Amp Power-Save Mode 0: Power-Save Mode (default) 1: Normal Operation When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, the SPP pin goes to Hi-Z and the SPN pin outputs AVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “L”, Speaker-Amp is in power-down mode since PMSPK bit is “0”. Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 05H Mode Control 2 READ MLOUT 0 0 0 0 INR INL R/W R/W R/W R R R R R/W R/W Default 0 0 0 0 0 0 0 0 INL: ADC Lch Input Source Select 0: LIN1 pin (default) 1: LIN2 pin INR: ADC Rch Input Source Select 0: RIN1 pin (default) 1: RIN2 pin

[AK4950] MS1320-E-00 2011/10 - 79 - MLOUT: Lineout Mono Mode Switch 0: Lineout Stereo mode (default) Both L and R channel lineout amplifiers are powered-up when PMLO bit = “0”. 1: Lineout Mono mode Only L channel lineout amplifier is powered-up when PMLO bit = “1”. R channel lineout amplifier is powered-down. READ: Read Function Enable 0: Disable (default) 1 : E n a b l e Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 06H Mode Control 3 0 0 EXTC 0 MONO1 MONO0 DEM1 DEM0 R/W R R R/W R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 DEM1-0: De-emphasis Control (Table 41) Default: “01” (OFF) MONO1-0: LOUT/ROUT Output Signal Mode Select (Table 44) EXTC: LIN1/RIN1 and LOUT/ROUT External Connect Mode Switch (Table 45) 0: External Connect Mode Disable (default) 1: External Connect Mode Enable Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 07H PLL Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0 R/W R/W R/W R/W R/ W R/W R R/W R/W Default 0 1 1 0 0 0 1 0 DIF1-0: Audio Interface Format (Table 17) Default: “10” (MSB justified) BCKO: Master Mode BICK Output Frequency Setting ( Table 10) PLL3-0: PLL Reference Clock Select ( Table 4) Default: “0110” (MCKI pin, 12MHz) Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 08H PLL Control 2 PS1 PS0 0 0 FS3 FS2 FS1 FS0 R/W R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 1 1 1 1 FS3-0: Sampling frequency ( Table 5, Table 6) and MCKI frequency (Table 11) Setting These bits control sampling frequency in PLL mode and control MCKI input frequency in EXT mode. PS1-0: MCKO Frequency Setting (Table 9) Default: “00” (256fs)

[AK4950] MS1320-E-00 2011/10 - 80 - Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 09H Digital MIC 0 0 PMDMR PMDML 0 DCLKE DCLKP DMIC R/W R R R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 DMIC: Digital Microphone Connection Select 0: Analog Microphone (default) 1: Digital Microphone DCLKP: Data Latching Edge Select 0: Lch data is latched on the DMCLK rising edge (“ ↑”). (default) 1: Lch data is latched on the DMCLK falling edge (“ ↓”). DCLKE: DMCLK pin Output Clock Control 0: “L” Output (default) 1: 64fs Output PMDML/R: Input Signal Select with Digital Microphone ( Table 19) Default: “00” ADC digital block is powered-down by PMDML = PMDMR bits = “0” when selecting a digital microphone input (DMIC bit = “1”, INL/R bits = “00”, “01” or “10”). Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 0AH BEEP Control BPM 0 0 BPVCM 0 BPLVL2 BPLVL1 BPLVL0 R/W R/W R R R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BPLVL2-0: BEEP Output Level Setting (Table 50) Default: “0H”: 0dB BPVCM: Common Voltage Setting of MIN Input Amplifier 0: 1.15V (default) 1: 1.65V BPM: BEEP Mode Setting ( Table 47) Default: “0”: Internal Resistance Mode

When PMADL bit = “1” or PMADR bit = “1”, set HPFAD bit to “1”.

[AK4950] MS1320-E-00 2011/10 - 82 - Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 0DH Mode Control 4 THDET 0 0 0 0 0 0 COEW R/W R R R R R R R R/W Default 0 0 0 0 0 0 0 0 COEW: Filter Coefficient Write Enable 0: Disable (default) 1 : E n a b l e THDET: Thermal Shutdown Detection (READ only) This bit becomes “1” when the internal temperature of LSI exceeds 170°C (typ). When THDET bit changes to “1”, PMSPK, PMLO, PMV and PMCP bits become “0” forc ibly. THDET bit returns to “0” when the internal temperature is down, however, PMSPK, PMLO, PMV and PMCP bits stays “0”. Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 0EH Mode Control 5 0 0 0 0 0 0 0 INIT R/W R R R R R R R R/W Default 0 0 0 0 0 0 0 0 INIT: Programmable Filter Initializing Programmable filter coefficients are initialized by INIT bit = “1”. INIT bit returns to “0” automatically when the initialization is finished. This initialization must be made after clocks are input following the PDN pin = “L” → “H”. Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 0FH ALC Volume VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 R/W R R R R R R R R Default - - - - - - - - VOL7-0: Current ALC volume value, Read operation only (Table 34) (ALC Registers) Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 20H Lch Intput Volume Control IVL7 IV L6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 21H Rch Intput Volume Control IVR7 IV R6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 1 0 0 0 0 1 IVL7-0, IVR7-0: Input Digital Volume Default: “E1H” (+30dB) Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 22H Lch Output Volume Control OVL7 OVL6 OVL5 OVL4 OVL3 OVL2 OVL1 OVL0 23H Rch Output Volume Control OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 0 0 1 0 0 0 1 OVL7-0, OVR7-0: Output Digital Volume Default: “91H” (0dB)

[AK4950] MS1320-E-00 2011/10 - 83 - Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 24H ALC Mode Control 1 IREF7 IREF6 I REF5 IREF4 IREF3 IREF2 IREF1 IREF0 25H ALC Mode Control 2 OREF7 OREF6 OREF5 OREF4 OREF3 OREF2 OREF1 OREF0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 1 0 0 0 0 1 IREF7-0: Reference Value of ALC Recovery Operation (Recording). 0.375dB step, 242 Level (Table 31) OREF7-0: Reference Value of ALC Recovery Operation (Playback). 0.375dB step, 242 Level (Table 32) Default: “E1H” (+30.0dB) Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 26H ALC Mode Control 3 0 0 WTM1 WTM0 0 0 RFST1 RFST0 R/W R R R/W R/W R R R/W R/W Default 0 0 0 0 0 0 0 0 RFST1-0: ALC First Recovery Speed ( Table 33) Default: “00” * Writing to these registers is valid only when PMFIL bit =“0”. When PMFIL bit = “1”, writings are ignored. WTM1-0: ALC Recovery Waiting Period ( Table 29) Default: “00” Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 27H ALC Mode Control 3 SMUTE ALC RGAIN2 RGAIN1 RGAIN0 0 LMTH1 LMTH0 R/W R/W R/W R/W R/ W R/W R R/W R/W Default 0 0 0 0 0 0 0 0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 27) Default: “00” RGAIN2-0: ALC Recovery GAIN Step ( Table 30) Default: “000” * Writing to these registers is valid only when PMFIL bit =“0”. When PMFIL bit = “1”, writings are ignored. ALC: ALC Enable 0: ALC Disable (default) 1 : A L C E n a b l e SMUTE: Soft Mute Control 0: Normal Operation (default) 1: DAC outputs soft-muted * This bit is invalid during an ALC operation.

[AK4950] MS1320-E-00 2011/10 - 84 - Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 2AH Digital Volume Control DVOL 7 DVOL6 DVOL5 DVOL4 DVOL 3 DVOL2 DVOL1 DVOL0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 0 0 0 0 0 1 DVOL7-0: Output Digital Volume 2 (Table 39) Default: “C1H” (0dB) Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 2BH MIC Gain Control 2 MSGAINR3 MSGAI NR2 MSGAINR1 MSGAINR0 M SGAINL3 MSGAINL2 MSGAINL1 MSGAINL0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 MSGAINL0-3: Lch Mic Sensitivity Compensation ( Table 22) MSGAINR0-3: Rch Mic Sensitivity Compensation ( Table 22) Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 2CH Digital Filter Control 1 0 0 0 PFSDO PFDAC ADCPF OVOLC IVOLC R/W R R R R/W R/ W R/W R/W R/W Default 0 0 0 0 0 1 1 1 IVOLC: IVOL Control 0: Independent 1: Dependent (default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume levels, while register values of IVL7-0 bits are not written to IVR7-0 bits. OVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When OVOLC bit = “1”, OVL7-0 bits control both Lch and Rch volume levels, while register values of OVL7-0 bits are not written to OVR7-0 bits. ADCPF: Programmable Filter / ALC Input Signal Select 0: SDTI 1: ALC Output (default) PFDAC: DAC Input Signal Select 0: SDTI (default) 1: Programmable Filter / ALC Output PFSDO: SDTO Output Signal Select 0: ADC (+ 1st HPF) Output 1: Programmable Filter / ALC Output (default)

[AK4950] MS1320-E-00 2011/10 - 85 - Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 2DH Digital Filter Control 2 0 0 LPF HPF EQ0 GN1 GN0 FIL3 R/W R R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 FIL3: Stereo Emphasis Filter Control 0: OFF (default) 1: ON When FIL3 bit = “1”, the settings of 8FH ~ 93H are enabled. GN1-0: Gain Block Gain Setting (Table 26) Default: “00” (0dB) EQ0: Gain Compensation Filter (EQ0) Control 0: OFF (default) 1: ON When EQ0 bit = “1”, the settings of 99H ~ 9DH are enabled. When EQ0 bit = “0”, EQ0 block is through (0dB). HPF: HPF2 Coefficient Setting Enable 0: OFF (default) 1: ON When HPF bit is “1”, the settings of 83H ~ 87H are enabled. When HPF bit is “0”, HPF2 block is through (0dB). LPF: LPF Coefficient Setting Enable 0: OFF (default) 1: ON When LPF bit is “1”, the settings of 89H ~ 8DH are enabled. When LPF bit is “0”, LPF block is through (0dB).

[AK4950] MS1320-E-00 2011/10 - 86 - Addr Register Name D23 D22 D21 D20 D19 D18 D17 D16 2EH Digital Filter Control 3 0 0 0 0 EQ4 EQ3 EQ2 0 R/W R R R R R/W R/W R/W R Default 0 0 0 0 0 0 0 0 EQ2: Equalizer 2 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ2 bit is “1”, the settings of A0H ~ A6H are enabled. When EQ2 bit is “0”, EQ2 block is through (0dB). EQ3: Equalizer 3 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ3 bit is “1”, the settings of A9H ~ AFH are enabled. When EQ3 bit is “0”, EQ3 block is through (0dB). EQ4: Equalizer 4 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ4 bit is “1”, the settings of B2 ~ B6H are enabled. When EQ4 bit is “0”, EQ4 block is through (0dB).

[AK4950] MS1320-E-00 2011/10 - 87 - Register Map 2 MIC Sensitivity Compensation Coefficient D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 01H (3-wire) 81H (I2C) Lch input volume 0001 0000 0000 0000 0000 0000 02H (3-wire) 82H (I2C) Rch input volume 0001 0000 0000 0000 0000 0000 R/W W W W W W W * MIC sensitivity compensation gain can be written to the DSP directly without setting register 2BH. HPF2 Coefficient D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 03H (3-wire) 83H (I2C) HPF A0 0001 0000 0000 0000 0000 0000 04H (3-wire) 84H (I2C) HPF A1 0000 0000 0000 0000 0000 0000 06H (3-wire) 86H (I2C) HPF B1 0000 0000 0000 0000 0000 0000 R/W W W W W W W * When the coefficients are in default setting, audio data passes through this block by 0dB gain even if HPF bit = “1”. LPF Coefficient D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 09H (3-wire) 89H (I2C) LPF A0 0001 0000 0000 0000 0000 0000 0AH (3-wire) 8AH (I2C) LPF A1 0000 0000 0000 0000 0000 0000 0CH (3-wire) 8CH (I2C) LPF B1 0000 0000 0000 0000 0000 0000 R/W W W W W W W * When the coefficients are in default setting, audio data passes through this block by 0dB gain even if LPF bit = “1”. Stereo Emphasis FIL3 Coefficient D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 0FH (3-wire) 8FH (I2C) Stereo Filter A0 0001 0000 0000 0000 0000 0000 10H (3-wire) 90H (I2C) Stereo Filter A1 0000 0000 0000 0000 0000 0000 11H (3-wire) 91H (I2C) Stereo Filter A2 0000 0000 0000 0000 0000 0000 12H (3-wire) 92H (I2C) Stereo Filter B1 0000 0000 0000 0000 0000 0000 13H (3-wire) 93H (I2C) Stereo Filter B2 0000 0000 0000 0000 0000 0000 R/W W W W W W W * When the coefficients are in default setting, audio data passes through this block by 0dB gain even if FIL3 bit = “1”.

[AK4950] MS1320-E-00 2011/10 - 88 - Stereo Emphasis EQ0 (Gain compensation) Coefficient D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 19H (3-wire) 99H (I2C) EQ0 A0 0001 0000 0000 0000 0000 0000 1AH (3-wire) 9AH (I2C) EQ0 A1 0000 0000 0000 0000 0000 0000 1BH (3-wire) 9BH (I2C) EQ0 A2 0000 0000 0000 0000 0000 0000 1CH (3-wire) 9CH (I2C) EQ0 B1 0000 0000 0000 0000 0000 0000 1DH (3-wire) 9DH (I2C) EQ0 B2 0000 0000 0000 0000 0000 0000 R/W W W W W W W * When the coefficients are in default setting, audio data passes through this block by 0dB gain even if EQ0 bit = “1”. EQ2 Coefficient D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 20H (3-wire) A0H (I2C) EQ2 A0 0001 0000 0000 0000 0000 0000 21H (3-wire) A1H (I2C) EQ2 A1 0000 0000 0000 0000 0000 0000 22H (3-wire) A2H (I2C) EQ2 A2 0000 0000 0000 0000 0000 0000 23H (3-wire) A3H (I2C) EQ2 B1 0000 0000 0000 0000 0000 0000 24H (3-wire) A4H (I2C) EQ2 B2 0000 0000 0000 0000 0000 0000 25H (3-wire) A5H (I2C) EQ2 B1 0000 0000 0000 0000 0000 0000 26H (3-wire) A6H (I2C) EQ2 B2 0000 0000 0000 0000 0000 0000 R/W W W W W W W * When the coefficients are in default setting, audio data passes through this block by 0dB gain even if EQ2 bit = “1”. EQ3 Coefficient D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 29H (3-wire) A9H (I2C) EQ3 A0 0001 0000 0000 0000 0000 0000 2AH (3-wire) AAH (I2C) EQ3 A1 0000 0000 0000 0000 0000 0000 2BH (3-wire) ABH (I2C) EQ3 A2 0000 0000 0000 0000 0000 0000 2CH (3-wire) ACH (I2C) EQ3 B1 0000 0000 0000 0000 0000 0000 2DH (3-wire) ADH (I2C) EQ3 B2 0000 0000 0000 0000 0000 0000 2EH (3-wire) AEH (I2C) EQ3 B1 0000 0000 0000 0000 0000 0000 2FH (3-wire) AFH (I2C) EQ3 B2 0000 0000 0000 0000 0000 0000 R/W W W W W W W * When the coefficients are in default setting, audio data passes through this block by 0dB gain even if EQ3 bit = “1”. EQ4 Coefficient

[AK4950] MS1320-E-00 2011/10 - 89 - D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 32H (3-wire) B2H (I2C) EQ4 A0 0001 0000 0000 0000 0000 0000 33H (3-wire) B3H (I2C) EQ4 A1 0000 0000 0000 0000 0000 0000 34H (3-wire) B4H (I2C) EQ4 A2 0000 0000 0000 0000 0000 0000 35H (3-wire) B5H (I2C) EQ4 B1 0000 0000 0000 0000 0000 0000 36H (3-wire) B6H (I2C) EQ4 B2 0000 0000 0000 0000 0000 0000 R/W W W W W W W * When the coefficients are in default setting, audio data passes through this block by 0dB gain even if EQ4 bit = “1”. EQ1 Coefficient D23 ~ D20 D19 ~ D16 D15 ~ D12 D11 ~ D8 D7 ~ D4 D3 ~ D0 Addr Register Name Default 6BH (3-wire) EBH (I2C) EQ1A0 0001 0000 0000 0000 0000 0000 6CH (3-wire) ECH (I2C) EQ1 A1 0000 0000 0000 0000 0000 0000 6DH (3-wire) EDH (I2C) EQ1 A2 0000 0000 0000 0000 0000 0000 6EH (3-wire) EEH (I2C) EQ1 B1 0000 0000 0000 0000 0000 0000 6FH (3-wire) EFH (I2C) EQ1 B2 0000 0000 0000 0000 0000 0000 R/W W W W W W W * When the coefficients are in default setting, audio data passes through this block by 0dB gain even if EQ1 bit = “1”.

[AK4950] MS1320-E-00 2011/10 - 91 - 1. Grounding and Power Supply Decoupling The AK4950 requires careful attention to power supply and grounding arrangements. A ceramic capacitor of 0.1μF or more should be connected to between AVDD and VSS1/3/4. If AVDD and TVDD are supplied separately, the power-up sequence is not critical. VSS1, VSS2, VSS3 and VSS4 of the AK4950 must be connected to the analog ground plane. System analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors must be as near to the AK4950 as possible, with the small value ceramic capacitor being the nearest. 2. Internal Regulated Voltage Power Supply VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4950. 3. Analog Inputs The Mic and Line inputs supports single-ended. The input signal range scales with nominally at typ. 0.9 x 2.3Vpp (@ MGAIN = 0dB), centered around the internal signal ground (typ. 1.15V). Usually the input signal is AC coupled with a capacitor. The cut-off frequency is fc = 1/(2πRC). The AK4950 can accept input voltages from VSS1 to AVDD. 6. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit data). The common voltage of stereo lineout is 1.35V or 1.43V (typ) and the speaker output is centered on AVDD/2 (typ).

When ADC, DAC, Digital Microphone and Programmable Filter are used, the clocks must be supplied. Figure 66. Clock Set Up Sequence (1) “L” time (1) of 150ns or more is needed to reset the AK4950. Wait time of 1ms or more is needed for the internal VCOM voltage rising. (8) Invalid clock is output from MCKO pin during this period when MCKO bit = “1”. (9) Normal clock is output from the MCKO pin after PLL is locked when MCKO bit = “1”. initialization is finished. This initialization must be executed when using ALC and Programmable Filter.

1. When the external clock (BICK pin) is used in PLL Slave mode.

Figure 67. Clock Set Up Sequence (2) “L” time (1) of 150ns or more is needed to reset the AK4950. Wait time of 1ms or more is needed for the internal VCOM voltage rising. (6) Normal operation starts after the PLL is locked. initialization must be executed when using ALC and Programmable Filter.

1. When the external clock (MCKI pin) is used in PLL Slave mode.

Figure 68. Clock Set Up Sequence (3) “L” time (1) of 150ns or more is needed to reset the AK4950. Wait time of 1ms or more is needed for the internal VCOM voltage rising. (7) Normal clock is output from the MCKO pin after PLL is locked. (8) Invalid clock is output from MCKO pin during this period. (9) BICK and LRCK clocks should be synchronized with MCKO clock. initialization must be executed when using ALC and Programmable Filter.

Figure 69. Clock Set Up Sequence (4) “L” time (1) of 150ns or more is needed to reset the AK4950. Wait time of 1ms or more is needed for the internal VCOM voltage rising. (4) Normal operation starts after the MCKI, LRCK and BICK are supplied. initializing time is 1/512fs x 18,000 [s]. INIT bit returns to “0” automatically when the initialization is finished. This initialization must be executed when using ALC and Programmable Filter.

Figure 72. Speaker-Amp Output Sequence At first, clocks should be supplied according to “Clock Set Up” sequence. value (0dB) in soft transition. When ALC bit is “0”, this volume can be used as a digital volume. (10) Power down DAC, MIN-Amp, Programmable Filter and Speaker-Amp.

Figure 73. Stereo Lineout Sequence At first, clocks should be supplied according to “Clock Set Up” sequence. operation by setting LOPS bit to “0”. LOUT and ROUT pins fall down to VSS1. Fall time is 300ms (max.) at C=1μF and AVDD=1.8V. LOPS bit should be set to “0” after LOUT and ROUT pins fall down.

Figure 74. “MIN-Amp Æ Speaker-Amp” Output Sequence When only the path of “MIN-Amp → SRK-Amp” is in operation, the clocks are not needed.

Figure 75. Video Output Sequence When only the video block is in operation, the clocks are not needed. (1) Set up the video gain (VG1-0 bits). The VOUT pin output is stopped and becomes 0V. Clocks Clocks can be stopped, if only video output is enabled.

[AK4950] MS1320-E-00 2011/10 - 104 - PACKAGE 32pin QFN (Unit: mm) 2.8 ± 0.1 0.4 16 25 4.0 ± 0.1 4.0 ± 0.1 0.35 ± 0.10 A B 17 24 Exposed Pad 0.40 ± 0.10 0.75 ± 0.05 C0.35 Note: The exposed pad on the bottom surface of the package must be connected to the ground. ■ Material & Lead Finish Package molding compound: Epoxy resin, Halogen (Br and Cl) free Lead frame material: Cu alloy Lead frame surface treatment: Solder (Pb free) plate

[AK4950] MS1320-E-00 2011/10 - 105 - MARKING 4950 XXXX XXXX: Date code (4 digit) Pin #1 indication Date (YY/MM/DD) Revision Reason Page Contents 11/10/13 00 First Edition

REVISION HISTORY

[AK4950] MS1320-E-00 2011/10 - 106 - IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility fo r such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.